IDT 89HPES16NT2 User manual

®
April 2008
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: [phone] • [phone] • FAX: [phone]
Printed in U.S.A.
©2008 Integrated Device Technology, Inc.
IDT™89HPES16NT2
PCI Express® Switch
User Manual

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Notes
PES16NT2 User Manual 1 April 15, 2008
®
About This Manual
Introduction
This user manual includes hardware and software information on the 89HPES16NT2, a member of
IDT’s PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect
standard.
Finding Additional Information
Informationnot includedin thismanual suchas mechanicals,package pin-outs,and electricalcharacter-
istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com)
as well as through your local IDT sales representative.
Content Summary
Chapter 1, “PES16NT2 Device Overview,” provides a complete introduction to the performance capa-
bilities of the 89HPES16NT2. Included in this chapter is a summary of features for the device as well as a
system block diagram and pin description.
Chapter 2, “Clocking, Reset, and Initialization,” provides a description of the two differential refer-
ence clock inputs that are used internally to generate all of the clocks required by the internal switch logic
and the SerDes.
Chapter 3, “Link Operation,” describes the operation of the link feature including polarity inversion,
link width negotiation, and lane reversal.
Chapter 4, “Switch Operation,” discusses the procedure for forwarding PCIe® TLPs between switch
ports.
Chapter 5, “Power Management,” describes thepower managementcapability structurelocated inthe
configuration space of each PCI-PCI bridge in the PES16NT2.
Chapter 6, “SMBus Interfaces,” describes the operation of the 2 SMBus interfaces on the PES16NT2.
Chapter 7, “NTB Upstream Port Failover,” describes the NTB upstream port failover mechanism that
enables the construction of fault tolerant systems.
Chapter 8, “General Purpose I/O,” describes how the eight General Purpose I/O (GPIO) pins may be
individually configured as general purpose inputs, general purpose outputs, or alternate functions
Chapter 9, “Transparent Mode Operation,” describes how the PES16NT2 can be configured during a
fundamental reset to operate in transparent mode or transparent mode with serial EEPROM initialization.
Chapter 10, “Non-Transparent Mode Operation,” describes how the PES16NT2 can be configured
during a fundamental reset to operate in non-transparent mode or non-transparent mode with serial
EEPROM initialization.
Chapter 11, “JTAG Boundary Scan,” discusses an enhanced JTAG interface, including a system logic
TAP controller, signal definitions, a test dataregister, an instruction register, and usage considerations.
Signal Nomenclature
To avoid confusion when dealing with a mixture of “active-low” and “active-high” signals, the terms
assertion and negation are used. The term assert or assertion is used to indicate that a signal is active or
true, independent of whether thatlevel is representedby a high or low voltage. The term negate or negation
is used to indicate that a signal is inactive or false.

IDT
PES16NT2 User Manual 2 April 15, 2008
Notes To define the active polarity of a signal, a suffix will be used. Signals ending with an ‘N’ should be inter-
preted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks,
buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level. To
define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will be on the
right. No leading zeros will be included.
Throughout this manual, when describing signal transitions, the following terminology is used. Rising
edgeindicates alow-to-high (0to 1)transition. Falling edge indicates a high-to-low (1 to0) transition.These
terms are illustrated in Figure 1.
Figure 1 Signal Transitions
Numeric Representations
To represent numerical values, either decimal, binary, or hexadecimal formats will be used. The binary
format is as follows: 0bDDD, where “D” represents either 0 or 1; the hexadecimal format is as follows:
0xDD, where “D” represents the hexadecimal digit(s); otherwise, it is decimal.
The compressed notation ABC[x|y|z]D refers to ABCxD, ABCyD, and ABCzD.
The compressed notation ABC[x..y]D refers to ABCxD, ABC(x+1)D, ABC(x+2)D,... ABCyD.
Data Units
The following data unit terminology is used in this document.
In quadwords, bit 63 is always the most significant bit and bit 0 is the least significant bit. In double-
words, bit 31 is always the most significant bit and bit 0 is the least significant bit. In words, bit 15is always
the most significant bit and bit 0 is the least significant bit. In bytes, bit 7 is always the most significant bit
and bit 0 is the least significant bit.
The ordering of bytes within words is referred to as either “big endian” or “little endian.” Big endian
systems label byte zero as the most significant (leftmost) byte of a word. Little endian systems label byte
zero as the least significant (rightmost) byte of a word. See Figure 2.
Term Words Bytes Bits
Byte 1/2 1 8
Word 1 2 16
Doubleword (Dword) 2 4 32
Quadword (Qword) 4 8 64
Table 1 Data Unit Terminology
1234
high-to-low
transition low-to-high
transition
single clock cycle

IDT
PES16NT2 User Manual 3 April 15, 2008
Notes
Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition
Register Terminology
Software in the context of this register terminology refers to modifications made by PCIe root configura-
tion writes, writes to registers made through the slave SMBus interface, or serial EEPROM register initial-
ization. See Table 2.
Type Abbreviation Description
Hardware Initialized HWINIT Register bits are initialized by firmware or hardware mechanisms
such as pin strapping or serial EEPROM. (System firmware hard-
ware initialization is only allowed for system integrated devices.)
Bits are read-only after initialization and can only be reset (for
write-once by firmware) with reset.
Read Only and Clear RC Software can read the register/bits with this attribute. Reading the
value will automatically cause the register/bit to be reset to zero.
Writing to a RC location has no effect.
Read Clear and Write RCW Software can read the register/bits with this attribute. Reading the
value will automatically cause the register/bits to be reset to zero.
Writes cause the register/bits to be modified.
Reserved Reserved The value read from a reserved register/bit is undefined. Thus,
software must deal correctly with fields that are reserved. On
reads,software mustuseappropriate maskstoextractthedefined
bits and not rely on reserved bits being any particular value. On
writes, software must ensure that the values of reserved bit posi-
tions are preserved. That is, the values of reserved bit positions
must first be read, merged with the new values for other bit posi-
tions and then written back.
Read Only RO Software can only read registers/bits with this attribute. Contents
are hardwired. Writing to a RO location has no effect.
Read Only and set by
Hardware ROS Software can only read registers/bits with this attribute. Contents are set by hardware and may change. Writing to a ROS location
has no effect.
Read and Write RW Software can both read and write bits with this attribute.
Table 2 Register Terminology (Sheet 1 of 2)
0123
bit 0bit 31
Address of Bytes within Words: Big Endian
3210
bit 0bit 31
Address of Bytes within Words: Little Endian

IDT
PES16NT2 User Manual 4 April 15, 2008
Notes
Use of Hypertext
In Chapters 9 and 10 there are tables which contain register names and page numbers highlighted in
blue under the Register Definition column. In pdf files, users can jump from the source table directly to the
registers by clicking on the register name in the source table. Each register name in the table is linked
directly to the appropriate register in the register section of the chapter. To return to the source table after
having jumped to the register section, click on the same register name (in blue) in the register section.
Revision History
April 15, 2008: Initial publication of user manual.
Read and Write Clear RW1C Software can read and write to registers/bits with this attribute.
However, writing a value of zero to a bit with this attribute has no
effect. A RW1C bit can only be set to a value of 1 by a hardware
event. To clear a RW1C bit (i.e., change its value to zero) a value
of one must be written to the location. An RW1C bit is never
cleared by hardware.
Read and Write when
Unlocked RWL Software can read the register/bits with this attribute. Writing to register/bits with this attribute will only cause the value to be modi-
fied if the REGUNLOCK bit in the SWCNTL register is set. When
the REGUNLOCK bit is cleared, writes are ignored and the regis-
ter/bits are effectively read-only
Zero Zero A zero register or bit must be written with a value of zero and
returns a value of zero when read.
Type Abbreviation Description
Table 2 Register Terminology (Sheet 2 of 2)

Notes
PES16NT2 User Manual i April 15, 2008
Table of Contents
®
About This Manual
Introduction ....................................................................................................................................1
Content Summary ..........................................................................................................................1
Signal Nomenclature .....................................................................................................................1
Numeric Representations ..............................................................................................................2
Data Units ......................................................................................................................................2
Register Terminology .....................................................................................................................3
Use of Hypertext ............................................................................................................................4
Revision History .............................................................................................................................4
PES16NT2 Device Overview
Introduction.....................................................................................................................................1-1
List of Features...............................................................................................................................1-3
System Identification.......................................................................................................................1-4
Vendor ID................................................................................................................................1-4
Device ID................................................................................................................................1-4
Revision ID.............................................................................................................................1-5
JTAG ID..................................................................................................................................1-5
Logic Diagram.................................................................................................................................1-6
Pin Description................................................................................................................................1-7
Pin Characteristics........................................................................................................................1-10
Clocking, Reset, and Initialization
Introduction.....................................................................................................................................2-1
Initialization.....................................................................................................................................2-3
Reset...............................................................................................................................................2-5
Fundamental Reset................................................................................................................2-7
Hot Reset................................................................................................................................2-8
Non-Transparent Mode Reset................................................................................................2-9
Link Operation
Introduction.....................................................................................................................................3-1
Polarity Inversion............................................................................................................................3-1
Link Width Negotiation....................................................................................................................3-1
Lane Reversal.................................................................................................................................3-1
Link Retraining................................................................................................................................3-4
Link Down.......................................................................................................................................3-4
Slot Power Limit Support................................................................................................................3-4
Crosslink.........................................................................................................................................3-5
Link Status......................................................................................................................................3-5

IDT Table of Contents
PES16NT2 User Manual ii April 15, 2008
Notes Switch Operation
Introduction.....................................................................................................................................4-1
Routing ...........................................................................................................................................4-3
Data Integrity ..................................................................................................................................4-4
Switch Time-Outs ...........................................................................................................................4-5
Interrupts.........................................................................................................................................4-5
Switch Core Errors..........................................................................................................................4-6
Power Management
Introduction.....................................................................................................................................5-1
PME Messages ......................................................................................................................5-2
Link States......................................................................................................................................5-2
Active State Power Management ...................................................................................................5-3
SMBus Interfaces
Introduction.....................................................................................................................................6-1
SMBus Registers............................................................................................................................6-2
Master SMBus Interface.................................................................................................................6-4
Initialization.............................................................................................................................6-4
Serial EEPROM......................................................................................................................6-4
Slave SMBus Interface...................................................................................................................6-8
Initialization.............................................................................................................................6-9
SMBus Transactions ..............................................................................................................6-9
NTB Upstream Port Failover
Introduction.....................................................................................................................................7-1
Failover...........................................................................................................................................7-2
Static Upstream Port Failover.................................................................................................7-3
Dynamic Upstream Port Failover............................................................................................7-3
General Purpose I/O
Introduction.....................................................................................................................................8-1
GPIO Registers...............................................................................................................................8-1
GPIO Configuration ........................................................................................................................8-2
GPIO Pin Configured as an Input...........................................................................................8-2
GPIO Pin Configured as an Output........................................................................................8-2
GPIO Pin Configured as an Alternate Function......................................................................8-2
Transparent Mode Operation
Introduction.....................................................................................................................................9-1
End-to-End CRC.............................................................................................................................9-2
Interrupts.........................................................................................................................................9-2
Error Detection and Handling .........................................................................................................9-2
Configuration Requests..........................................................................................................9-5
Port Configuration Space Organization..........................................................................................9-5
Upstream Port A Configuration Space Registers ...........................................................................9-7
PCI Express Capability Structure.........................................................................................9-19
Power Management Capability Structure.............................................................................9-26
Switch Control and Status Registers....................................................................................9-30
Extended Configuration Space Access and INTx Status Registers.....................................9-36
PCI Express Virtual Channel Capability...............................................................................9-37

IDT Table of Contents
PES16NT2 User Manual iii April 15, 2008
Notes Physical Layer Control and Status Registers.......................................................................9-42
Non-Transparent Mode Operation
Introduction...................................................................................................................................10-1
Transaction Routing......................................................................................................................10-3
Address Routing...................................................................................................................10-3
ID Routing.............................................................................................................................10-6
Route to Root Implicit Routing..............................................................................................10-6
Broadcast from Root Implicit Routing...................................................................................10-6
Local Terminate at Receiver Implicit Routing.......................................................................10-6
Gather and Route to Root Implicit Routing...........................................................................10-7
Non-Transparent Bridge Interprocessor Communications............................................................10-7
Message Registers...............................................................................................................10-7
Doorbell Registers................................................................................................................10-8
Scratchpad Registers...........................................................................................................10-8
Interrupts.......................................................................................................................................10-8
MSI and INTx Message Generation.....................................................................................10-8
Non-Transparent Bridge TLP Processing.....................................................................................10-9
Configuration ................................................................................................................................10-9
Configuration Space...........................................................................................................10-10
Memory Mapped Configuration Space...............................................................................10-11
Configuration Requests......................................................................................................10-11
End-to-End CRC.........................................................................................................................10-12
Error Detection and Handling .....................................................................................................10-12
Power Management....................................................................................................................10-15
Initializing the Non-Transparent Bridge ......................................................................................10-16
Non-Transparent Port C Configuration Space Organization.......................................................10-18
Non-Transparent Mode Downstream Port C Configuration Space Organization Registers.......10-19
Port C Registers .........................................................................................................................10-21
PCI Express Capability Structure.......................................................................................10-31
Power Management Capability Structure...........................................................................10-38
Switch Control and Status Registers..................................................................................10-41
Extended Configuration Space Access and INTx Status Registers...................................10-47
PCI Express Virtual Channel Capability.............................................................................10-48
Physical Layer Control and Status Registers.....................................................................10-53
NTB Endpoint Configuration Space Organization ......................................................................10-55
NTB Internal Endpoint Configuration Space Registers...............................................................10-56
Non-Transparent Bridge Internal Endpoint Registers.................................................................10-59
PCI Express Capability Structure.......................................................................................10-68
Message Signaled Interrupt Capability Structure...............................................................10-72
Non-Transparent Bridge Configuration Capability Structure..............................................10-73
Non-Transparent Bridge Communications Capability Structure.........................................10-89
Power Management Capability Structure...........................................................................10-95
Extended Configuration Space Access Registers..............................................................10-97
PCI Express Extended Capability Header..........................................................................10-97
Non-Transparent Bridge Control and Status Registers......................................................10-98
NTB External Endpoint Configuration Space Registers ...........................................................10-104
Non-Transparent Bridge External Endpoint Registers..............................................................10-107
PCI Express Capability Structure.....................................................................................10-116
Message Signaled Interrupt Capability Structure.............................................................10-120
Non-Transparent Bridge Configuration Capability Structure............................................10-121
Non-Transparent Bridge Communications Capability Structure.......................................10-137
Power Management Capability Structure.........................................................................10-143
Extended Configuration Space Access Registers............................................................10-145
PCI Express Extended Capability Header........................................................................10-145

IDT Table of Contents
PES16NT2 User Manual iv April 15, 2008
Notes Non-Transparent Bridge Control and Status Registers....................................................10-146
JTAG Boundary Scan
Introduction...................................................................................................................................11-1
Test Access Point.........................................................................................................................11-1
Signal Definitions..........................................................................................................................11-1
Boundary Scan Chain...................................................................................................................11-3
Test Data Register (DR)...............................................................................................................11-3
Boundary Scan Registers.....................................................................................................11-4
Instruction Register (IR)................................................................................................................11-5
EXTEST................................................................................................................................11-6
SAMPLE/PRELOAD.............................................................................................................11-6
BYPASS...............................................................................................................................11-6
CLAMP.................................................................................................................................11-7
IDCODE................................................................................................................................11-7
VALIDATE............................................................................................................................11-7
RESERVED..........................................................................................................................11-7
Usage Considerations..........................................................................................................11-7

Notes
PES16NT2 User Manual v April 15, 2008
List of Tables
®
Table 1.1 PES16NT2 Offset Device IDs..............................................................................................1-4
Table 1.2 PES16NT2 Revision IDs......................................................................................................1-5
Table 1.3 PCI Express Interface Pins..................................................................................................1-7
Table 1.4 SMBus Interface Pins..........................................................................................................1-7
Table 1.5 General Purpose I/O Pins....................................................................................................1-8
Table 1.6 System Pins.........................................................................................................................1-8
Table 1.7 Test Pins..............................................................................................................................1-9
Table 1.8 Power and Ground Pins.......................................................................................................1-9
Table 1.9 Pin Characteristics.............................................................................................................1-10
Table 2.1 Reference Clock Mode Encoding........................................................................................2-1
Table 2.2 Boot Configuration Vector Signals.......................................................................................2-3
Table 2.3 System Pins.........................................................................................................................2-4
Table 2.4 Reset Conditions and Their Effect.......................................................................................2-5
Table 4.1 PES16NT2 Buffer Sizes......................................................................................................4-1
Table 4.2 PES16NT2 Advertised Flow Control Credits.......................................................................4-2
Table 4.3 Switch Routing Methods......................................................................................................4-3
Table 4.4 PCI Compatible INTx Aggregation.......................................................................................4-6
Table 4.5 PES16NT2 Upstream Port Bridge Interrupt Mapping..........................................................4-6
Table 5.1 PES16NT2 Power Management State Transition Diagram.................................................5-2
Table 6.1 SMBUSSTS - SMBus Status...............................................................................................6-2
Table 6.2 SMBUSCTL - SMBus Control..............................................................................................6-3
Table 6.3 Serial EEPROM SMBus Address........................................................................................6-4
Table 6.4 Base Addresses for PCI Configuration Spaces in the PES16NT2......................................6-5
Table 6.5 PES16NT2 Compatible Serial EEPROMs...........................................................................6-5
Table 6.6 Serial EEPROM Initialization Errors....................................................................................6-8
Table 6.7 Slave SMBus Address When a Static Address is Selected.................................................6-9
Table 6.8 Slave SMBus Command Code Fields ...............................................................................6-10
Table 6.9 CSR Register Read or Write Operation Byte Sequence...................................................6-11
Table 6.10 CSR Register Read or Write CMD Field Description.........................................................6-11
Table 6.11 Serial EEPROM Read or Write Operation Byte Sequence................................................6-12
Table 6.12 Serial EEPROM Read or Write CMD Field Description.....................................................6-13
Table 8.1 General Purpose IO Registers.............................................................................................8-1
Table 8.2 General Purpose I/O Pin Alternate Function.......................................................................8-2
Table 8.3 GPIO Pin Configuration.......................................................................................................8-2
Table 9.1 Physical Layer Errors...........................................................................................................9-2
Table 9.2 Data Link Layer Errors.........................................................................................................9-2
Table 9.3 Transaction Layer Errors.....................................................................................................9-3
Table 9.4 Malformed TLP Error Checks..............................................................................................9-4
Table 9.5 Upstream Port A Configuration Space Registers................................................................9-7
Table 10.1 Non-Transparent Bridge Mapping Table Fields.................................................................10-4
Table 10.2 Physical Layer Errors.......................................................................................................10-12
Table 10.3 Data Link Layer Errors.....................................................................................................10-13
Table 10.4 Transaction Layer Errors.................................................................................................10-13
Table 10.5 Malformed TLP Error Checks..........................................................................................10-14
Table 10.6 Downstream Port C Configuration Space Registers in Non-Transparent Mode..............10-19
Table 10.7 Non-Transparent Bridge Internal Endpoint Configuration Space Registers....................10-56
Table 10.8 Non-Transparent Bridge External Endpoint Configuration Space Registers.................10-104
Table 11.1 JTAG Pin Descriptions.......................................................................................................11-2
Table 11.2 Boundary Scan Chain........................................................................................................11-3

IDT List of Tables
PES16NT2 User Manual vi April 15, 2008
Notes Table 11.3 Instructions Supported by PES16NT2’s JTAG Boundary Scan ........................................11-6
Table 11.4 System Controller Device Identification Register ..............................................................11-7

Notes
PES16NT2 User Manual vii April 15, 2008
List of Figures
®
Figure 1.1 PES16NT2 Functional Block Diagram ...............................................................................1-2
Figure 1.2 PES16NT2 Architectural Block Diagram ............................................................................1-3
Figure 1.3 PES16NT2 Logic Diagram .................................................................................................1-6
Figure 2.1 Common Clock on Upstream and Downstream (option to enable or disable Spread
Spectrum Clock) ................................................................................................................2-1
Figure 2.2 Non-Common Clock on Upstream; Common Clock on Downstream (must disable
Spread Spectrum Clock) ....................................................................................................2-2
Figure 2.3 Common Clock on Upstream; Non-Common Clock on Downstream (must disable
Spread Spectrum Clock) ....................................................................................................2-2
Figure 2.4 Non-Common Clock on Upstream and Downstream (must disable Spread Spectrum
Clock) .................................................................................................................................2-3
Figure 2.5 Fundamental Reset in Transparent Mode with Serial EEPROM initialization ....................2-8
Figure 3.1 Lane Reversal for Maximum Link Width of x8 ....................................................................3-2
Figure 3.2 Lane Reversal for Maximum Link Width of x4 ....................................................................3-3
Figure 3.3 Lane Reversal for Maximum Link Width of x2 ....................................................................3-4
Figure 4.1 PES16NT2 Switch Data Flow and Buffering ......................................................................4-1
Figure 5.1 PES16NT2 Power Management State Transition Diagram ...............................................5-1
Figure 5.2 PES16NT2 ASPM Link Sate Transitions ...........................................................................5-3
Figure 6.1 SMBus Interface Configuration Examples .........................................................................6-1
Figure 6.2 Single Double Word Initialization Sequence Format ..........................................................6-6
Figure 6.3 Sequential Double Word Initialization Sequence Format ...................................................6-6
Figure 6.4 Configuration Done Sequence Format ..............................................................................6-7
Figure 6.5 Slave SMBus Command Code Format ..............................................................................6-9
Figure 6.6 CSR Register Read or Write CMD Field Format ..............................................................6-11
Figure 6.7 Serial EEPROM Read or Write CMD Field Format ..........................................................6-12
Figure 6.8 CSR Register Read Using SMBus Block Write/Read Transactions with PEC
Disabled ...........................................................................................................................6-13
Figure 6.9 Serial EEPROM Read Using SMBus Block Write/Read Transactions with PEC
Disabled ...........................................................................................................................6-14
Figure 6.10 CSR Register Write Using SMBus Block Write Transactions with PEC Disabled ...........6-14
Figure 6.11 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled ........6-14
Figure 6.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled ........6-14
Figure 6.13 CSR Register Read Using SMBus Read and Write Transactions with PEC Disabled ....6-15
Figure 7.1 NTB Upstream Port Failover Usage Model ........................................................................7-1
Figure 7.2 PES16NT2 NTB Upstream Port Failover Architecture .......................................................7-2
Figure 9.1 PES16NT2 Functional Block Diagram in Transparent Mode .............................................9-1
Figure 10.1 PES16NT2 Functional Block Diagram in Non-Transparent Mode ...................................10-2
Figure 10.2 Internal and External Endpoint Non-Transparent Bridge Mapping Table Format ............10-3
Figure 10.3 NTB Base and Limit Address Translation ........................................................................10-5
Figure 10.4 Non-Transparent Bridge Interprocessor Communications Facilities ................................10-7
Figure 10.5 Non-Transparent Bridge Configuration Window ............................................................10-10
Figure 10.6 Port C Configuration Space Organization in Non-Transparent Mode ............................10-18
Figure 10.7 Non-Transparent Bridge Endpoint Configuration Space Layout ....................................10-55
Figure 11.1 Diagram of the JTAG Logic ..............................................................................................11-1
Figure 11.2 State Diagram of PES16NT2’s TAP Controller ................................................................11-2
Figure 11.3 Diagram of Observe-only Input Cell .................................................................................11-4
Figure 11.4 Diagram of Output Cell ....................................................................................................11-4
Figure 11.5 Diagram of Bidirectional Cell ............................................................................................11-5
Figure 11.6 Device ID Register Format ...............................................................................................11-7

DT List of Figures
PES16NT2 User Manual viii April 15, 2008
Notes

Notes
PES16NT2 User Manual ix April 15, 2008
Register List
®
PA_BAR0 - Base Address Register 0 (0x010).......................................................................................9-13
PA_BAR1 - Base Address Register 1 (0x014).......................................................................................9-13
PA_BCTRL - Bridge Control (0x03E)..................................................................................................... 9-18
PA_BIST - Built-in Self Test (0x00F)...................................................................................................... 9-12
PA_CAPPTR - Capabilities Pointer (0x034)........................................................................................... 9-17
PA_CCODE - Class Code (0x009)......................................................................................................... 9-12
PA_CLS - Cache Line Size (0x00C) ...................................................................................................... 9-12
PA_DID - Device Identification (0x002).................................................................................................... 9-9
PA_ECFGADDR - Extended Configuration Space Access Address (0x0F8)........................................ 9-36
PA_ECFGDATA - Extended Configuration Space Access Data (0x0FC).............................................. 9-37
PA_EEPROMINTF - Serial EEPROM Interface (0x0B4)........................................................................ 9-35
PA_EROMBASE - Expansion ROM Base Address (0x038) .................................................................. 9-17
PA_GPIOCS - General Purpose I/O Control and Status (0x0A8).......................................................... 9-32
PA_HDR - Header Type (0x00E)........................................................................................................... 9-12
PA_INTRLINE - Interrupt Line (0x03C).................................................................................................. 9-17
PA_INTRPIN - Interrupt PIN (0x03D)..................................................................................................... 9-18
PA_INTSTS - Interrupt Status (0x0F4)................................................................................................... 9-36
PA_IOBASE - I/O Base (0x01C)............................................................................................................ 9-14
PA_IOBASEU - I/O Base Upper (0x030) ............................................................................................... 9-17
PA_IOLIMIT - I/O Limit (0x01D)............................................................................................................. 9-14
PA_IOLIMITU - I/O Limit Upper (0x032) ................................................................................................ 9-17
PA_MBASE - Memory Base (0x020) ..................................................................................................... 9-15
PA_MLIMIT - Memory Limit (0x022)....................................................................................................... 9-15
PA_PBUSN - Primary Bus Number (0x018)...........................................................................................9-13
PA_PCICMD - PCI Command (0x004)..................................................................................................... 9-9
PA_PCIECAP - PCI Express Capability (0x040).................................................................................... 9-19
PA_PCIEDCAP - PCI Express Device Capabilities (0x044) .................................................................. 9-19
PA_PCIEDCTL - PCI Express Device Control (0x048).......................................................................... 9-20
PA_PCIEDSTS - PCI Express Device Status (0x04A)........................................................................... 9-21
PA_PCIELCAP - PCI Express Link Capabilities (0x04C)....................................................................... 9-22
PA_PCIELCTL - PCI Express Link Control (0x050)............................................................................... 9-23
PA_PCIELSTS - PCI Express Link Status (0x052)................................................................................ 9-23
PA_PCIESCAP - PCI Express Slot Capabilities (0x054) ....................................................................... 9-24
PA_PCIESCTL - PCI Express Slot Control (0x058)............................................................................... 9-25
PA_PCIESSTS - PCI Express Slot Status (0x05A)................................................................................ 9-25
PA_PCIEVCECAP - PCI Express Virtual Channel Enhanced Capability Header (0x100)..................... 9-37
PA_PCISTS - PCI Status (0x006).......................................................................................................... 9-10
PA_PLTIMER - Primary Latency Timer (0x00D).................................................................................... 9-12
PA_PMBASE - Prefetchable Memory Base (0x024).............................................................................. 9-15
PA_PMBASEU - Prefetchable Memory Base Upper (0x028)................................................................. 9-16
PA_PMCAP - PCI Power Management Capabilities (0x070)................................................................. 9-26
PA_PMCSR - PCI Power Management Control and Status (0x074)..................................................... 9-27
PA_PMLIMIT - Prefetchable Memory Limit (0x026)............................................................................... 9-16
PA_PMLIMITU - Prefetchable Memory Limit Upper (0x02C)................................................................. 9-16
PA_PMPC - PCI Power Management Proprietary Control (0x078)........................................................9-27
PA_PVCCAP1- Port VC Capability 1 (0x104)........................................................................................9-37
PA_RID - Revision Identification (0x008)............................................................................................... 9-11
PA_SBUSN - Secondary Bus Number (0x019)...................................................................................... 9-13
PA_SECSTS - Secondary Status (0x01E)............................................................................................. 9-14

IDT Register List
PES16NT2 User Manual x April 15, 2008
Notes PA_SERDESCTL - SerDes Control (0x200)...........................................................................................9-42
PA_SLTIMER - Secondary Latency Timer (0x01B)................................................................................9-13
PA_SMBUSCTL - SMBus Control (0x0B0).............................................................................................9-34
PA_SMBUSSTS - SMBus Status (0x0AC)..............................................................................................9-33
PA_SUBUSN - Subordinate Bus Number (0x01A) .................................................................................9-13
PA_SWCTL - Switch Control (0x0A4).....................................................................................................9-31
PA_SWSTS Switch Status (0x0A0) ........................................................................................................9-30
PA_VCR0CAP- VC Resource 0 Capability (0x110)................................................................................9-38
PA_VCR0CTL- VC Resource 0 Control (0x114).....................................................................................9-38
PA_VCR0STS - VC Resource 0 Status (0x118).....................................................................................9-39
PA_VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x120).......................................................9-40
PA_VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x124).......................................................9-41
PA_VID - Vendor Identification (0x000) ....................................................................................................9-9
PC_BAR0 - Base Address Register 0 (0x010)......................................................................................10-25
PC_BAR1 - Base Address Register 1 (0x014)......................................................................................10-25
PC_BCTRL - Bridge Control (0x03E)....................................................................................................10-30
PC_BIST - Built-in Self Test (0x00F).....................................................................................................10-24
PC_CAPPTR - Capabilities Pointer (0x034) .........................................................................................10-29
PC_CCODE - Class Code (0x009) .......................................................................................................10-24
PC_CLS - Cache Line Size (0x00C).....................................................................................................10-24
PC_DID - Device Identification (0x002).................................................................................................10-21
PC_ECFGADDR - Extended Configuration Space Access Address (0x0F8).......................................10-47
PC_ECFGDATA - Extended Configuration Space Access Data (0x0FC).............................................10-48
PC_EEPROMINTF - Serial EEPROM Interface (0x0B4)......................................................................10-46
PC_EROMBASE - Expansion ROM Base Address (0x038).................................................................10-29
PC_GPIOCS - General Purpose I/O Control and Status (0x0A8).........................................................10-43
PC_HDR - Header Type (0x00E)..........................................................................................................10-24
PC_INTRLINE - Interrupt Line (0x03C).................................................................................................10-30
PC_INTRPIN - Interrupt PIN (0x03D)....................................................................................................10-30
PC_INTSTS - Interrupt Status (0x0F4) .................................................................................................10-47
PC_IOBASE - I/O Base (0x01C)...........................................................................................................10-26
PC_IOBASEU - I/O Base Upper (0x030)..............................................................................................10-29
PC_IOLIMIT - I/O Limit (0x01D)............................................................................................................10-26
PC_IOLIMITU - I/O Limit Upper (0x032)...............................................................................................10-29
PC_MBASE - Memory Base (0x020)....................................................................................................10-27
PC_MLIMIT - Memory Limit (0x022).....................................................................................................10-27
PC_PBUSN - Primary Bus Number (0x018).........................................................................................10-25
PC_PCICMD - PCI Command (0x004).................................................................................................10-21
PC_PCIECAP - PCI Express Capability (0x040) ..................................................................................10-31
PC_PCIEDCAP - PCI Express Device Capabilities (0x044).................................................................10-31
PC_PCIEDCTL - PCI Express Device Control (0x048).........................................................................10-32
PC_PCIEDSTS - PCI Express Device Status (0x04A) .........................................................................10-33
PC_PCIELCAP - Port C NTB Mode PCI Express Link Capabilities (0x04C)........................................10-34
PC_PCIELCTL - Port C NTB Mode PCI Express Link Control (0x050)................................................10-35
PC_PCIELSTS - Port C NTB Mode PCI Express Link Status (0x052) .................................................10-36
PC_PCIESCAP - Port C NTB Mode PCI Express Slot Capabilities (0x054).........................................10-36
PC_PCIESCTL - Port C NTB Mode PCI Express Slot Control (0x058)................................................10-37
PC_PCIESSTS - Port C NTB Mode PCI Express Slot Status (0x5A)...................................................10-37
PC_PCIEVCECAP - PCI Express Virtual Channel Enhanced Capability Header (0x100) ...................10-48
PC_PCISTS - PCI Status (0x006).........................................................................................................10-22
PC_PLTIMER - Primary Latency Timer (0x00D)...................................................................................10-24
PC_PMBASE - Prefetchable Memory Base (0x024).............................................................................10-28
PC_PMBASEU - Prefetchable Memory Base Upper (0x028)...............................................................10-28
PC_PMCAP - PCI Power Management Capabilities (0x070) ...............................................................10-38
PC_PMCSR - PCI Power Management Control and Status (0x074)....................................................10-38

IDT Register List
PES16NT2 User Manual xi April 15, 2008
Notes PC_PMLIMIT - Prefetchable Memory Limit (0x026)..............................................................................10-28
PC_PMLIMITU - Prefetchable Memory Limit Upper (0x02C)................................................................10-29
PC_PMPC - PCI Power Management Proprietary Control (0x078)......................................................10-39
PC_PVCCAP1- Port VC Capability 1 (0x104).......................................................................................10-48
PC_RID - Revision Identification (0x008)..............................................................................................10-23
PC_SBUSN - Secondary Bus Number (0x019) ....................................................................................10-25
PC_SECSTS - Secondary Status (0x01E)............................................................................................10-26
PC_SERDESCTL - SerDes Control (0x200).........................................................................................10-53
PC_SLTIMER - Secondary Latency Timer (0x01B)..............................................................................10-25
PC_SMBUSCTL - SMBus Control (0x0B0)...........................................................................................10-45
PC_SMBUSSTS - SMBus Status (0x0AC) ...........................................................................................10-44
PC_SUBUSN - Subordinate Bus Number (0x01A)...............................................................................10-25
PC_SWCTL - Switch Control (0x0A4)...................................................................................................10-42
PC_SWSTS Switch Status (0x0A0)......................................................................................................10-41
PC_VCR0CAP- VC Resource 0 Capability (0x110)..............................................................................10-49
PC_VCR0CTL- VC Resource 0 Control (0x114)...................................................................................10-49
PC_VCR0STS - VC Resource 0 Status (0x118)...................................................................................10-50
PC_VCR0TBL0 - VC Resource 0 Arbitration Table Entry 0 (0x120).....................................................10-51
PC_VCR0TBL1 - VC Resource 0 Arbitration Table Entry 1 (0x124).....................................................10-52
PC_VID - Vendor Identification (0x000)................................................................................................10-21
PCEE_BAR0 - Base Address Register 0 (0x010)...............................................................................10-111
PCEE_BAR1 - Base Address Register 1 (0x014)...............................................................................10-112
PCEE_BAR2 - Base Address Register 2 (0x018)...............................................................................10-112
PCEE_BAR3 - Base Address Register 3 (0x01C) ..............................................................................10-113
PCEE_BAR4 - Base Address Register 4 (0x020)...............................................................................10-114
PCEE_BARSETUP0 - BAR 0 Setup (0x07C) .....................................................................................10-125
PCEE_BARSETUP1 - BAR 1 Setup (0x084)......................................................................................10-127
PCEE_BARSETUP2 - BAR 2 Setup (0x08C) .....................................................................................10-129
PCEE_BARSETUP3 - BAR 3 Setup (0x094)......................................................................................10-131
PCEE_BARSETUP4 - BAR 4 Setup (0x09C) .....................................................................................10-133
PCEE_BARTBASE0 - BAR 0 Translated Base Address (0x080).......................................................10-126
PCEE_BARTBASE1 - BAR 1 Translated Base Address (0x088).......................................................10-128
PCEE_BARTBASE2 - BAR 2 Translated Base Address (0x090).......................................................10-130
PCEE_BARTBASE3 - BAR 3 Translated Base Address (0x098).......................................................10-132
PCEE_BARTLIMIT0 - BAR 0 Translated Limit Address (0x218)........................................................10-150
PCEE_BARTLIMIT1 - BAR 1 Translated Limit Address (0x21C)........................................................10-151
PCEE_BARTLIMIT2 - BAR 2 Translated Limit Address (0x220)........................................................10-151
PCEE_BARTLIMIT3 - BAR 3 Translated Limit Address (0x224)........................................................10-151
PCEE_BIST - Built-on Self Test (0x00F).............................................................................................10-111
PCEE_CAPPTR - Capabilities Pointer (0x034)...................................................................................10-115
PCEE_CCODE - Class Code (0x009).................................................................................................10-110
PCEE_CLS - Cache Line Size (0x00C) ..............................................................................................10-110
PCEE_DID - Device Identification (0x002)..........................................................................................10-107
PCEE_ECFGADDR - Extended Configuration Space Access Address (0x0F8)................................10-145
PCEE_ECFGDATA - Extended Configuration Space Access Data (0x0FC)......................................10-145
PCEE_FOVRCTL - Failover Control (0x22C) .....................................................................................10-152
PCEE_FOVRSTS - Failover Status (0x228).......................................................................................10-152
PCEE_FOVRTIMER - Failover Watchdog Timer (0x230)...................................................................10-153
PCEE_HDR - Header Type (0x00E)...................................................................................................10-110
PCEE_INDBELL - Inbound Doorbell (0x0E0) .....................................................................................10-138
PCEE_INMSG[0|1|2|3] - Inbound Message [0|1|2|3] (0x0B8-0C4).....................................................10-137
PCEE_INTCTL0 - Interrupt Control 0 (0x0EC)....................................................................................10-140
PCEE_INTCTL1 - Interrupt Control 1 (0x210).....................................................................................10-146
PCEE_INTRLINE - Interrupt Line (0x03C)..........................................................................................10-115
PCEE_INTRPIN - Interrupt PIN (0x03D).............................................................................................10-115

IDT Register List
PES16NT2 User Manual xii April 15, 2008
Notes PCEE_INTSTS - Interrupt Status (0x0E8) ..........................................................................................10-138
PCEE_MAXLAT - Maximum Latency (0x03F) ....................................................................................10-116
PCEE_MINGNT - Minimum Grant (0x03E).........................................................................................10-115
PCEE_MLTIMER - Master Latency Timer (0x00D).............................................................................10-110
PCEE_MSIADDR - Message Signaled Interrupt Address (0x068) .....................................................10-121
PCEE_MSICAP - Message Signaled Interrupt Capability and Control (0x064)..................................10-120
PCEE_MSIMDATA - Message Signaled Interrupt Message Data (0x070).........................................10-121
PCEE_MSIUADDR - Message Signaled Interrupt Upper Address (0x06C) .......................................10-121
PCEE_MTADDR - Mapping Table Address (0x0AC)..........................................................................10-135
PCEE_MTDATA - Mapping Table DATA (0x0B0)...............................................................................10-136
PCEE_NTBCFG - Non-Transparent Bridge Configuration (0x200) ....................................................10-146
PCEE_NTBCFGC - Non-Transparent Bridge Configuration Capability (0x074).................................10-121
PCEE_NTBCOMC - Non-Transparent Bridge Communications Capability (0x0B4) ..........................10-137
PCEE_NTBCTL - Non-Transparent Bridge Control (0x078)...............................................................10-122
PCEE_NTBEPID - Non-Transparent Bridge Endpoint Identification (0x07A).....................................10-124
PCEE_NTBSTS - Non-Transparent Bridge Status (0x079)................................................................10-123
PCEE_OUTDBELL - Outbound Doorbell (0x0E4)...............................................................................10-138
PCEE_OUTMSG[0|1|2|3] - Outbound Message [0|1|2|3] (0x0C8-0D4)..............................................10-137
PCEE_PCICMD - PCI Command (0x004) ..........................................................................................10-108
PCEE_PCIECAP - PCI Express Capability (0x040)............................................................................10-116
PCEE_PCIEDCAP - PCI Express Device Capabilities (0x044)..........................................................10-116
PCEE_PCIEDCTL - PCI Express Device Control (0x048)..................................................................10-117
PCEE_PCIEDSTS PCI Express Device Status (0x04A).....................................................................10-118
PCEE_PCIEECAP - PCI Express Extended Capability (0x100).........................................................10-145
PCEE_PCIELCAP - PCI Express Link Capabilities (0x04C)...............................................................10-119
PCEE_PCIELCTL - PCI Express Link Control (0x050).......................................................................10-119
PCEE_PCIELSTS - PCI Express Link Status (0x052)........................................................................10-120
PCEE_PCISTS - PCI Status (0x006)..................................................................................................10-109
PCEE_PMCAP - PCI Power Management Capabilities (0x0F0) ........................................................10-143
PCEE_PMCSR - PCI Power Management Control and Status (0x0F4).............................................10-144
PCEE_PTCCFG - Punch Through Configuration Control (0x0A0) .....................................................10-133
PCEE_PTCDATA - Punch Through Configuration Data (0x0A4) .......................................................10-134
PCEE_PTCSTS - Punch Through Configuration Status (0x0A8) .......................................................10-135
PCEE_RID - Revision Identification (0x008).......................................................................................10-110
PCEE_SCRATCHPAD[0..1] - Scratchpad [0..1] (0x0D8-ODC) ..........................................................10-138
PCEE_SUBID - Subsystem ID Pointer (0x02E)..................................................................................10-115
PCEE_SUBVID - Subsystem Vendor ID Pointer (0x02C)...................................................................10-115
PCEE_TLPPCTL - TLP Processing Control (0x214) ..........................................................................10-150
PCEE_VID - Vendor Identification (0x000) .........................................................................................10-107
PCIE_BAR0 - Base Address Register 0 (0x010) ..................................................................................10-63
PCIE_BAR1 - Base Address Register 1 (0x014) ..................................................................................10-64
PCIE_BAR2 - Base Address Register 2 (0x018) ..................................................................................10-64
PCIE_BAR3 - Base Address Register 3 (0x01C)..................................................................................10-65
PCIE_BAR4 - Base Address Register 4 (0x020) ..................................................................................10-66
PCIE_BARSETUP0 - BAR 0 Setup (0x07C).........................................................................................10-77
PCIE_BARSETUP1 - BAR 1 Setup (0x084) .........................................................................................10-79
PCIE_BARSETUP2 - BAR 2 Setup (0x08C).........................................................................................10-81
PCIE_BARSETUP3 - BAR 3 Setup (0x094) .........................................................................................10-83
PCIE_BARSETUP4 - BAR 4 Setup (0x09C).........................................................................................10-85
PCIE_BARTBASE0 - BAR 0 Translated Base Address (0x080)...........................................................10-78
PCIE_BARTBASE1 - BAR 1 Translated Base Address (0x088)...........................................................10-80
PCIE_BARTBASE2 - BAR 2 Translated Base Address (0x090)...........................................................10-82
PCIE_BARTBASE3 - BAR 3 Translated Base Address (0x098)...........................................................10-84
PCIE_BARTLIMIT0 - BAR 0 Translated Limit Address (0x218)..........................................................10-102
PCIE_BARTLIMIT1 - BAR 1 Translated Limit Address (0x21C).........................................................10-103

IDT Register List
PES16NT2 User Manual xiii April 15, 2008
Notes PCIE_BARTLIMIT2 - BAR 2 Translated Limit Address (0x220)..........................................................10-103
PCIE_BARTLIMIT3 - BAR 3 Translated Limit Address (0x224)..........................................................10-103
PCIE_BIST - Built-on Self Test (0x00F)................................................................................................10-63
PCIE_CAPPTR - Capabilities Pointer (0x034)......................................................................................10-67
PCIE_CCODE - Class Code (0x009)....................................................................................................10-62
PCIE_CLS - Cache Line Size (0x00C)..................................................................................................10-62
PCIE_DID - Device Identification (0x002).............................................................................................10-59
PCIE_ECFGADDR - Extended Configuration Space Access Address (0x0F8)....................................10-97
PCIE_ECFGDATA - Extended Configuration Space Access Data (0x0FC).........................................10-97
PCIE_HDR - Header Type (0x00E).......................................................................................................10-62
PCIE_INDBELL - Inbound Doorbell (0x0E0).........................................................................................10-90
PCIE_INMSG[0|1|2|3] - Inbound Message [0|1|2|3] (0x0B8-0C4)........................................................10-89
PCIE_INTCTL0 - Interrupt Control 0 (0x0EC).......................................................................................10-92
PCIE_INTCTL1 - Interrupt Control 1 (0x210)........................................................................................10-98
PCIE_INTRLINE - Interrupt Line (0x03C) .............................................................................................10-67
PCIE_INTRPIN - Interrupt PIN (0x03D)................................................................................................10-67
PCIE_INTSTS - Interrupt Status (0x0E8)..............................................................................................10-90
PCIE_MAXLAT - Maximum Latency (0x03F)........................................................................................10-68
PCIE_MINGNT - Minimum Grant (0x03E) ............................................................................................10-67
PCIE_MLTIMER - Master Latency Timer (0x00D)................................................................................10-62
PCIE_MSIADDR - Message Signaled Interrupt Address (0x068).........................................................10-73
PCIE_MSICAP - Message Signaled Interrupt Capability and Control (0x064).....................................10-72
PCIE_MSIMDATA - Message Signaled Interrupt Message Data (0x070) ............................................10-73
PCIE_MSIUADDR - Message Signaled Interrupt Upper Address (0x06C)...........................................10-73
PCIE_MTADDR - Mapping Table Address (0x0AC).............................................................................10-87
PCIE_MTDATA - Mapping Table DATA (0x0B0)..................................................................................10-88
PCIE_NTBCFG - Non-Transparent Bridge Configuration (0x200)........................................................10-98
PCIE_NTBCFGC - Non-Transparent Bridge Configuration Capability (0x074) ....................................10-73
PCIE_NTBCOMC - Non-Transparent Bridge Communications Capability (0x0B4)..............................10-89
PCIE_NTBCTL - Non-Transparent Bridge Control (0x078) ..................................................................10-74
PCIE_NTBEPID - Non-Transparent Bridge Endpoint Identification (0x07A).........................................10-76
PCIE_NTBSTS - Non-Transparent Bridge Status (0x079)....................................................................10-75
PCIE_OUTDBELL - Outbound Doorbell (0x0E4)..................................................................................10-90
PCIE_OUTMSG[0|1|2|3] - Outbound Message [0|1|2|3] (0x0C8-0D4) .................................................10-89
PCIE_PCICMD - PCI Command (0x004)..............................................................................................10-59
PCIE_PCIECAP - PCI Express Capability (0x040)...............................................................................10-68
PCIE_PCIEDCAP - PCI Express Device Capabilities (0x044)..............................................................10-68
PCIE_PCIEDCTL - PCI Express Device Control (0x048).....................................................................10-69
PCIE_PCIEDSTS - PCI Express Device Status (0x04A)......................................................................10-70
PCIE_PCIEECAP - PCI Express Extended Capability (0x100) ............................................................10-97
PCIE_PCIELCAP - PCI Express Link Capabilities (0x04C)..................................................................10-71
PCIE_PCIELCTL - PCI Express Link Control (0x050)..........................................................................10-71
PCIE_PCIELSTS - PCI Express Link Status (0x052) ...........................................................................10-72
PCIE_PCISTS - PCI Status (0x006) .....................................................................................................10-61
PCIE_PMCAP - PCI Power Management Capabilities (0x0F0)............................................................10-95
PCIE_PMCSR - PCI Power Management Control and Status (0x0F4) ................................................10-96
PCIE_PTCCFG - Punch Through Configuration Control (0x0A0).........................................................10-85
PCIE_PTCDATA - Punch Through Configuration Data (0x0A4)...........................................................10-86
PCIE_PTCSTS - Punch Through Configuration Status (0x0A8)...........................................................10-87
PCIE_RID - Revision Identification (0x008) ..........................................................................................10-62
PCIE_SCRATCHPAD[0..1] - Scratchpad [0..1] (0x0D8-ODC)..............................................................10-90
PCIE_SUBID - Subsystem ID Pointer (0x02E) .....................................................................................10-67
PCIE_SUBVID - Subsystem Vendor ID Pointer (0x02C)......................................................................10-67
PCIE_TLPPCTL - TLP Processing Control (0x214)............................................................................10-102
PCIE_VID - Vendor Identification (0x000).............................................................................................10-59

IDT Register List
PES16NT2 User Manual xiv April 15, 2008
Notes