IMS 740 User manual

IMS INTERNATIONAL
MODEL 740
I/O PROCESSORBOARD
* A
GENERAL DESCRIPTION
The Model 740I/O PROCESSOR isa singleboardcomputer with a Z-80A processor,
64K bytes of Dynamic RAM with Parity, 2K bytes of IPL PROM, Two programmable
Synchronous/Asynchronous communication channelswith MODEM control, Ten
programmable parallel I/O linescompatible with Bell 801 AutomaticCalling Unit, Four
intervaltimers ( two used for baud rates), Z-80 internally-prioritized vectored
interruptstructure, and Parallelinterface tothe S-100 BUS Host processor.
The Z-80A SIO interfaces the Z-80A CPUtoTwo asynchronous or synchronousSerial
DataChannels. TheSIO converts input serialdata from the RS-232Cport to parallel
data tobe acted upon bythe system.Outputdata is converted from parallel to
serial data tobe placed onthe RS-232C port.
The 8255A Programmable PeripheralInterfacecircuitinterfaces the S-100 BUStothe
slave Z-80 A CPU bus.
The MODEL 740I/O Processorconsists ofa singleprintedcircuitboard that occupies
one slot inthe Series 5000 or 8000 ComputerSystems.Eachserial RS-232C port is
brought outtoa 3M 26-pin header. The RS-232C ports are designed as DataTerminal
Equipment (DTE) to connectdirectly toa MODEM. To connect a terminaldirectly to
the RS-232C port(DTE to DTE) the RS-232Ccablewires must be interchanged for
properoperation of terminal.
S-100 BUS TOI/O PROCESSORINTERFACE
8255A Mode 2 S-100 BUSto Slave Z-80A CPU Interface
Due tothe drasticreduction of hardware costs, systemdesigns which utilizemultiple
CPU modules are becoming more common. A Model 451 Z-80A CPUis configured as
the masterS-100 CPUand used to control multiple Z-80A slave modules which actas
intelligent I/O controllers. When multiple CPUs are utilized, a method of processor
intercommunication must be supported. TheIMS740 Z-80A module is implemented asa
master/slaveinterfacethrough theuseofthe 8255A Mode 2 bidirectionalbus.
The S-100 BUS interface is supported byan 8255A which is configued in Mode 2.The
8255A is selected through theuseofa standardS-100 I/O Addressdecode select
scheme andthe S-100vectorinterruptstructure. The Z-80Aslavelogic is
implemented to allow the slave Z-80A CPUto generate the ACK- and STB-signals
required to READ from and WRITE tothe 8255A bidirectionalbus.
IMS INTERNATIONAL
D00740 REV1.0 October 20, 1981 Page 1

S-100 Configuring and Programming
I/O DEVICEADDRESSSELECTION(JE)
JE
A7 1
A62
A5 3
A4 4
A3 5
A2 6
12
11
10
9
8
7
SHUNT OFF= 1
SHUNT ON= 0
Exampleshown places 740 board atI/O address 40H- 43H
8255ABASICOPERATION
I/O
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DEVICE ADDRESS
XO
X2
OPERATION
PORT A -> S-100 BUS
PORT C -> S-100 BUS
XO
X2
X3
X3
X3
X3
X3
X3
X3
X3
X3
X3
X3
X3
X3
X3
S-100
S-100
S-100
COH
OOH
01H
02H
03H
08H
09H
OAH
OBH
OCH
ODH
OEH
OFH
BUS->
BUS->
BUS->
_>
0->
1->
0->
1->
0->
1->
0 ->
1->
0->
1->
0->
1->
P OR1
POR'
CON
CON'
PCO
PCO
PCI
PCI
PC4
PC4
PCS
PCS
PC6
PC6
PC7
PC7
CONTROL(Mode 2)
Control/Data Flag
Res
INT
IBF
Reset Slave
INTE2 (INTE forIBF
INTE1 (INTE forOBF
OBF
IMS INTERNATIONAL
D00740 REV1.0 October 20, 1981 Page 2

8255A Bidirectional BusI/O Control SignalDefinition
INTR+ (Interrupt Request)Used to interrupt the S-100 BUS Master for bothinput or
output operations.
OBF-(Output buffer Full)Used to indicate that the S-100 BUShas written data out
to PORT A.
:
•- ..*<•-•• : •. -.-.••, :•:•• • :; - •••;•• •-•*>': '-, • '••• .... . i.
ACK- (Acknowledge) Enables the tri-state output buffer of PORT A. •
. - . *' t :. . ' ,'.
INTE1 (The INTE Flip-FlopAssociated with OBF)Controlled bybit set/reset of PC6.
STB-(StrobeInput) Used to loaddata into the input latch of PORT A.
!
IBF+ (Input Buffer Full)Indicates that data has beenloadedinto the input latch of
PORT A.
^ INTE2 (The INTE Flip-FlopAssociated with IBF) Controlled bybit set/reset of PC4.
8255A Definition Summary
PAO-PA7 I/O DATA
PBO-PB7 UNUSED
PCO CONTROL/DATA FLAG
PCI RESETSLAVE
PC2 UNUSED
PC3 INTR+
PC4 STB-/INTE2 •
PCS IBF+
PC6 ACK-/INTE1
PC7 OBF-
INTERRÜPT SELECTION OPTION (JF)
JF
VIO
VII
VI2
VI3
VI4
VI5
VI6
VI7
1 .
2 .
3 .
4 .
5 .
6 .
7 .
8 .
.16
.15
.14
.13
.12
.11
.10
.9
The installing ofa SHUNT will attach the selected VIx InterruptLevel to Parallel
Port A Interrupt (PCS INTR).
Note: For more detail regarding the programming ofthe 8255A seethe Intel
PeripheralDesignHandbook.
' *•"•• IMS INTERNATIONAL
t> v -4 D00740 REV1.0 October 20, 1981Page 3

I/O Processor Configuring and Programming
4 „ . •* .1 ' **.
Z-80A SIO PORT A Receive and Transmit Band dock Selection (JA)
JA
1. .8 RxCA- from Z-80A CTC TO (thisconnection is etched) . ,,
2..7 RxCA- from RS-232 Interface PIN17 Signal DD
3- -fi TxCA- from Z-80A CTC T0(requires a shunt)
4..5 TxCA- from RS-232 Interface PIN15 Signal DB
Z-80A SIO PORT B Receive and Transmit Baud dock Selections (JB)
JB
1..6 RxTxCB- from Z-80A CTC Tl(thi s connection is etched)
2..5 RxTxCB- from RS-232 Interface PIN17 Signal DD
3..4 RxTxCB- from RS-232 Interface PIN15 Signal DB
S-100 RESETDISABLESHUNT (JD)
JD
1.
2.
SHUNT OFF= Normal mode J
SHUNT ON= Local 740 Test mode
IMS INTERNATIONAL
D00740 REV1.0 October 20, 1981 Page 4

MODEL 740
SERIAL PORT TO RS-232C CONNECTORCABLE
Signal
Name
Protective Ground
SignalGround
Transmit Data
(Data to MODEM)
ReceiveData
(Data from MODEM)
Request To Send
Clear To Send
Data Set Ready
DataTerminalReady
Ring Indicator
Data Carrier Detect
TransmitClock
(Clock From MODEM)
ReceiveClock
(Clock From MODEM)
RS-232C
Circuit Pin
£\£\
AR
£\D
RA
DA
RR
DD
r*A
v>A
r*R
vxJD
pr»
vA^
f~*T\
OJJ
r*f?
Vxui
T»R
± /
7v
1 /
o x
—
3
\ ^__
/ — — —
4 \_______
^ — — — — — — —
c;s_______
6
\
/
Oft\ _ ___ _
O 0 N _ — — — ___
OS
o ^ — — — — — — —
i ti \
Controller
Pin
> 1
> 3
> 5
> 7
> 9
DD
17>
>4
>8
IMS INTERNATIONAL
D00740 REV1.0 October 20, 1981 Page 9

Z-80A PIO Definition
PORT A INPUT BITS
AO
A2 DSS-
A3 DLO-
A4 C/D+
A5 IBF+
A6 OBF-
A7 PER+
PORT B OUTPUT BITS
BO NB1+
Bl NB2+
B2 NB4+
B3 NB8+
B4 DPR-
B5 CRQ-
B6 ROMEN +
B7 PERR+
Summary
BELL 801 DATA SET STATUS
BELL 801 DATALINE OCCUPIED
8255A PCO CONTROL/DATA FLAG
8255A PCS INPUTBUFFER FÜLL
8255A PC7 OUTPUT BUFFER FÜLL
RAM PARITY ERROR
BELL 801
BELL 801
BELL 801
BELL 801
BELL 801
BELL 801
ROM ENABLE
RAM PARITY
NUMBER
NUMBER
NUMBER
NUMBER
BIT1
BIT2
BIT 4
BIT 8
DIGITPRESENT
CALL REQUEST
RESET
NOTE: For more detail regarding the programming ofthe Z-80AMicrocomputer
Components see Zilog Data Book or TechnicalManuals.
IMS INTERNATIONAL
D00740 REV1.0 October 20, 1981 Page 6

HD
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LU
Ck
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O
O
cc
CL
O
O
O

MODEL 740 Pl SIGNALLIST
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
SIGNAL
+8V
+16V
VIO-
VII-
VI2-
VI3-
VI4-
VI5-
VI6-
VI7-
GND
A5+
A4+
A3+
DO1 +
DOO +
DO4 +
DO5 +
DO6 +
DI2+
DI3+
DI7+
sOUT+
SINP +
GND
PIN
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
SIGNAL
+8V
-16V
GND
pWR-
pDBIN +
AO +
A1+
A2+
A6 +
A7+
DO2 +
DO3 +
DO7 +
DI4+
DI5 +
DI6 +
DI1+
DIO +
POC-
GND
BIS INTERNATIONAL
D00740 REV1.0 October 209 1981Page 8

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MODEL 740
BELL 801ACÜ PARALLELPORT TO RS-232C CONNECTORCABLE
Signal
Name
ACU Connector
Circuit Pin
Controller
Pin
FrameGround
Signal Ground
Digit Present
Abandon Call-Retry
Call Request
Present Next Digit
Power Indication
Data Set Status
Number Bit 1
Number Bit2
Number Bit 4
Number Bit 8
Data Line Occupied
FGD
SGD
DPR
ACR
CRQ
PND
PWI
DSS
NB1
NB2
NB4
NB8
DLO
> 1
7>-
2>-
3>
4>
5>
6>
14>
15>
17>
22>
>5
> 9
>25
> 2
> 4
> 6
> 8
o
!IMS INTERNATIONAL
D00740 REV1.0 October 20, 1981 Page 10