Index DW9916S User manual

SERVICE MANUAL
DW9916S
R
Ver 0.0

INDEX
BLOCK DIAGRAM .........................................................................................................................
BLOCK DIAGRAM
PREFACE
FEATURES ........................................................................................................................................... 1
FRONT PANEL&REAR PANEL
....................................................................................................................................... 2
REMOTE CONTROL
................................................................................................................................ 3
SCHEMATIC DIAGRAM&PCB SILKSCREEN
MAIN BOARD SCHEMATIC AND PCB LAYOUT .................................................................................. 25-37
AV BOARD SCHEMATICAND PCB LAYOUT
.............................................................................................................. 38-47
48-52
KEY BOARD SCHEMATIC AND PCB LAYOUT
.................................................................................
POWER BOARD SCHEMATIC AND PCB LAYOUT ............................................................ 53-55
PARTS SPECIFICATIONS
SST39VF160............................................................................................................................................ 6
M13S128168A .......................................................................................................................................7
TSB41AB1
................................................................................................................ 8
TVP5146
................................................................................................................................9
CS4360
...................................................................................................................... 13
CS5333 .............................................................................................................................................. 15
74HC/HCT14 ........................................................................................................................................ 17
74ALVT16373............................................................................................................................... 18
MM1225 ...................................................................................................................................................... 19
LP2995
....................................................................................................................... 21
PQXXXEZ02Z .................................................................................................................................. 22
MS3415
......................................................................................................................... 23
TUNER ..................................................................................................................... 24
PARTS LIST
MAIN BOARD................................................................................................................................. 62-63
MAIN KEY BOARD
........................................................................................................................................
64
AUXILIARY KEY BOARD ...................................................................................................... 65
DV+FRONT AV BOARD ...........................................................................................................................66
CARD READER BOARD....................................................................................................67
POWER BOARD .................................................................................................................. 68-69
........................................................................................................................................5
EXPLODED VIEW
EXPLODED VIEW
BLOCK DIAGRAM ......................................................................................................................... 4
BLOCK DIAGRAM
DV+FRONT AV BOARD SCHEMATIC AND PCB LAYOUT..............................................................56-58
CARD READER BOARD SCHEMATIC AND PCB LAYOUT..............................................................59-61
CONTROLLER....................................................................................................................................70
REAR AV BOARD...............................................................................................................................71-72

1

2

3

DMN-8602
SDR/DDR SDRAM
Audio DAC 5.1CH Cs4
FP Control Front Panel
DV(1394) Phy
NTSC/PAL Decoder tvp5146
Audio FLASH
39VF160 1M 16bit
×
5VSTB +3.3V +5V +2.5V +12V -12V -22V
DVD+RW DVD Recordable
FRONTAV+DV INPUT CDW9916-4 CARD READER
DDW916-2
FRONT PANEL 4DW9916-2,9DW9916-1 DISPLAY&KEY
AV INPUT/OUTPUTBOARD 7DW9916-5
POWER BOARD 5AB9915-3
Scartinput/output5.1CHAudio
output
Video output
(component) A/V input TV Tuner
360
2DW9916-3
MAIN BOARD
4
BLOCK DIAGRAM
AC 100V-240V INPUT

EXPLODED VIEW
55

© 1998 Silicon Storage Technology, Inc.329-09 11/98
16 Megabit Multi-Purpose Flash
SST39VF160Q / SST39VF160
Advance Information
FIGURE 1: PIN ASSIGNMENTS FOR 48-PIN TSOP PACKAGES
FUNCTIONAL BLOCK DIAGRAM
FIGURE 2: PIN ASSIGNMENTS FOR 48-PIN TFBGA
Y-Decoder
I/O Buffers and Data Latches
329 ILL B1.2
Address Buffer & Latches
X-Decoder
DQ15 - DQ0
A19 - A0
OE#
CE#
WE#
16,777,216 bit
EEPROM
Cell Array
Control Logic
VDDQ
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
NC
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
VDDQ
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
329 ILL F01.2
Standard Pinout
Top View
Die Up
SST39VF160Q
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
NC
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
329 ILL F01a.0
Standard Pinout
Top View
Die Up
SST39VF160
329 ILL F02.4
SST39VF160Q
123456
A
A3 A7 NC WE# A9 A13
B A4 A17 NC NC A8 A12
C A2 A6 A18 NC A10 A14
D A1 A5 NC A19 A11 A15
E A0 DQ0 DQ2 DQ5 DQ7 A16
F CE# DQ8 DQ10 DQ12 DQ14 VDDQ
G OE# DQ9 DQ11 VDD DQ13 DQ15
H VSS DQ1 DQ3 DQ4 DQ6 VSS
329 ILL F02a.0
SST39VF160
123456
A
A3 A7 NC WE# A9 A13
B A4 A17 NC NC A8 A12
C A2 A6 A18 NC A10 A14
D A1 A5 NC A19 A11 A15
E A0 DQ0 DQ2 DQ5 DQ7 A16
F CE# DQ8 DQ10 DQ12 DQ14 NC
G OE# DQ9 DQ11 VDD DQ13 DQ15
H VSS DQ1 DQ3 DQ4 DQ6 VSS
6

ESMT   
M13S128168A
Elite Semiconductor Memory TechnologyInc.
Publication Date:Nov.2002
Revision :0.2 

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  
45-45 2
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66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm PIN PITCH)

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
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 
7
Revision :0.2 


   

SLLS423D –JUNE 2000 –REVISED SEPTEMBER 2002
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
description (continued)
required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is
in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and returns it
to normal operation.
When the PHY-LLC interface is in the low-power disabled state, the TSB41AB1 automatically enters a
low-power mode if the port is inactive (disconnected, disabled, or suspended). In this low-power mode, the
TSB41AB1 disables its internal clock generators and also disables various voltage and current reference
circuits depending on the state of the port (some reference circuitry must remain active in order to detect new
cable connections, disconnections, or incoming TPBIAS, for example). The lowest power consumption (the
ultralow-power sleep mode) is attained when the port is either disconnected, or disabled with the port interrupt
enable bit cleared. The TSB41AB1 exits the low-power mode when the LPS input is asserted high or when a
port event occurs which requires that the TSB41AB1 become active in order to respond to the event or to notify
the LLC of the event (for example, incoming bias is detected on a suspended port, a disconnection is detected
on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output becomes
active (and the PHY-LLC interface is initialized and becomes operative) within 7.3 ms after LPS is asserted high
when the TSB41AB1 is in the low-power mode.
The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the
C/LKON signal is a square wave of approximately 163-ns period. The PHY activates the C/LKON output when
the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is
inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet
addressed to this node is received, or when a PHY interrupt occurs. The PHY deasserts the C/LKON output
when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also deasserts the C/LKON
output when a bus reset occurs unless a PHY interrupt condition exists which would otherwise cause C/LKON
to be active.
PHP package terminal diagram
14 15
AGND
AVDD
R1
R0
AGND
TPBIAS
TPA+
TPA–
TPB+
TPB–
AGND
AVDD
36
35
34
33
32
31
30
29
28
27
26
25
16
1
2
3
4
5
6
7
8
9
10
11
12
SYSCLK
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
PD
17 18 19 20
47 46 45 44 4348 42 40 39 3841
21 22 23 24
37
13
PHP PACKAGE
(TOP VIEW)
TSB41AB1
PLLGND PLLV FILTER1 FILTER0 LREQ DGND DGND DV
TESTM
SE
SM
C/LKON
PC1 PC2
ISO
CPS
DV
RESET XO XI
DGND
LPS
PC0 DD
DVDD
DD
DD
8

1–4
1.5 Functional Block Diagram
Composite and S-Video Processor
Y/C
Separation
5-line
Adaptive
Comb
Luma
Processing
Chroma
Processing
ADC1
ADC2
ADC3
ADC4
M
U
XComponent
Processor
CVBS/Y
C
Y/G
Pb/B
Pr/R Gain/Offset
Color
Space
Conversion
C
Y
Output
Formatter
Y[9:0]
YCbCr
VBI
Data
Slicer
Copy
Protection
Detector
C[9:0]
Host
Interface
Timing Processor
with Sync Detector
VI_1_A
VI_1_B
VI_1_C
VI_2_A
VI_2_B
VI_2_C
VI_3_A
VI_3_B
VI_3_C
VI_4_A
CVBS/
Y/G
CVBS/
Pb/B/C
CVBS/
Pr/R/C
CVBS/Y
CVBS/Y/G
Analog Front End
Sampling
Clock
GPIO
FSS
HS/CS
VS/VBLK
FID
AVID
XTAL1 XTAL2
DATACLK
RESETB
GLCO
DR
DG
DB
FSO
PWDN
SCL
SDA
YCbCr
Figure 1–1. Functional Block Diagram
TVP5146
IS24C08-2,IS24C08-3
9

1–5
1.6 Terminal Assignments
22 23
C_6/GPIO/RED
C_7/GPIO/GREEN
C_8/GPIO/BLUE
C_9/GPIO/FSO
DGND
DVDD
Y_0
Y_1
Y_2
Y_3
Y_4
IOGND
IOVDD
Y_5
Y_6
Y_7
Y_8
Y_9
DGND
DVDD
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VI_1_B
VI_1_C
CH1_A33GND
CH1_A33VDD
CH2_A33VDD
CH2_A33GND
VI_2_A
VI_2_B
VI_2_C
CH2_A18GND
CH2_A18VDD
A18VDD_REF
A18GND_REF
CH3_A18VDD
CH3_A18GND
VI_3_A
VI_3_B
VI_3_C
CH3_A33GND
CH3_A33VDD
25 26 27 28
PFP PACKAGE
(TOP VIEW)
79 78 77 76 7580 74 72 71 7073
29 30 31 32 33
69 68
21
67 66 65 64
34 35 36 37 38 39 40
63 62 61
VI_1_A CH1_A18GND CH1_A18VDD PLL_A18GND PLL_A18VDD XTAL2 XTAL1 VS/VBLK/GPIO HS/CS/GPIO FID/GPIO C_0/GPIO C_1/GPIO DGND DVDD C_2/GPIO C_3/GPIO C_4/GPIO C_5/GPIO IOGND IOVDD
CH4_A33VDD
CH4_A33GND
VI_4_A
CH4_A18GND
CH4_A18VDD
AGND
DGND
SCL
SDA
INTREQ
DVDD
DGND
PWDN
RESETB
FSS/GPIO
AVID/GPIO
GLCO/I2CA
IOVDD
IOGND
DATACLK
Figure 1–2. Terminal Assignments Diagram
TVP5146
10

1–6
1.7 Terminal Functions
Table 1–1. Terminal Functions
TERMINAL
NAME NUMBER I/O DESCRIPTION
Analog Video
VI_1_A
VI_1_B
VI_1_C
VI_2_A
VI_2_B
VI_2_C
VI_3_A
VI_3_B
VI_3_C
VI_4_A
80
1
2
7
8
9
16
17
18
23
I
VI_1_x: Analog video input for CVBS/Pb/B/C
VI_2_x: Analog video input for CVBS/Y/G
VI_3_x: Analog video input for CVBS/Pr/R/C
VI_4_A: Analog video input for CVBS/Y
Up to 10 composite, 4 S-video, and 2 composite or 3 component video inputs (or a combination thereof)
can be supported.
The inputs must be ac-coupled. The recommended coupling capacitor is 0.1 µF.
The possible input configurations are listed in the input select register at I2C subaddress 00h (see
Section 2.11.1).
Clock Signals
DATACLK 40 O Line-locked data output clock.
XTAL1 74 I External clock reference input. It may be connected to an external oscillator with a 1.8-V compatible clock
signal or a 14.31818-MHz crystal oscillator.
XTAL2 75 O External clock reference output. Not connected if XTAL1 is driven by an external single-ended oscillator.
Digital Video
C[9:0]/
GPIO[9:0]
57, 58,
59, 60,
63, 64,
65, 66,
69, 70
O
Digital video output of CbCr, C[9] is MSB and C[0] is LSB. Unused outputs can be left unconnected. Also,
these terminals can be programmable general-purpose I/O.
For the 8-bit mode, the two LSBs are ignored.
D_BLUE 58 I Digital BLUE input from overlay device
D_GREEN 59 I Digital GREEN input from overlay device
D_RED 60 I Digital RED input from overlay device
FSO 57 I Fast-switch overlay between digital RGB and any video
Y[9:0]
43, 44,
45, 46,
47, 50,
51, 52,
53, 54
ODigital video output of Y/YCbCr, Y[9] is MSB and Y[0] is LSB.
For the 8-bit mode, the two LSBs are ignored. Unused outputs can be left unconnected.
Miscellaneous Signals
FSS/GPIO 35 I/O
Fast-switch (blanking) input. Switching signal between the synchronous component video (YPbPr/RGB)
and the composite video input.
Programmable general-purpose I/O
GLCO/I2CA 37 I/O
Genlock control output (GLCO). Two Genlock data formats are available: TI format and real time control
(RTC) format.
During reset, this terminal is an input used to program the I2C address LSB.
INTREQ 30 O Interrupt request
PWDN 33 I
Power down input:
1 = Power down
0 = Normal mode
RESETB 34 I Reset input, active low
TVP5146
11

1–7
Table 1–1. Terminal Functions (Continued)
TERMINAL
NAME NUMBER I/O DESCRIPTION
Host Interface
SCL 28 I I2C clock input
SDA 29 I/O I2C data bus
Power Supplies
AGND 26 I Analog ground. Connect to analog ground.
A18GND_REF 13 I Analog 1.8-V return
A18VDD_REF 12 I Analog power for reference 1.8 V
CH1_A18GND
CH2_A18GND
CH3_A18GND
CH4_A18GND
79
10
15
24
IAnalog 1.8-V return
CH1_A18VDD
CH2_A18VDD
CH3_A18VDD
CH4_A18VDD
78
11
14
25
IAnalog power. Connect to 1.8 V.
CH1_A33GND
CH2_A33GND
CH3_A33GND
CH4_A33GND
3
6
19
22
IAnalog 3.3-V return
CH1_A33VDD
CH2_A33VDD
CH3_A33VDD
CH4_A33VDD
4
5
20
21
IAnalog power. Connect to 3.3 V.
DGND 27, 32, 42,
56, 68 IDigital return
DVDD 31, 41, 55,
67 IDigital power. Connect to 1.8 V.
IOGND 39, 49, 62 IDigital power return
IOVDD 38, 48, 61 IDigital power. Connect to 3.3 V or less for reduced noise.
PLL_A18GND 77 I Analog power return
PLL_A18VDD 76 I Analog power. Connect to 1.8 V.
Sync Signals
HS/CS/GPIO 72 I/O Horizontal sync output or digital composite sync output
Programmable general-purpose I/O
VS/VBLK/GPIO 73 I/O Vertical sync output (for modes with dedicated VSYNC) or VBLK output
Programmable general-purpose I/O
FID/GPIO 71 I/O Odd/even field indicator output. This terminal needs a pulldown resistor.
Programmable general-purpose I/O
AVID/GPIO 36 I/O Active video indicator output
Programmable general-purpose I/O
TVP5146
12

14
13

15
14

16
15

17
IS24C08-2,IS24C08-3
16

Philips SemiconductorsProduct specification
Hex inverting Schmitt trigger 74HC/HCT14
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 3, 5, 9, 11, 13 1A to 6A data inputs
2, 4, 6, 8, 10, 12 1Y to 6Y data outputs
7 GND ground (0 V)
14 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
Fig.4 Functional diagram. Fig.5 Logic diagram
(one Schmitt trigger).
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
APPLICATIONS
•Wave and pulse shapers
•Astable multivibrators
•Monostable multivibrators
INPUT OUTPUT
nA nY
L
HH L
17

Philips Semiconductors Product specification
74ALVT163732.5V/3.3V 16-bit transparent D-type latch (3-State)
LOGIC SYMBOL
32
1Q0 1Q1 1Q2
65
1Q3
47 46 44 43
1D0 1D1 1D2 1D3
48
1
98
1Q4 1Q5 1Q6
1211
1Q7
41 40 38 37
1D4 1D5 1D6 1D7
1LE
1OE
1413 1716
36 35 33 32
25
24
2019 2322
30 29 27 26
2Q0 2Q1 2Q2 2Q3
2D02D21 2D2 2D3
2Q4 2Q5 2Q6 2Q7
2D4 2D5 2D6 2D7
2LE
2OE
SA00044
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
47, 46, 44, 43, 41, 40, 38, 37,
36, 35, 33, 32, 30, 29, 27, 26 1D0 – 1D7 2D0 – 2D7 Data inputs
2, 3, 5, 6, 8, 9, 11, 12, 13,
14, 16, 17, 19, 20, 22, 23 1Q0 – 1Q7 2Q0 – 2Q7 Data outputs
1, 24 1OE, 2OE Output enable
inputs
(active-Low)
48, 25 1LE, 2LE Enable inputs
(active-High)
4, 10, 15, 21, 28, 34, 39, 45 GND Ground (0V)
7, 18, 31, 42 VCC Positive
supply voltage
LOGIC SYMBOL (IEEE/IEC)
48
1EN
1 ∇
46
44
43
41
40
38
37
36
C3
2EN
C4
2 ∇
1
24
25
47
35
33
32
30
29
27
26
3
2
5
6
8
9
11
12
13
14
16
17
19
20
22
23
SW00010
1OE
1LE
2OE
2LE
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q8
1D8
2Q6
2Q7
3D
4D
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q0
1Q1
GND
1Q2
1Q3
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q3
VCC
2Q4
VCC
2Q2
2Q5
GND
2Q7
2OE
2Q6
1LE
1D0
1D1
GND
1D2
1D3
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D3
VCC
2D4
VCC
2D2
2D5
GND
2D7
2LE
2D6
SA00043
18