Index DW9916S User manual

SERVICE MANUAL
DW9916S
R
Ver 0.0

INDEX
BLOCK DIAGRAM .........................................................................................................................
BLOCK DIAGRAM
PREFACE
FEATURES ........................................................................................................................................... 1
FRONT PANEL&REAR PANEL
....................................................................................................................................... 2
REMOTE CONTROL
................................................................................................................................ 3
SCHEMATIC DIAGRAM&PCB SILKSCREEN
MAIN BOARD SCHEMATIC AND PCB LAYOUT .................................................................................. 25-37
AV BOARD SCHEMATICAND PCB LAYOUT
.............................................................................................................. 38-47
48-52
KEY BOARD SCHEMATIC AND PCB LAYOUT
.................................................................................
POWER BOARD SCHEMATIC AND PCB LAYOUT ............................................................ 53-55
PARTS SPECIFICATIONS
SST39VF160............................................................................................................................................ 6
M13S128168A .......................................................................................................................................7
TSB41AB1
................................................................................................................ 8
TVP5146
................................................................................................................................9
CS4360
...................................................................................................................... 13
CS5333 .............................................................................................................................................. 15
74HC/HCT14 ........................................................................................................................................ 17
74ALVT16373............................................................................................................................... 18
MM1225 ...................................................................................................................................................... 19
LP2995
....................................................................................................................... 21
PQXXXEZ02Z .................................................................................................................................. 22
MS3415
......................................................................................................................... 23
TUNER ..................................................................................................................... 24
PARTS LIST
MAIN BOARD................................................................................................................................. 62-63
MAIN KEY BOARD
........................................................................................................................................
64
AUXILIARY KEY BOARD ...................................................................................................... 65
DV+FRONT AV BOARD ...........................................................................................................................66
CARD READER BOARD....................................................................................................67
POWER BOARD .................................................................................................................. 68-69
........................................................................................................................................5
EXPLODED VIEW
EXPLODED VIEW
BLOCK DIAGRAM ......................................................................................................................... 4
BLOCK DIAGRAM
DV+FRONT AV BOARD SCHEMATIC AND PCB LAYOUT..............................................................56-58
CARD READER BOARD SCHEMATIC AND PCB LAYOUT..............................................................59-61
CONTROLLER....................................................................................................................................70
REAR AV BOARD...............................................................................................................................71-72

1

2

3

DMN-8602
SDR/DDR SDRAM
Audio DAC 5.1CH Cs4
FP Control Front Panel
DV(1394) Phy
NTSC/PAL Decoder tvp5146
Audio FLASH
39VF160 1M 16bit
×
5VSTB +3.3V +5V +2.5V +12V -12V -22V
DVD+RW DVD Recordable
FRONTAV+DV INPUT CDW9916-4 CARD READER
DDW916-2
FRONT PANEL 4DW9916-2,9DW9916-1 DISPLAY&KEY
AV INPUT/OUTPUTBOARD 7DW9916-5
POWER BOARD 5AB9915-3
Scartinput/output5.1CHAudio
output
Video output
(component) A/V input TV Tuner
360
2DW9916-3
MAIN BOARD
4
BLOCK DIAGRAM
AC 100V-240V INPUT

EXPLODED VIEW
55

© 1998 Silicon Storage Technology, Inc.329-09 11/98
16 Megabit Multi-Purpose Flash
SST39VF160Q / SST39VF160
Advance Information
FIGURE 1: PIN ASSIGNMENTS FOR 48-PIN TSOP PACKAGES
FUNCTIONAL BLOCK DIAGRAM
FIGURE 2: PIN ASSIGNMENTS FOR 48-PIN TFBGA
Y-Decoder
I/O Buffers and Data Latches
329 ILL B1.2
Address Buffer & Latches
X-Decoder
DQ15 - DQ0
A19 - A0
OE#
CE#
WE#
16,777,216 bit
EEPROM
Cell Array
Control Logic
VDDQ
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
NC
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
VDDQ
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
329 ILL F01.2
Standard Pinout
Top View
Die Up
SST39VF160Q
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
NC
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
329 ILL F01a.0
Standard Pinout
Top View
Die Up
SST39VF160
329 ILL F02.4
SST39VF160Q
123456
A
A3 A7 NC WE# A9 A13
B A4 A17 NC NC A8 A12
C A2 A6 A18 NC A10 A14
D A1 A5 NC A19 A11 A15
E A0 DQ0 DQ2 DQ5 DQ7 A16
F CE# DQ8 DQ10 DQ12 DQ14 VDDQ
G OE# DQ9 DQ11 VDD DQ13 DQ15
H VSS DQ1 DQ3 DQ4 DQ6 VSS
329 ILL F02a.0
SST39VF160
123456
A
A3 A7 NC WE# A9 A13
B A4 A17 NC NC A8 A12
C A2 A6 A18 NC A10 A14
D A1 A5 NC A19 A11 A15
E A0 DQ0 DQ2 DQ5 DQ7 A16
F CE# DQ8 DQ10 DQ12 DQ14 NC
G OE# DQ9 DQ11 VDD DQ13 DQ15
H VSS DQ1 DQ3 DQ4 DQ6 VSS
6

ESMT   
M13S128168A
Elite Semiconductor Memory TechnologyInc.
Publication Date:Nov.2002
Revision :0.2 










2

 
 




















 
45
45
5(



;(
  
45-45 2

































66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm PIN PITCH)

 

 
 

 
 

 
 

 









































 




 
 



















































 
7
Revision :0.2 


   

SLLS423D –JUNE 2000 –REVISED SEPTEMBER 2002
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
description (continued)
required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is
in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and returns it
to normal operation.
When the PHY-LLC interface is in the low-power disabled state, the TSB41AB1 automatically enters a
low-power mode if the port is inactive (disconnected, disabled, or suspended). In this low-power mode, the
TSB41AB1 disables its internal clock generators and also disables various voltage and current reference
circuits depending on the state of the port (some reference circuitry must remain active in order to detect new
cable connections, disconnections, or incoming TPBIAS, for example). The lowest power consumption (the
ultralow-power sleep mode) is attained when the port is either disconnected, or disabled with the port interrupt
enable bit cleared. The TSB41AB1 exits the low-power mode when the LPS input is asserted high or when a
port event occurs which requires that the TSB41AB1 become active in order to respond to the event or to notify
the LLC of the event (for example, incoming bias is detected on a suspended port, a disconnection is detected
on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output becomes
active (and the PHY-LLC interface is initialized and becomes operative) within 7.3 ms after LPS is asserted high
when the TSB41AB1 is in the low-power mode.
The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the
C/LKON signal is a square wave of approximately 163-ns period. The PHY activates the C/LKON output when
the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is
inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet
addressed to this node is received, or when a PHY interrupt occurs. The PHY deasserts the C/LKON output
when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also deasserts the C/LKON
output when a bus reset occurs unless a PHY interrupt condition exists which would otherwise cause C/LKON
to be active.
PHP package terminal diagram
14 15
AGND
AVDD
R1
R0
AGND
TPBIAS
TPA+
TPA–
TPB+
TPB–
AGND
AVDD
36
35
34
33
32
31
30
29
28
27
26
25
16
1
2
3
4
5
6
7
8
9
10
11
12
SYSCLK
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
PD
17 18 19 20
47 46 45 44 4348 42 40 39 3841
21 22 23 24
37
13
PHP PACKAGE
(TOP VIEW)
TSB41AB1
PLLGND PLLV FILTER1 FILTER0 LREQ DGND DGND DV
TESTM
SE
SM
C/LKON
PC1 PC2
ISO
CPS
DV
RESET XO XI
DGND
LPS
PC0 DD
DVDD
DD
DD
8