Innovative Integration PC44 User manual

Innovative Integration
PC44 Hardware Manual

The PC44 Hardware Manual was prepared by the technical staff of Innovative Integration, Aug. ‘95.
Third Edition prepared June ‘96 (applies to Rev. E and later cards)
For further assistance contact
Innovative Integration
31352 W. Via Colinas #101
Westlake Village, California 91362
PH: [phone]
FAX: [phone]
email: [e-mail]
WWW: www.innovative-dsp.com
This document is copyright 1994, 1995, 1996 by Innovative Integration. All rights are reserved.
IBM PC, AT and PS/2 are registered trademarks of
International Business Machines
Windows is a registered trademark of Microsoft Corporation
file: \\p60\c\winword\manuals\pc44\hardware\pc44hdw3.doc
#51022 rev – 3.00

Table of Contents
1. PC44 Hardware Functions.................................................................. 1
1.1 PC44 Bus Interface...................................................................................................................... 1
1.2 PC44 Memory.............................................................................................................................. 3
1.2.1 PC44 Local Memory............................................................................................................. 3
1.2.2 Local Boot FLASH Memory................................................................................................ 3
1.2.3 Local SRAM Memory........................................................................................................... 4
1.2.4 PC44 Global Memory........................................................................................................... 4
1.2.4.1 Global Arbitration............................................................................................................ 4
1.2.4.2 Global Peripheral Region.................................................................................................4
1.2.5 Wait States............................................................................................................................. 6
1.2.6 Memory Options ................................................................................................................... 7
1.2.7 Dual Port Memory................................................................................................................ 8
1.2.7.1 Dual Port Semaphores...................................................................................................... 9
1.2.8 PC44 Boot PROM............................................................................................................... 10
1.3 Processor Interrupts.................................................................................................................. 11
1.3.1 Interrupt Combinations...................................................................................................... 11
1.3.2 Interrupt Types................................................................................................................... 11
1.3.3 Interrupt Selection.............................................................................................................. 13
1.4 TIM40 Expansion Sites............................................................................................................. 15
1.4.1 TIM40 Comm Port Interconnections................................................................................ 15
1.4.2 TIM Site JTAG Considerations......................................................................................... 16
1.5 Peripherals ................................................................................................................................. 18
1.5.1 External Memory Mapped Peripherals ............................................................................ 18
1.5.2 Timer Source Selection....................................................................................................... 20
1.5.3 The Parallel I/O Ports......................................................................................................... 20
1.5.3.1 Digital Connections......................................................................................................... 21
1.5.4 The 82C54 Counter/Timers................................................................................................ 21
1.5.5 Analog I/O ........................................................................................................................... 22
1.5.6 Analog Input........................................................................................................................ 23
1.5.6.1 PC44 A/D Register Set....................................................................................................25
1.5.6.2 A/D Conversion Triggering............................................................................................ 26
1.5.6.3 A/D Channel Calibration................................................................................................ 27
1.5.6.4 Input Range Control....................................................................................................... 27
1.5.6.5 Single-Ended/Differential Inputs................................................................................... 28
1.5.6.6 Analog Multiplexer......................................................................................................... 29
1.5.6.7 MUX Software Cautions................................................................................................ 31
1.5.6.8 Programmable Gain Amplifiers..................................................................................... 32

1.5.6.9 Anti-alias Filtering ..........................................................................................................32
1.5.7 Analog Output.....................................................................................................................35
1.5.7.1 D/A Converter Output Ranges.......................................................................................35
1.5.7.2 D/A Output Trimming....................................................................................................36
1.5.7.3 D/A Output Amplification and Filtering.......................................................................36
1.5.7.4 D/A Converter Control Registers (Software Conversion Triggering)........................36
1.5.7.5 D/A Hardware Conversion Triggering..........................................................................37
1.5.8 Analog Output Bits (ABITS)..............................................................................................38
1.5.9 Analog Power Supplies.......................................................................................................38
2. Appendices...........................................................................................39
2.1 Factory Jumper Settings ...........................................................................................................39
2.2 Connector Pinouts......................................................................................................................40
2.3 Component Data Sheets.............................................................................................................44

List of Figures
Figure 1: PC44 Memory Map...................................................................................................................... 5
Figure 2: PC44 Communication Port Connections.................................................................................. 15
Figure 3: JTAG Connections and Shorting Jumper Functionality........................................................ 17
Figure 4: PC44 Multiboard Installation................................................................................................... 17
Figure 5: Block Diagram of Analog Inputs .............................................................................................. 24
Figure 6: MUX Channel Input Diagram .................................................................................................. 30
Figure 7: Anti-alias Filter Frequency Response....................................................................................... 33
Figure 8: Anti-aliasing Filter Schematic................................................................................................... 34
Figure 9: JP7 - Digital I/O, External Clocks, and External Interrupts.................................................. 41
Figure 10: P1 - External Analog I/O and Power Supplies....................................................................... 42
Figure 11: JP31-36 - Processor Communication Port Headers.............................................................. 43

List of Tables
Table 1: I/O Mapped PC Bus Registers...................................................................................................... 1
Table 2: Processor Interrupt Types and Reception Compatibility......................................................... 11
Table 3: Processor A Interrupt Selector................................................................................................... 13
Table 4: Processor B Interrupt Selector................................................................................................... 13
Table 5: Processor C Interrupt Selector................................................................................................... 14
Table 6: Comm Port Jumper Direction Settings...................................................................................... 16
Table 7: PC44 External Peripheral Memory Map ................................................................................. 18
Table 8: Timer Source 0 Selection Jumpers............................................................................................. 20
Table 9: Timer Source 1 Selection Jumpers............................................................................................. 20
Table 10: JP5 Digital I/O Port Direction Jumper Settings...................................................................... 21
Table 11: JP4 Digital I/O Port Readback Clock Jumper Settings.......................................................... 21
Table 12: 82C54 Register Locations.......................................................................................................... 22
Table 13: 82C54 Clock Sources................................................................................................................. 22
Table 14: A/D Control Registers ............................................................................................................... 25
Table 15: A/D Conversion Trigger Selection Jumper.............................................................................. 26
Table 16:A/D Input Range Jumper Settings ............................................................................................ 27
Table 17: ADC Multiplexer Options......................................................................................................... 28
Table 18: JP17 Settings (A/D Channel A)................................................................................................. 28
Table 19: JP16 Settings (A/D Channel B)................................................................................................. 28
Table 20: MUX Channel A Selector Values ............................................................................................. 31
Table 21: MUX Channel B Selector Values ............................................................................................. 31
Table 22: Channel A Gain Selection ......................................................................................................... 32
Table 23: Channel B Gain Selection.......................................................................................................... 32
Table 24: DAC0 Output Range Selection................................................................................................. 35
Table 25: DAC1 Output Range Selection................................................................................................. 35
Table 26: DAC2 Output Range Selection................................................................................................. 35
Table 27: DAC3 Output Range Selection................................................................................................. 35
Table 28: DAC Output Range Adjustment Amplifier Resistors and Filtering Capacitors, with
Factory Defaults ................................................................................................................................ 36
Table 29: D/A Software Update Registers................................................................................................ 37
Table 30: D/A Update Trigger Selection................................................................................................... 37
Table 31: Analog Power Supply Current Limits ..................................................................................... 38
Table 32: JP7 - Pin Description................................................................................................................. 41
Table 33: P1 - Pin Description................................................................................................................... 42
Table 34: JP31-36 Pin Description............................................................................................................ 43

PC44 Hardware Manual - 1
1. PC44 Hardware Functions
The PC44 single board computer is built around the Texas Instruments TMS320C44 digital signal
processor capable of up to 200 MOPS (50 MHz clock) sustained performance. The major subsections of
the board are the bus interface, memory, I/O ports and analog I/O.
1.1 PC44 Bus Interface
The PC44 is mapped into the I/O and memory space of the IBM AT. The PC44 supports 16-bit and 32-bit
accesses only - no eight bit accesses are supported. The 32-bit operations on the PC bus allow easy use
with newer 32-bit protected mode PC software.
The PC44 is mapped into the I/O space of the IBM-AT and consumes 32 contiguous bytes of conventional
I/O space located on an even 32-bit boundary within the I/O map. Within this I/O region lie three 16-bit
registers which are manipulated to control the PC44, as well as eight 32-bit semaphore registers available to
development and user software. The I/O register map is described in the following table. References to
BASE below refer to the I/O address into which you mapped the PC44 in your system during installation
(default 0x280).
Table 1: I/O Mapped PC Bus Registers
I/O Address Bit Direction Function
Control Register
Base + 0x800 0 Write only Reset to PC44
1=reset 0=run
1 Write only Enable dual port accesses
1=enable 0=disable
2 Read Only Config readback
1=all processors booted
0=at least one processor still
booting
Interrupt 0
Base + 0x802 - Read/Write Cause PC Int0 to PC44
(access to cause interrupt pulse)
Interrupt 1
Base + 0x804 - Read/Write Cause PC Int1 to PC44
(access to cause interrupt pulse)
Interrupt 2
Base + 0x806 - Read/Write Cause PC Int2 to PC44
(access to cause interrupt pulse)
Dual Port Semaphores
0 Base + 0x0 16-bit Read/ Write 0x0000 = resource captured
0xFFFF = resource busy
1 Base + 0x4 16-bit Read/ Write 0x0000 = resource captured
0xFFFF = resource busy
2 Base + 0x8 16-bit Read/ Write 0x0000 = resource captured
0xFFFF = resource busy

PC44 Hardware Manual - 2
3 Base + 0xC 16-bit Read/ Write 0x0000 = resource captured
0xFFFF = resource busy
4 Base + 0x10 16-bit Read/ Write 0x0000 = resource captured
0xFFFF = resource busy
5 Base + 0x14 16-bit Read/ Write 0x0000 = resource captured
0xFFFF = resource busy
6 Base + 0x18 16-bit Read/ Write 0x0000 = resource captured
0xFFFF = resource busy
7 Base + 0x1C 16-bit Read/ Write 0x0000 = resource captured
0xFFFF = resource busy

PC44 Hardware Manual - 3
1.2 PC44 Memory
The ‘C44 DSP has two physical memory busses - local and global. In a multiprocessor application, the
global memory is typically used as shared memory between processors. The PC44 supports both memory
spaces for the on-board processor and supports shared global memory with TIM40 site A.
The PC44 main processor local and global memory is designed to be zero wait state SRAM. The memory
SIMMs can be 32Kx32, 64Kx32, 128Kx32, 256Kx32, 512Kx32, 1Mx32 or 2Mx32 (local SRAM only).
SIMM modules should be 25 nS access time for 40 MHz operation and 20 nS for 50 MHz. SIMM modules
are available from Innovative Integration. Brands we have tested include Cypress and IDT.
The PC44 memory uses a 32-bit wide logical address, the lower 24 bits of which are significant. This is
because the 'C44 DSP memory address busses are physically 24 bits wide, but maintain basic compatibility
with the original ‘C40 DSP which has 32-bit addressing. To the programmer, the memory appears as a
logical 32-bit address with local memory defined from 0x0000 0000 to 0x7FFF FFFF, and global memory
defined from 0x8000 0000 to 0xFFFF FFFF. The two most significant nibbles of the logical 32-bit address
are “don’t care,” resulting in aliasing of the memory for every 16M page, i.e. local memory at 0x00E0 0000
also appears at 0x10E0 000, 0x20E0 000 etc. up to 0x7FE0 000, with global memory having the same
property. Thus, if a program were to write the value 0x12345678 to the first local SRAM memory location
at address 0x7FE0 0000, it would read the same value back at address 0x00E0 0000, address 0x01E0 0000,
etc. Similarly, a write to address 0x00E0 0000 could be read back at address 0x7FE0 0000. Note that the
memory map of the PC44 card is arranged such that such aliasing will not cause conflicts between different
memory devices in the same local or global address space.
1.2.1 PC44 Local Memory
The PC44 on-board ‘C44 processor has boot FLASH and SRAM memory. The boot FLASH is mapped to
local strobe 0 starting at 0x0030 0000. The local SRAM is mapped to local strobe 1 starting at 0x7FE0
0000. This mapping is defined by the LMCR (local memory control register) at boot-up time.
The on-board FLASH memory is used for the boot code of the ‘C44. At boot-up, the ‘C44 vectors to the
on-chip bootloader ROM and reads the boot FLASH into on-chip SRAM. After the load is complete, the
program execution begins from internal RAM and the LMCR is configured to enable the local SRAM.
1.2.2 Local Boot FLASH Memory
The standard FLASH memory on the PC44 is a 1M bit (128Kx8) part, AMD AM29F010-120JC. The
PC44 may also be configured with a 4M bit FLASH for larger storage.
The FLASH memory may be read or written at any time during normal operation for reprogramming or
used as general storage provided the LMCR is not reconfigured in the application. The boot FLASH
memory operates at 4 wait states for reads. Writes to FLASH require a special routine which monitors the
FLASH to determine erasure and validates proper programming. Typical sector erase times for this part are
on the order of 1.3 seconds for a single 16K byte sector. Typically programming (write) times are on the
order of 0.3 seconds for a single 16K byte sector.

PC44 Hardware Manual - 4
1.2.3 Local SRAM Memory
Local SRAM is configured by the boot program to be zero-wait state memory logically mapped to 0x7FE0
0000. Since the memory aliases in the memory map, the physical address is 0xE0 0000, allowing for future
expansion up to 2M of local SRAM. The local memory appears to the programmer to be contiguous with
the global memory SRAM for ease of use. In single processor systems, this effectively makes the two
SIMMs available as a contiguous memory bank of up to 3M in size.
1.2.4 PC44 Global Memory
The PC44 has on-board support for global memory which is arbitrated with a second processor in TIM site
A. The global memory, as configured in the GMCR (Global Memory Control Register) by the boot
program, is divided into SRAM and expansion EDRAM on global strobe 0 and peripherals on strobe 1.
The peripheral section includes the on-board peripherals and an expansion area.
1.2.4.1 Global Arbitration
The global memory arbitration on the PC44 is designed to arbitrate the global memory usage between the
on-board processor and the TIM site A processor. The arbitration insures that memory collisions do not
occur between the two processors and that memory accesses are as fast as possible.
The arbitration logic monitors the two processors and awards ownership of the global memory based upon
the access cycles of the processor requesting ownership as well as those of the current global bus master.
The arbitrator allows one processor to own the memory until another processor requests ownership. If one
processor has ownership and has locked out the other processor (via the ‘C44 interlock instructions), no
arbitration will take place until it the lock is removed. While a processor owns the global memory,
accesses to the global memory are not burdened by additional wait states. For global SRAM, this allows
zero wait state performance for the processor which currently owns memory. When arbitration is permitted,
there is a minimum five clock hold placed on both processors. Once bus mastership is resolved, the new
bus master is permitted zero wait-state access to global SRAM.
1.2.4.2 Global Peripheral Region
The peripheral region in the global memory space contains the on-board peripherals and the expansion port
for the PC44. The on-board peripherals can have either two or seven wait state access, depending on the
particular peripheral. The expansion port is intended for custom hardware devices. Additional wait states
can be applied to the expansion area’s user strobes by modifying the GMCR value.

PC44 Hardware Manual - 5
Figure 1: PC44 Memory Map
Logical Address Physical Address
$0000 0000 Boot Loader ROM
(internal)
$0000 FFFF
Reserved
$0010 0000 Internal Peripherals
$0010 00FF
Reserved
Reserved Local
Space
$002F F800 1K RAM Block 0
(internal)
$002F FBFF
$002F FC00 1K RAM Block 1
(internal)
$002F FFFF
$0030 0000 $30 0000
Boot Flash
(local strobe 0)
$0031 FFFF $31 FFFF
$7FE0 0000 $E0 0000
Local SRAM
(local strobe 1)
$7FFF FFFF $FF FFFF
$8000 0000 $00 0000
Global SRAM/EDRAM
(global strobe 0)
$801F FFFF $1F FFFF Global
Space
Reserved
(global strobe 1)
$FFF0 0000 $F0 0000
External Peripherals
(global strobe 1)
$FFFF FFFF $FF FFFF

PC44 Hardware Manual - 6
1.2.5 Wait States
The ‘C44 features independent, flexible, programmable wait-state generators for each strobe in global and
local memory. The wait state generators can be programmed to insert from one to seven wait states on
accesses to program and/or data memory.
During hardware reset, the PC44 configures its internal wait state generators for seven-wait-state operation
in program and data spaces.
Within initialization code in all PC44 applications, the wait state control registers should be modified to
configure the internal wait state generators for zero-wait operation in program and data spaces. Failure to
reconfigure this register during initialization will cause improper operation and all accesses to memory
to run with seven wait states. The startup code routines within the PC44 boot ROM have been customized
to automatically perform this initialization during the startup of each application program with zero wait
state for on-board local and global SRAM and an appropriate mix of wait states for peripherals. However,
renegade applications which do not make use of this code will need to explicitly initialize this register.
Normally, software should include boot.asm for proper operations. boot.asm provides proper
initialization of the local and global bus control registers. C applications developed with the Innovative
Integration C Developer’s Package automatically use boot.asm.

PC44 Hardware Manual - 7
1.2.6 Memory Options
The PC44 supports up to 2048 KWords of local SRAM and 1024 KWords of global SRAM on the board
without additional hardware. The standard memory configuration shipped is 128 KWords of zero wait state
local memory.
Memory can be configured for any of the following sizes of SIMMs: 32K, 64K, 128K, 256K, 1024K, or
2048K. Any mix of SIMM modules is allowed, including exclusion of global memory. Some amount of
local memory is required for operation.
Please note that certain TIM processor and peripheral cards may include global memory which intrudes into
the PC44 global SRAM space. If this is the case, global SRAM population on the PC44 is disallowed, and
the memory on the TIM module is addressed instead. Please contact the factory concerning global SRAM
questions.

PC44 Hardware Manual - 8
1.2.7 Dual Port Memory
The PC44 is configured with a 4K X 32 dual port memory to allow high speed data communication
between the ISA bus and PC44 processors. The dual port is addressable by the PC44 as a contiguous
0x1000 word memory starting at address 0xFFF8 0000. The dual port is addressed from the IBM-PC side
at the conventional memory address specified via DIP switch S2 (default D000:0000). Accesses to dual
port memory always run with zero wait states from the PC side and two wait states from the PC44 side
(after initial global bus arbitration overhead).
Please note that there is no hardware arbitration on the dual port between contending PC and ‘C44 accesses.
If both the ISA bus and one of the ‘C44 processors try to read or write data to the same dual port location at
the same time, unpredictable results will occur. The PC44 supports a software arbitration scheme using the
dual port hardware semaphores and requires software cooperation to synchronize accesses from both bus
sides.
The arbitration scheme works as follows: access to a region of dual port is keyed to ownership of one of the
eight dual port semaphores. If either the host or one of the ‘C44 processors wants access to the dual port
memory region, it must first request and receive ownership of the corresponding dual port semaphore (see
2.2.3.1, “Dual Port Semaphores”). Once a processor owns the semaphore granting access to the region, that
side is allowed exclusive access and the other processor should not access the same region of dual port.
Once the owner completes its access, it releases the semaphore, allowing the other processor to claim dual
port access if it needs to.
Note that this scheme, while supported by hardware semaphore bits in the dual port memories, is not
hardware arbitrated and depends on cooperative software on both host and target. There is no hardware
mechanism restraining either processor’s software from accessing dual port at any time. Only the
cooperation of software between processors keeps the dual port memory contents from being corrupted.
Therefore, proper software construction is imperative to error-free dual port data movement. Software on
both sides of dual port must always obtain semaphore ownership before accessing shared memory.

PC44 Hardware Manual - 9
1.2.7.1 Dual Port Semaphores
The PC44 dual port has eight semaphores which may be used by software to control the data flow through
the dual port memory. The semaphores assist software by providing an arbitration method when accessing
the dual port memory. Software can pass access control over regions of the dual port memory by passing
ownership of one of the semaphores such that bi-directional communications are always handshaken
between the two processors. Also, semaphore driven dual port accesses are typically faster since no
hardware arbitration contests will occur between the processors for each dual port memory access. This
method is particularly useful for block transfers, since one side can prepare a block to be transferred by
filling a section of dual port with data completely unhindered by the byte-by-byte arbitration contests
typical of a hardware arbitration system. Once the buffer is filled, the originating side relinquishes dual port
access to the receiver, which then empties the dual port contents (again unhindered by arbitration contests).
The dual port semaphores reside at 0xFFF8 4000 - 0xFFF8 4007 on the ‘C44 side. All accesses to the dual
port semaphores from the ‘C44 side are arbitrated between the PC44 processors, since the dual port lies in
global address space and can be accessed by either ‘C44.
From the PC side, the semaphores reside at I/O location Base+0 through Base+0x1f, each on 32-bit
boundaries. Please note that dual port semaphore accesses only return results on the lower 16 bits of the 32
bit location: the upper 16 bits of any semaphore read by either processor should be masked.
The handshaking steps in using the semaphores are as follows :
1. A processor attempts to write a 0 to the semaphore.
2. A read is performed by the processor and if a 0xXXXX0000 is returned, the semaphore was
successfully seized. If a 0xXXXXFFFF is returned the resource is busy.
3. Relinquish the semaphore by writing a 1 to the semaphore when the dual port is no longer
needed.
The dual port semaphores are fully arbitrated by the on-chip hardware. Access to the semaphores is always
first-come, first-served. Truly simultaneous accesses by both busses will result in an arbitrary winner.
Note that failed requests for a semaphore are latched by the semaphore control logic. This means that the
request will eventually be granted when the owner relinquishes control of the semaphore. The following
example illustrates this behavior:
1. ‘C44 requests semaphore #0 and it is granted.
2. Some time later, host software requests semaphore #0 and is denied access since the ‘C44
already owns the bit.
3. Some time later, the ‘C44 releases semaphore #0, and since the host never released the original
request, the semaphore is immediately granted to the host. If the host software has not been
dwelling on the semaphore, it is possible that it is not expecting access to be granted and so
may not release the semaphore. For this execution session, the semaphore has been effectively
lost since the host software does not release it and the ‘C44 can no longer gain access.
This example illustrates that it is good form to release a failed request for a semaphore if the software
intends to proceed to other tasks. Doing so avoids the possible deadlock which might result from a granted
semaphore which is never released.

PC44 Hardware Manual - 10
1.2.8 PC44 Boot PROM
The 'C44 has a pin called ROMEN, which controls the memory map of the chip and the boot loader mode
of operation. When the 'C44 comes out of reset and ROMEN is high, the DSP boots in the ROM enabled
mode. In this case the ‘C44 internal boot ROM is active and the DSP jumps to the boot FLASH memory at
location 0x30 0000 and copies the contents of the boot FLASH into SRAM.
The bootloader mode is the standard mode of operation for the PC44. The PC44 has a boot program
installed in FLASH memory at the factory which allows proper boot-up and register initialization to interact
with the II Monitor or your application software.
Occasionally, you may want to reprogram the boot FLASH memory with either a custom program or a boot
program update. If the FLASH must be reprogrammed, there are 3 ways to do so:
1. Download a program capable of reburning the FLASH memory using the existing FLASH to
initiate the process. If you only have this means of programming, be careful not to burn a bad
image, as the process is not recoverable without a JTAG debugger or FLASH programmer
(since the PC44 cannot be rebooted from the bad image just downloaded).
2. Use the JTAG Debugger board (available from II) to download a new program into memory
which can burn a new FLASH. If you make a mistake, you can reload the old monitor using
the JTAG into SRAM and try again.
3. Use a ROM programmer to burn a new FLASH chip and insert that into the PC44. It is a good
idea to read out the existing working monitor program before you reburn the FLASH in case
the new program doesn’t work.
The factory installed boot FLASH is a 1M bit (128Kx8) AMD 29F010-120JC. The PC44 may also use the
4 Mbit (512Kx8) AMD 29F040-120JC in the same socket without modification.

PC44 Hardware Manual - 11
1.3 Processor Interrupts
The PC44 provides the option to generate interrupts to processors attached to the PC44 from a number of
on- and off-board sources. These user-selectable connections are made via jumper headers JP41, JP42, and
JP43, which each control the interrupts for one processor (there is a maximum of three processors
installable on a single PC44). Each header selects the signals which will drive up to three external interrupt
inputs per processor (compliant with the TIM-40 specification). Possible sources for these interrupts and
their signal requirements are listed below.
1.3.1 Interrupt Combinations
The following table lists the possible interrupt types and which processors can make use of them, and on
which processor interrupt inputs (this assumes ‘C4x class processors in all sites). Descriptions of each
interrupt type and specific signal requirements are given following the table. The user should make use of
this table when planning the overall system design so as to avoid interrupt conflicts and configuration
problems.
Table 2: Processor Interrupt Types and Reception Compatibility
Interrupt Type Processor A (on-
board) Processor B (TIM-40 Site A) Processor C (TIM_40 Site B)
EXT_INT0 IIOF0 IIOF0 IIOF0
EXT_INT1 IIOF1 IIOF1 IIOF1
EXT_INT2 IIOF2 IIOF2 IIOF2
EXT_INT3 not usable not usable IIOF2
DPORT_INT IIOF0 IIOF0 IIOF0
ADC_A_BUSY IIOF1 IIOF1 IIOF1
ADC_B_BUSY IIOF1 IIOF1 IIOF1
TM_SRC0 IIOF0 IIOF0 IIOF0
TM_SRC1 IIOF1 IIOF1 IIOF1
EXT_TM_SRC0 IIOF2 IIOF2 IIOF2
EXT_TM_SRC1 IIOF2 IIOF2 IIOF2
INT_A_TO_B not usable IIOF2 not usable
INT_B_TO_A IIOF2 not usable not usable
PC_INT0 IIOF2 not usable not usable
PC_INT1 not usable IIOF2 not usable
PC_INT2 not usable not usable IIOF2
Thus, the combinations are limited in that the user does not have the ability to connect any interrupt pin on
any processor to any interrupt source, but the available combinations should prove sufficient if judiciously
allocated.
1.3.2 Interrupt Types
The following section gives descriptions of each interrupt type, its source connection, and any signal
requirements which must be met by external equipment. In all cases, external interrupt and time source
inputs should be low-going TTL with pulse widths no less than one H1 clock width (50 ns on a 40 MHz
PC44).

PC44 Hardware Manual - 12
1. EXT_INT0, 1, 2, and 3: These are externally generated signals delivered to the board via pins
42, 44, 46, and 48 of JP7, respectively. They can be used to signal an outside event requiring
the PC44’s attention.
2. DPORT_INT: This is an interrupt which can optionally be generated by the dual port memory in
both directions, i.e. it can be used by the PC host software to interrupt a processor on the PC44,
and can also be used by a PC44 processor to interrupt the PC. The interrupt is triggered and
cleared by writing and reading certain dual port memory locations. See the data sheet for the
IDT7024 Dual Port Memory in the Appendix for more details.
3. ADC_A_BUSY, ADC_B_BUSY: These interrupts are generated by the channel A and B A/D
converters. The interrupts will occur at the start of the conversion period.
4. TM_SRC0, TM_SRC1: These interrupts are actually downselected outputs from the 82C54
timer chip and processor A TCLK signals. The downselection simplifies the processor
interrupt headers as well as the A/D and D/A conversion clock selection headers. The
downselection is performed on jumpers JP39 (for TM_SRC0) and JP40 (for TM_SRC1). For
more information, see the description of the downselection jumpers in section 2.3.1, “Timer
Source Selection.”
5. EXT_TM_SRC0, EXT_TM_SRC1: These signals are available on the DB37 external
connector. They can serve as externally driven A/D and D/A conversion triggers as well as
processor interrupts.
6. INT_A_TO_B, INT_B_TO_A: These are interprocessor interrupts which are implemented on
the PC44 in board logic as memory-mapped addresses in global space. INT_A_TO_B is
mapped to location 0xFFF1 8000 and INT_B_TO_A is mapped to location 0xFFF1 C000.
Any access to either of these locations by any processor will cause an interrupt on the
accompanying pin. Although the interrupts are intended to be used for interprocessor
messaging, it is possible for processors to trip interrupts to themselves (for instance, processor
B could write to location 0xFFF1 8000 and trip an interrupt to itself).
7. PC_INT0, PC_INT1, PC_INT2: These are interrupts from the ISA bus to one of the processors,
used by host software to flag a condition to target software.