Inrevium TB-FMCH-HDMI2 Instructions for use

TB-FMCH-HDMI2 Hardware User Manual
1
Rev.1.05
TB-FMCH-HDMI2
Hardware User Manual
Rev.1.05

TB-FMCH-HDMI2 Hardware User Manual
2
Rev.1.05
Revision History
Version
Date
Description
Publisher
Rev.1.00
2011/02/01
Initial release
Yoshioka
Rev.1.01
2011/03/29
Modified Figure4-2, 4-3, 5-2, 5-3
Yoshioka
Rev.1.02
2012/10/18
Add Table5-6
Yanagisawa
Rev.1.03
2014/04/15
Add EC Declaration of Conformity
Amano
Rev.1.04
2014/08/13
Modify Table 5-7
Amano
Rev.1.05
2017/05/10
Modify Table 4-7
Goto

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Table of Contents
1. Related Documents and Board Accessories............................................................................... 8
2. Overview...................................................................................................................................... 8
3. Feature ........................................................................................................................................ 9
4. TB-FMCH-HDMI2-RX................................................................................................................ 10
4.1. Block Diagram ......................................................................................................................... 10
4.2. External View of the Board.......................................................................................................11
4.3. Board Specification.................................................................................................................. 12
4.4. Supplying Power to the Board................................................................................................. 13
4.5. HDMI Receiver ........................................................................................................................ 14
4.6. FMC Connector ....................................................................................................................... 15
4.7. Other Interfaces....................................................................................................................... 18
4.7.1. EEPROM Interface.......................................................................................................... 18
4.7.2. JTAG Interface................................................................................................................. 18
4.7.3. General-Purpose Clock Interface.................................................................................... 18
4.8. LED Status............................................................................................................................... 19
4.9. Control Function ...................................................................................................................... 19
4.10. FPGA Pin Assignment ......................................................................................................... 20
4.11. FPGAOutput Data Phase ....................................................................................................... 27
4.12. Image Size........................................................................................................................... 28
4.12.1. 2D Image Size................................................................................................................. 28
4.12.2. 3D Image Size................................................................................................................. 28
5. TB-FMCH-HDMI2-TX................................................................................................................ 29
5.1. Block Diagram ......................................................................................................................... 29
5.2. External View of the Board...................................................................................................... 30
5.3. Board Specification.................................................................................................................. 31
5.4. Power Supply to the Board...................................................................................................... 32
5.5. HDMI Transmitter .................................................................................................................... 33
5.6. FMC Connector ....................................................................................................................... 34
5.7. Other Interfaces....................................................................................................................... 37
5.7.1. JTAG Interface................................................................................................................. 37
5.7.2. General-Purpose Clock Interface.................................................................................... 37
5.8. LED Status............................................................................................................................... 38
5.9. Relation of ROM and Input Video Format ............................................................................... 38
5.10. Control Function .................................................................................................................. 39
5.11. FPGA Pin Assignment ............................................................................................................. 40
5.12. FPGA Input Data Phase ...................................................................................................... 47
5.13. Image Size........................................................................................................................... 48
5.13.1. 2D Image Size................................................................................................................. 48
5.13.2. 3D Image Size................................................................................................................. 48
6. DDC Connection (Normal/ Through)......................................................................................... 49
6.1. DDC Connection (Normal)....................................................................................................... 49
6.2. DDC Connection (Through)..................................................................................................... 50
7. Default Switch Setting ............................................................................................................... 51
8. Usage Example......................................................................................................................... 55

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List of Figures
Figure 3-1 FMC Connector Pin Layout .............................................................................................. 9
Figure 4-1 TB-FMCH-HDMI2-RX Block Diagram............................................................................. 10
Figure 4-2 External View of TB-FMCH-HDMI2-RX (component side)..............................................11
Figure 4-3 External View of TB-FMCH-HDMI2-RX (solder side)......................................................11
Figure 4-4 TB-FMCH-HDMI2-RX Board Dimensions ...................................................................... 12
Figure 4-5 TB-FMCH-HDMI2-RX Power Supply Structure .............................................................. 13
Figure 4-6 FPGA Output Data Timing.............................................................................................. 27
Figure 5-1 TB-FMCH-HDMI2-TX Block Diagram............................................................................. 29
Figure 5-2 TB-FMCH-HDMI2-TX (component side) ........................................................................ 30
Figure 5-3 TB-FMCH-HDMI2-TX (solder side)................................................................................. 30
Figure 5-4 TB-FMCH-HDMI2-TX Board Dimensions....................................................................... 31
Figure 5-5 TB-FMCH-HDMI2-TX Power Supply Structure............................................................... 32
Figure 5-6 FPGA Input Data Timing................................................................................................. 47
Figure 6-1 DDC Connection Structure (Normal) .............................................................................. 49
Figure 6-2 DDC Connection Structure (Through) ............................................................................ 50
Figure 7-1 TB-FMCH-HDMI2-RX Default Switch Settings (component side).................................. 51
Figure 7-2 TB-FMCH-HDMI2-TX Default Settings (component side).............................................. 53
Figure 8-1 Usage Example .............................................................................................................. 55
List of Tables
Table 2-1 ROM data ........................................................................................................................... 8
Table 4-1 HDMI Connector (receiving side)..................................................................................... 14
Table 4-2 SCL/SDA Jumper Setting................................................................................................. 14
Table 4-3 JP1 Jumper Setting.......................................................................................................... 15
Table 4-4 FMC Connector Pin Assignment...................................................................................... 16
Table 4-5 JTAG Connector............................................................................................................... 18
Table 4-6 LED Status........................................................................................................................ 19
Table 4-7 Switches........................................................................................................................... 19
Table 4-8 FPGA Pin Assignment...................................................................................................... 20
Table 5-1 HDMI Connector (transmit side)....................................................................................... 33
Table 5-2 JP3 Jumper Setting.......................................................................................................... 34
Table 5-3 FMC Connector Pin Assignment...................................................................................... 35
Table 5-4 JTAG Connector............................................................................................................... 37
Table 5-5 LED Status........................................................................................................................ 38
Table 5-6 Relation of ROM and Input Video Format........................................................................ 38
Table 5-7 Switch Function................................................................................................................ 39
Table 5-8 FPGA Pin Assignment...................................................................................................... 40
Table 6-1 DDC Jumper Setting (Normal) ......................................................................................... 49
Table 6-2 DDC Jumper Setting (Through)........................................................................................ 50
Table 7-1 TB-FMCH-HDMI2-RX Default Settings (JP pin)............................................................... 51
Table 7-2 TB-FMCH-HDMI2-RX Default Setting (DSW/RSW)......................................................... 52
Table 7-3 TB-FMCH2-TX Default Settings (JP Pin)......................................................................... 53
Table 7-4 TB-FMCH-HDMI2-TX Default Switch Settings (DSW/RSW)............................................ 54
Table 8-1 Setting Example ............................................................................................................... 55

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Introduction
Thank you for purchasing the TB-FMCH-HDMI2－RX/TB-FMCH-HDMI2-TX boards. Before using the
product, be sure to carefully read this user manual and fully understand how to correctly use the product.
First read through this manual, then always keep it handy.
SAFETY PRECAUTIONS Be sure to observe these precautions
Observe the precautions listed below to prevent injuries to you or other personnel or damage to property.
Before using the product, read these safety precautions carefully to assure correct use.
These precautions contain serious safety instructions that must be observed.
After reading through this manual, be sure to always keep it handy.
The following conventions are used to indicate the possibility of injury/damage and classify precautions if
the product is handled incorrectly.
Indicates the high possibility of serious injury or death if the product is handled
incorrectly.
Indicates the possibility of serious injury or death if the product is handled
incorrectly.
Indicates the possibility of injury or physical damage in connection with houses or
household goods if the product is handled incorrectly.
The following graphical symbols are used to indicate and classify precautions in this manual.
(Examples)
Turn off the power switch.
Do not disassemble the product.
Do not attempt this.
Danger
Warning
Caution

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In the event of a failure, disconnect the power supply.
If the product is used as is, a fire or electric shock may occur. Disconnect the power supply
immediately and contact our sales personnel for repair.
If an unpleasant smell or smoking occurs, disconnect the power supply.
If the product is used as is, a fire or electric shock may occur. Disconnect the power supply
immediately. After verifying that no smoking is observed, contact our sales personnel for
repair.
Do not disassemble, repair or modify the product.
Otherwise, a fire or electric shock may occur due to a short circuit or heat generation. For
inspection, modification or repair, contact our sales personnel.
Do not touch a cooling fan.
As a cooling fan rotates in high speed, do not put your hand close to it. Otherwise, it may
cause injury to persons. Never touch a rotating cooling fan.
Do not place the product on unstable locations.
Otherwise, it may drop or fall, resulting in injury to persons or failure.
If the product is dropped or damaged, do not use it as is.
Otherwise, a fire or electric shock may occur.
Do not touch the product with a metallic object.
Otherwise, a fire or electric shock may occur.
Do not place the product in dusty or humid locations or where water may
splash.
Otherwise, a fire or electric shock may occur.
Do not get the product wet or touch it with a wet hand.
Otherwise, the product may break down or it may cause a fire, smoking or electric shock.
Do not touch a connector on the product (gold-plated portion).
Otherwise, the surface of a connector may be contaminated with sweat or skin oil, resulting
in contact failure of a connector or it may cause a malfunction, fire or electric shock due to
static electricity.
Warning

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Do not use or place the product in the following locations.
Humid and dusty locations
Airless locations such as closet or bookshelf
Locations which receive oily smoke or steam
Locations exposed to direct sunlight
Locations close to heating equipment
Closed inside of a car where the temperature becomes high
Staticky locations
Locations close to water or chemicals
Otherwise, a fire, electric shock, accident or deformation may occur due to a short circuit or heat
generation.
Do not place heavy things on the product.
Otherwise, the product may be damaged.
■Disclaimer
This product is HDMI interface for Xilinx FPGA evaluation boards. Tokyo Electron Device Limited
assumes no responsibility for any damages resulting from the use of this product for purposes other than
those stated.
Even if the product is used properly, Tokyo Electron Device Limited assumes no responsibility for any
damages caused by:
(1) Earthquake, thunder, natural disaster or fire resulting from the use beyond our responsibility, acts by
a third party or other accidents, the customer’s willful or accidental misuse or use under other
abnormal conditions.
(2) Secondary impact arising from use of this product or its unusable state (business interruption or
others)
(3) Use of this product against the instructions given in this manual.
(4) Malfunctions due to connection to other devices.
Tokyo Electron Device Limited assumes no responsibility or liability for:
(1) Erasure or corruption of data arising from use of this product.
(2) Any consequences or other abnormalities arising from use of this product, or
(3) Damage of this product not due to our responsibility or failure due to modification
This product has been developed by assuming its use for research, testing or evaluation. It is not
authorized for use in any system or application that requires high reliability.
Repair of this product is carried out by replacing it on a chargeable basis, not repairing the faulty devices.
However, non-chargeable replacement is offered for initial failure if such notification is received within
two weeks after delivery of the product.
The specification of this product is subject to change without prior notice.
The product is subject to discontinuation without prior notice.
Caution

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1. Related Documents and Board Accessories
All documents relating to this board can be downloaded from our website Club-X.
Accessories:
Interboard spacers and screws
Interboard jumper cable
2. Overview
The TB-FMCH-HDMI2 comes either with AnalogDevices’s HDMI Receiver "ADV7612BSWZ-P" or
HDMI Transmitter "ADV7511KSTZ-P".
(Collectively, there are called TB-FMCH-HDMI2. This document specifically describes these
optional boards in the RX and TX sections respectively).
Each board has two independent receivers/transmitters and is designed for high resolution
support.
It uses Samtec’s FMC connector and Molex’s HDMI connector for connection with a platform board
having High-Pin Count connectors.
This User Manual is refer to Initial ROM files.
TB-FMCH-HDMI2 boards need to download following ROM files.
Table 2-1 ROM data
No
Board name
FPGA ROM data
1
TB-FMCH-HDMI2-RX
rx_fpga_top.mcs
2
TB-FMCH-HDMI2-TX
tx_fpga_top.mcs

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3. Feature
HDMI Devices
Receiver : AnalogDevices’s ADV7612BSWZ-P
Transmitter : AnalogDevices’s ADV7511KSTZ-P
FMC Connector : Samtec’s ASP-134488-01
HDMI Connector (common) : Molex’s 5002541927
Power Supply (common) : Jumper switch selection
The RX board has an EEPROM for Display Data Channel (hereafter referred to as DDC) and allows
setting the AnalogDevices’s ADV7612BSWZ-P board operation via jumpers.
Figure 3-1 FMC Connector Pin Layout

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4. TB-FMCH-HDMI2-RX
4.1. Block Diagram
Figure 4-1 shows the TB-FMCH-HDMI2-RX block diagram.
The FMC-HPC connector is mounted on the solder side of the board.
XC6SLX45-3FGG484C
FPGAFMC-HPC
DEC#0
500254-1927
HDMI#0（RX)
ADV7612
RX#0_C、RX#0_0～2
RX#0_P[35:0]
RX#0_VS/HS/DE
RX#0_LLC
RX#0_DDCA_SCL
CEC#0
DET0
HPD#0
28.6363MHz
RX#0_SPDIF
RX#0_I2S[3:0]
RX#0_SCLK
RX#0_LRCLK
RX#0_MCLKOUT
RX#0_SCL
RX#0_INT1/CSN
RX#0_RESETN
PROM
ASP-134488-01
XCF16PFSG48C
LA[33:00]_P/N
HA[23:00]_P/N
CLK[3:0]_M2C_P/N
FPGA_D[7:0]
FPGA_DONE
FPGA_INITB
FPGA_PROGB
FPGA_CCLK
FPGA_TCK/TMS/TDI/TDO
EEPROM#0
24LCS22A
CLK
SYSCLK_P
RX#0_SDA
RX#0_DDCA_SDA
LED[7:0]
DSW[7:0]
RSW[3:0]
JTAG
87832-1420
KC5032C27.000
RX#0_HPD_IO
DDC0_GND
DDC0
DDC0_HPD
DDC0_5V
DDC0_SDA
RX#0_CEC
RX#0_DDCA_SDA_F
RX#0_DDCA_SCL_F
RX#0_DET1
DDC0_SCL
DDC_GND0
DEC#1
500254-1927
HDMI#1（RX)
ADV7612
RX#1_C、RX#1_0～2
RX#1_P[35:0]
RX#1_VS/HS/DE
RX#1_LLC
RX#1_DDCA_SCL
CEC#1
DET1
HPD#1
28.6363MHz
RX#1_SPDIF
RX#1_I2S[3:0]
RX#1_SCLK
RX#1_LRCLK
RX#1_MCLKOUT
RX#1_SCL
RX#1_INT1/CSN
RX#1_RESETN
EEPROM#1
24LCS22A
RX#1_SDA
RX#1_DDCA_SDA
RX#1_HPD_IO
DDC1_GND
DDC1
DDC1_HPD
DDC1_5V
DDC1_SDA
RX#1_CEC
RX#1_DDCA_SDA_F
RX#1_DDCA_SCL_F
RX#1_DET1
DDC1_SCL
DDC_GND1
Figure 4-1 TB-FMCH-HDMI2-RX Block Diagram
Main Functions:
1. HDMI receive function (ADV7612 => FPGA)
2. FMC connector interface (FPGA => FMC-HPC connector)
3. EEPROM interface
4. JTAG interface
5. General-purpose clock interface (27MHz)
6. General-purpose switch
7. General-purpose LED
8. DDC connection (Normal/ Through)

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4.2. External View of the Board
Figures 4-2 and 4-3 show the external view of the TB-FMCH-HDMI2-RX board.
Caution : This board has a plastic cover for protecting HDMI devices. Do not remove a plastic cover.
HDMI ConnectorHDMI ReceiverFPGA
Figure 4-2 External View of TB-FMCH-HDMI2-RX (component side)
FMC-HPC
Figure 4-3 External View of TB-FMCH-HDMI2-RX (solder side)

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4.3. Board Specification
The following shows TB-FMCH-HDMI2-RX board specifications.
External Dimensions : W:160mm x H:69mm
Number of Layers : 8 layers
Board Thickness : 1.6 mm
Material : FR-4
FPGA : Xilinx’s XC6SLX45-3FGG484C
FMC Connector : Samtec’s ASP-134488-01
HDMI Connector : Molex’s 5002541927
Figure 4-4 TB-FMCH-HDMI2-RX Board Dimensions

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4.4. Supplying Power to the Board
Figure 4-5 shows a TB-FMCH-HDMI2-RX power supply structure.
VCC_12V_IN VCC_5V
LT3503EDCB
VCC_1.8V0
LTC3026EMSE
VCC_1.8V1
LTC3026EMSE
ADV7612 : 449.7mA
VCC_3.3V
FPGA_VCAUX : 50mA FPGA_VCCIO : 29mA
ADV7612 : 312.5mA x2 = 625mA
1170mA
KC3225A: 6mA
NC7SZ125: 0.02mA x2 = 0.04mA
24LCS22A: 3mA x2 = 6mA
LTC1326: 0.04mA
135mA
VCC_2.5V
（2.926W）
750mA
(2.475W)
（0.677W）
562mA
LT3503EDCB
LT3568EDD
FPGA_VCCINT : 485mA
VCC_1.2V
FPGA_VCCIO : 261mA
XCF16 VCCINT : 10mA
ADV7612 : 449.7mA
XCF16 VCCIO : 40mA
LT3503EDCB
Figure 4-5 TB-FMCH-HDMI2-RX Power Supply Structure

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4.5. HDMI Receiver
HDMI Connector uses a 5002541927 (MOLEX).
HDMI Receiver uses an ADV7612BSWZ-P (Analog Devices).
The following device is used as ESD protection.
ESD protection: RCLAMP0524 and RCLAMP0504 (Semtech)
Table 4-1 shows the HDMI connector pin assignments.
Table 4-1 HDMI Connector (receiving side)
Pin #
Name
Description
1
TMDS DATA2+
TMDS receive data 2+
2
TMDS SHLD2
TMDS receive data 2 shield
3
TMDS DATA2-
TMDS receive data 2-
4
TMDS DATA1+
TMDS receive data 1+
5
TMDS SHLD1
TMDS receive data 1 shield
6
TMDS DATA1-
TMDS receive data 1-
7
TMDS DATA0+
TMDS receive data 0+
8
TMDS SHLD0
TMDS receive data 0 shield
9
TMDS DATA0-
TMDS receive data 0-
10
TMDS CLK+
TMDS receive clock+
11
TMDS CLK SHLD
TMDS receive clock shield
12
TMDS CLK-
TMDS receive clock-
13
CEC
CEC signal
14
RESERVED
Reserved
15
DDC_SCL
DDC serial clock
16
DDC_SDA
DDC serial data
17
DDC/CEC GND
DDC/CEC ground
18
DDC_+5V
+5V power supply
19
HOTPLUG_DET
Hot-plug detection
The receiver has an EEPROM (24LCS22A-SN: Micro Chip).
This EEPROM is used to store EDID data. The SCL signal can be switched by JP6/JP3 and the SDA
signal using JP7/JP4.
Note: At factory default settings, the EEPROM stores temporary data to enable output of image data
from an image output device. The ID used in the data is a dummy ID for evaluation purposes.
So, do not use it for actual products.
Table 4-2 SCL/SDA Jumper Setting
No
Purpose
Silk
Setting
1
DDC connection
(Normal)
JP6: SCL0, JP7: SDA0
JP3: SCL1,JP4: SDA1
JP6: 1-2 short JP7: 1-2 short
JP3: 1-2 short JP4: 1-2 short
2
DDC
connection(Through)
JP6: SCL0, JP7: SDA0
JP3: SCL1,JP4: SDA1
JP6: 2-3 short JP7: 2-3 short
JP3: 2-3 short JP4: 2-3 short

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4.6. FMC Connector
The FMC connector (High-Pin Count) connecting to the main board uses an ASP-134488-01 (SAMTEC).
Power to the TB-FMCH-HDMI2-RX is supplied from a +12V on the main board.
An external power source can also be used.
Table 4-3 shows JP1 jumper setting for power supply.
Table 4-3 JP1 Jumper Setting
No
Purpose
Silk
Setting
1
FMC connector
12VIN_SEL
JP1: 1-2 short
2
External power supply
12VIN_SEL
JP1: 2-3 short
To connect an external power source, use the following test pin:
TP14: 12VIN

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Table 4-4 shows the FMC connector pin assignment.
Table 4-4 FMC Connector Pin Assignment
Pin
A-row
B-row
C-row
D-row
E-row
1
GND
RES1
GND
PG_C2M
GND
2
DP1_M2C_P
GND
DP0_C2M_P
GND
HA01_P_CC
3
DP1_M2C_N
GND
DP0_C2M_N
GND
HA01_N_CC
4
GND
DP9_M2C_P
GND
GBTCLK0_M2C_P
GND
5
GND
DP9_M2C_N
GND
GBTCLK0_M2C_N
GND
6
DP2_M2C_P
GND
DP0_M2C_P
GND
HA05_P
7
DP2_M2C_N
GND
DP0_M2C_N
GND
HA05_N
8
GND
DP8_M2C_P
GND
LA01_P_CC
GND
9
GND
DP8_M2C_N
GND
LA01_N_CC
HA09_P
10
DP3_M2C_P
GND
LA06_P
GND
HA09_N
11
DP3_M2C_N
GND
LA06_N
LA05_P
GND
12
GND
DP7_M2C_P
GND
LA05_N
HA13_P
13
GND
DP7_M2C_N
GND
GND
HA13_N
14
DP4_M2C_P
GND
LA10_P
LA09_P
GND
15
DP4_M2C_N
GND
LA10_N
LA09_N
HA16_P
16
GND
DP6_M2C_P
GND
GND
HA16_N
17
GND
DP6_M2C_N
GND
LA13_P
GND
18
DP5_M2C_P
GND
LA14_P
LA13_N
HA20_P
19
DP5_M2C_N
GND
LA14_N
GND
HA20_N
20
GND
GBTCLK1_M2C_P
GND
LA17_P_CC
GND
21
GND
GBTCLK1_M2C_N
GND
LA17_N_CC
HB03_P
22
DP1_C2M_P
GND
LA18_P_CC
GND
HB03_N
23
DP1_C2M_N
GND
LA18_N_CC
LA23_P
GND
24
GND
DP2_C9M_P
GND
LA23_N
HB05_P
25
GND
DP2_C9M_N
GND
GND
HB05_N
26
DP2_C2M_P
GND
LA27_P
LA26_P
GND
27
DP2_C2M_N
GND
LA27_N
LA26_N
HB09_P
28
GND
DP2_C8M_P
GND
GND
HB09_N
29
GND
DP2_C8M_N
GND
TCK
GND
30
DP3_C2M_P
GND
SCL
TDI
HB13_P
31
DP3_C2M_N
GND
SDA
TDO
HB13_N
32
GND
DP2_C7M_P
GND
+3.3VAUX
GND
33
GND
DP2_C7M_N
GND
TMS
HB19_P
34
DP4_C2M_P
GND
GA0
TRST
HB19_N
35
DP4_C2M_N
GND
+12V
GA1
GND
36
GND
DP2_C6M_P
GND
+3.3V
HB21_P
37
GND
DP2_C6M_N
+12V
GND
HB21_N
38
DP5_C2M_P
GND
GND
+3.3V
GND
39
DP5_C2M_N
GND
+3.3V
GND
VADJ
40
GND
RES0
GND
+3.3V
GND

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Pin
F-row
G-row
H-row
J-row
K-row
1
PG_M2C
GND
VREF_A_M2C
GND
VREF_B_M2C
2
GND
CLK1_M2C_P
PRSNT_M2C_L
CLK3_M2C_P
GND
3
GND
CLK1_M2C_N
GND
CLK3_M2C_N
GND
4
HA00_P_CC
GND
CLK0_M2C_P
GND
CLK2_M2C_P
5
HA00_N_CC
GND
CLK0_M2C_N
GND
CLK2_M2C_N
6
GND
LA00_P_CC
GND
HA03_P
GND
7
GND
LA00_N_CC
LA02_P
HA03_N
HA02_P
8
HA04_P
GND
LA02_N
GND
HA02_N
9
HA04_N
LA03_P
GND
HA07_P
GND
10
GND
LA03_N
LA04_P
HA07_N
HA06_P
11
HA08_P
GND
LA04_N
GND
HA06_N
12
HA08_N
LA08_P
GND
HA11_P
GND
13
GND
LA08_N
LA07_P
HA11_N
HA10_P
14
HA12_P
GND
LA07_N
GND
HA10_N
15
HA12_N
LA12_P
GND
HA14_P
GND
16
GND
LA12_N
LA11_P
HA14_N
HA17_P_CC
17
HA15_P
GND
LA11_N
GND
HA17_N_CC
18
HA15_N
LA16_P
GND
HA18_P
GND
19
GND
LA16_N
LA15_P
HA18_N
HA21_P
20
HA19_P
GND
LA15_N
GND
HA21_N
21
HA19_N
LA20_P
GND
HA22_P
GND
22
GND
LA20_N
LA19_P
HA22_N
HA23_P
23
HB02_P
GND
LA19_N
GND
HA23_N
24
HB02_N
LA22_P
GND
HB01_P
GND
25
GND
LA22_N
LA21_P
HB01_N
HB00_P_CC
26
HB04_P
GND
LA21_N
GND
HB00_N_CC
27
HB04_N
LA25_P
GND
HB07_P
GND
28
GND
LA25_N
LA24_P
HB07_N
HB06_P_CC
29
HB08_P
GND
LA24_N
GND
HB06_N_CC
30
HB08_N
LA29_P
GND
HB11_P
GND
31
GND
LA29_N
LA28_P
HB11_N
HB10_P
32
HB12_P
GND
LA28_N
GND
HB10_N
33
HB12_N
LA31_P
GND
HB15_P
GND
34
GND
LA31_N
LA30_P
HB15_N
HB14_P
35
HB16_P
GND
LA30_N
GND
HB14_N
36
HB16_N
LA33_P
GND
HB18_P
GND
37
GND
LA33_N
LA32_P
HB18_N
HB17_P_CC
38
HB20_P
GND
LA32_N
GND
HB17_N_CC
39
HB20_N
VADJ
GND
VIO_B_M2C
GND
40
VADJ
GND
VADJ
GND
VIO_B_M2C

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Rev.1.05
4.7. Other Interfaces
The board also has the following interfaces.
4.7.1. EEPROM Interface
I2C interface used to control the EEPROM from the FPGA
EEPROM device: 24LCS22A-SN (Micro Chip)
4.7.2. JTAG Interface
JTAG connector for FPGA configuration
JTAG connector: 87832-1420 (Molex)
Table 4-5 JTAG Connector
Pin
Signal
Pin
Signal
1
GND
2
3.3V
3
GND
4
TMS
5
GND
6
TCK
7
GND
8
TDO
9
GND
10
TDI
11
GND
12
NC
13
GND
14
NC
4.7.3. General-Purpose Clock Interface
General-purpose clock for FPGA (27MHz crystal oscillator)
KC5032C027.0000C30E00 (Kyocera)

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Rev.1.05
4.8. LED Status
Table 4-6 shows the onboard LEDs.
Table 4-6 LED Status
No
Circuit #
Silk
Purpose
Description
1
DS1
LED0
General-purpose LED0
[RX0]I2C config state
Off: CFG done / On: CFG active
2
DS2
LED1
General-purposeLED1
[RX0]I2C read back
Off: Error / On: No error
3
DS3
LED2
General-purposeLED2
[RX1]I2C config state
Off: CFG done / On: CFG active
4
DS4
LED3
General-purposeLED3
[RX1]I2C read back
Off: Error / On: No error
5
DS5
LED4
General-purposeLED4
Unused (On)
6
DS6
LED5
General-purposeLED5
[RX0] Input video image clock monitor
Flashing: Clock / Off: No clock
7
DS7
LED6
General-purposeLED6
[RX1] Input video image clock monitor
Flashing: Clock / Off: No clock
8
DS8
LED7
General-purposeLED7
System reset monitor
On: Reset active / Off: Reset released
9
DS10
HPD0
RX0 hot-plug display
On: Connected state
10
DS9
HPD1
RX1 hot-plug display
On: Connected state
11
DS11
DONE
Config display
On: Config done
12
DS12
12VLED
12V display
On: 12V active
4.9. Control Function
Table 4-7 shows the onboard switch function.
Table 4-7 Switches
No
Circuit #
Silk
Function
1
S1-1
DSW
ADV7612 config ROM selection
*Should set all On
2
S1-2
DSW
3
S1-3
DSW
4
S1-4
DSW
5
S1-5
DSW
On
6
S1-6
DSW
Unused
7
S1-7
DSW
Unused
8
S1-8
DSW
Unused
9
S2
RSW
Unused
10
S3
RST
FPGA reconfig (long push: 3 seconds)
FPGA reset (short push)

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Rev.1.05
4.10. FPGA Pin Assignment
Table 4-8 shows the FPGA pin assignment.
In case of 8-bit signal format, active bits are assigned to MSB 8-bit of each RGB pin of FMC. LSB 2-bit
are always 2'b00 in 8-bit signal format.
Table 4-8 FPGA Pin Assignment
Pin Name
No.
IO
Spec
Description
CLK0_M2C_P
B10
O
LVCMOS25
RX#0_LLC signal (FPGA to FMC)
CLK1_M2C_P
C11
O
LVCMOS25
RX#1_LLC signal (FPGA to FMC)
LA00_P_CC
D6
O
LVCMOS25
RX#0_VSYNC signal (FPGA to FMC)
LA01_P_CC
C7
O
LVCMOS25
RX#0_HSYNC signal (FPGA to FMC)
LA02_P
D9
O
LVCMOS25
RX#0_DE signal (FPGA to FMC)
LA03_P
D7
O
LVCMOS25
RX#0_P0 signal (FPGA to FMC) [B0]
LA04_P
C13
O
LVCMOS25
RX#0_P1 signal (FPGA to FMC) [B1]
LA05_P
B14
O
LVCMOS25
RX#0_P2 signal (FPGA to FMC) [B2]
LA06_P
D15
O
LVCMOS25
RX#0_P3 signal (FPGA to FMC) [B3]
LA07_P
C17
O
LVCMOS25
RX#0_P4 signal (FPGA to FMC) [B4]
LA08_P
E16
O
LVCMOS25
RX#0_P5 signal (FPGA to FMC) [B5]
LA09_P
G16
O
LVCMOS25
RX#0_P6 signal (FPGA to FMC) [B6]
LA10_P
B21
O
LVCMOS25
RX#0_P7 signal (FPGA to FMC) [B7]
LA11_P
K16
O
LVCMOS25
RX#0_P8 signal (FPGA to FMC) [B8]
LA12_P
D19
O
LVCMOS25
RX#0_P9 signal (FPGA to FMC) [B9]
LA13_P
D21
O
LVCMOS25
RX#0_P10 signal (FPGA to FMC) [G0]
LA14_P
G19
O
LVCMOS25
RX#0_P11 signal (FPGA to FMC) [G1]
LA15_P
E20
O
LVCMOS25
RX#0_P12 signal (FPGA to FMC) [G2]
LA16_P
F21
O
LVCMOS25
RX#0_P13 signal (FPGA to FMC) [G3]
LA17_P_CC
G20
O
LVCMOS25
RX#0_P14 signal (FPGA to FMC) [G4]
LA18_P_CC
H21
O
LVCMOS25
RX#0_P15 signal (FPGA to FMC) [G5]
LA19_P
J20
O
LVCMOS25
RX#0_P16 signal (FPGA to FMC) [G6]
LA20_P
L20
O
LVCMOS25
RX#0_P17 signal (FPGA to FMC) [G7]
LA21_P
N20
O
LVCMOS25
RX#0_P18 signal (FPGA to FMC) [G8]
LA22_P
R20
O
LVCMOS25
RX#0_P19 signal (FPGA to FMC) [G9]
LA23_P
U20
O
LVCMOS25
RX#0_P20 signal (FPGA to FMC) [R0]
LA24_P
M19
O
LVCMOS25
RX#0_P21 signal (FPGA to FMC) [R1]
LA25_P
M16
O
LVCMOS25
RX#0_P22 signal (FPGA to FMC) [R2]
LA26_P
P19
O
LVCMOS25
RX#0_P23 signal (FPGA to FMC) [R3]
LA27_P
W20
O
LVCMOS25
RX#0_P24 signal (FPGA to FMC) [R4]
LA28_P
L17
O
LVCMOS25
RX#0_P25 signal (FPGA to FMC) [R5]
LA29_P
U19
O
LVCMOS25
RX#0_P26 signal (FPGA to FMC) [R6]
LA30_P
M17
O
LVCMOS25
RX#0_P27 signal (FPGA to FMC) [R7]
LA31_P
P17
O
LVCMOS25
RX#0_P28 signal (FPGA to FMC) [R8]
LA32_P
P18
O
LVCMOS25
RX#0_P29 signal (FPGA to FMC) [R9]
LA33_P
T19
IO
LVCMOS25
Unused
CLK0_M2C_N
A10
IO
LVCMOS25
Unused
CLK1_M2C_N
A11
IO
LVCMOS25
Unused