Intel LXD9781 User manual

LXD9781 PQFP Demo Board with
FPGAs for RMII-to-MII
Conversion
Developer Manual
January 2001
As of January 15, 2001, this document replaces the Level One document Order Number: 249043-001
LXD9781 PQFP Demo Board with FPGAs for RMII-to-MII Conversion User Guide.

LXD9781 PQFP Demo Board with FPGAs for RMII-to-MII Conversion Developer Manual
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Designers must not rely on the absence or characteristics of any features or instructions marked “reserved”or “undefined.”Intel reserves these for
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The LXD9781 PQFP Demo Board with FPGAs for RMII-to-MII Conversion may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
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Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.

LXD9781 PQFP Demo Board with FPGAs for RMII-to-MII Conversion Developer Manual iii
Contents
1.0 General Description ..................................................................................................5
1.1 Features................................................................................................................5
2.0 Introduction..................................................................................................................7
2.1 Overview ...............................................................................................................7
2.2 Equipment Requirements......................................................................................7
2.3 Typical Setup.........................................................................................................7
3.0 Quick-Start Checklist..............................................................................................10
4.0 Optional Configurations........................................................................................11
4.1 Global Operating Configurations.........................................................................11
4.2 LED/CFG Configurations.....................................................................................11
4.3 MII Address Configurations.................................................................................12
4.4 Alternate MDIO Routing Configuration................................................................13
4.5 Alternate Power Supply Configuration ................................................................13
4.6 Alternate MII Speed Configuration......................................................................14
5.0 LEDs..............................................................................................................................15
5.1 Quick Status LEDs ..............................................................................................15
5.2 Serial LEDs .........................................................................................................15
5.3 Direct Drive LEDs................................................................................................16
6.0 Fiber Setup ................................................................................................................18
6.1 Fiber Modules......................................................................................................18
7.0 Board Schematics and Bill of Materials..........................................................19
7.1 Bill of Materials....................................................................................................38

iv LXD9781 PQFP Demo Board with FPGAs for RMII-to-MII Conversion Developer Manual
Figures
1 LXD9781 PQFP Demo Board Block Diagram.......................................................6
2 Typical Test Setup ...............................................................................................8
3 LXD9781 MII Demo Board....................................................................................9
4 LXT97x1 Power (Board Revision B1) .................................................................19
5 MII Ports 0 and 1.................................................................................................20
6 MII Ports 2 and 3.................................................................................................21
7 MII Ports 4 and 5.................................................................................................22
8 MII Ports 6 and 7.................................................................................................23
9 Twisted-Pair Ports 0 and 1..................................................................................24
10 Twisted-Pair Ports 2 and 3..................................................................................25
11 Twisted-Pair Ports 4 and 5..................................................................................26
12 Twisted-Pair Ports 6 and 7..................................................................................27
13 Fiber Interface.....................................................................................................28
14 LED/CONFIG Ports 0 - 3.....................................................................................29
15 LED/CONFIG Ports 4 - 7.....................................................................................30
16 Serial LED 1........................................................................................................31
17 Serial LED 2........................................................................................................32
18 Serial LED 3........................................................................................................33
19 MII Converter FPGAs..........................................................................................34
20 QSTAT FPGA .....................................................................................................35
21 Capacitors...........................................................................................................36
22 Clock...................................................................................................................37
Tables
1 Quick-Start Jumper Settings ...............................................................................10
2 Quick-Start Switch Settings.................................................................................10
3 Global Configuration Settings (Switch S1)..........................................................11
4 LED/CFG_n Port Configuration Jumpers............................................................11
5 Configuration Settings for Auto-Negotiation........................................................12
6 Configuration Settings for Forced Operation.......................................................12
7 PHY Address Configuration Settings (Jumpers JP66 - JP70) ............................13
8 MDIO Routing .....................................................................................................13
9 Twisted-Pair Transmit Driver Supply...................................................................14
10 MII Port Speed Select.........................................................................................14
11 Manual MII Speed Settings (Switch S6)..............................................................14
12 Quick Status Clock Settings................................................................................15
13 Serial LED Outputs .............................................................................................15
14 Direct Drive LED Configuration Settings (Register 20).......................................17
15 LED Pulse Stretch Settings (Register 20)...........................................................17
16 MII Port Connections for Fiber Module Operation...............................................18
17 LXT9781 Bill of Materials....................................................................................38

LXD9781 PQFP Demo Board
Developer Manual 5
1.0 General Description
The LXD9781 Demo Board is an eight-port 10/100 Mbps Fast Ethernet Media Access Unit (MAU)
that provides a working platform for evaluation of the LXT9781 Fast Ethernet 10/100 Octal
Transceiver in 10BASE-T and/or 100BASE-TX/FX applications.
All eight network ports provide a combination twisted-pair (TP) for a 10/100BASE-TX connection
or pseudo-ECL (PECL) interface for a 100BASE-FX connection.
The LXD9781 Demo Board allows system designers to test 10 Mbps and 100 Mbps link
performance, auto-negotiation, and register functionality using a standard MII interface prior to
board prototyping. Four FPGAs convert the eight RMII interfaces on the LXT9781 to eight
standard MII interfaces. This simplifies evaluation of the LXT9781, rendering it compatible with
existing MII test equipment.
The LXD9781 requires only a single 3.3V power supply. Refer to the latest LXT9761/81 data sheet
for device functionality and specifications.
1.1 Features
•Eight independent IEEE 802.3-compliant 10BASE-T or 100BASE-TX ports.
•Quick setup, ease of use, and clear visibility of application settings for:
—- Complete system demonstration.
—- Individual circuit isolation.
•JTAG boundary scan.
•Auto-negotiation protocol compliant with legacy systems that do not support auto-negotiation.
•Three LED options for major functions:
—- Direct drive LEDs.
—- Serial LED output.
—- Quick Status LED output.
•Configurable via MDIO port or hardware jumpers.
•Half- or full-duplex operation at 10 or 100 Mbps.
•100BASE-FX fiber-optic capability on all ports.

LXD9781 PQFP Demo Board
6Developer Manual
Figure 1. LXD9781 PQFP Demo Board Block Diagram
LXT9781
Txfmr T1 Txfmr T2
RJ-45
2 x 4
FPGA
RMII-MII Converter
Port 0 MII
Header Port 1 MII Header Port 2 MII Header Port 3 MII Header Port 4 MII Header Port 5 MII Header Port 6 MII Header Port 7 MII Header
Config Logic
Switches & Jumpers Serial LED Output Converter Serial LEDs
QSTAT Serial
Output Converter Segment LED
FPGA
RMII-MII Converter
FPGA
RMII-MII Converter
FPGA
RMII-MII Converter
REFCLK & QSTAT Clocks
+3.3V Power
Supply Direct Drive LEDs
Optional Fiber ModuleOptional Fiber Module

LXD9781 PQFP Demo Board
Developer Manual 7
2.0 Introduction
2.1 Overview
This document describes typical hardware set-up procedures for the LXD9781 MII demo board. To
begin immediate operation, a “Quick-Start Checklist”on page 10 supports both 10BASE-T and
100BASE-TX operation.
Each port on the LXD9781 may be set independently. Optional configurations are discussed
starting on page 11, providing additional information for various alternative configurations.
The LXD9781 provides three sets of LED indicators: direct drive, per-port LEDs; a set of eight
serial LED outputs that are decoded to drive 64 individual LEDs; and a serial Quick Status output
that is decoded to drive a set of 14 LEDs. The QSTAT LEDs reflect the status of a single port, but
any of the eight network ports can be selected. For details, refer to “LEDs”on page 15.
For added flexibility, the LXD9781 provides two Pseudo-ECL (PECL) interfaces for 100BASE-
FX operation. Follow the hardware modifications in the Fiber Setup section on page 18 to install
external fiber optic modules.
Board schematics, and a Bill of Materials are located in the back of the document. Gerber files are
available by contacting your local sales office (see the back page).
2.2 Equipment Requirements
The LXD9781 Demo Board is populated with all of the IC components needed for twisted-pair
evaluation. However, the following additional equipment is also required:
•SmartBits Advanced Multi-port Performance Test Box
•PC with Smart Windows (version 6.51 or newer) installed.
•3.3V DC Power Supply.
•Eight MII Cables (male to male).
•Eight external NIC cards.
•Eight Category 5 Unshielded Twisted-Pair (UTP) cables.
•Fiber-optic transceiver modules (HFBR-5903 or similar), fiber-optic cable, and external
jumpers are required for 100BASE-FX evaluation.
2.3 Typical Setup
Figure 2 shows a typical test setup for standard operation of the LXD9781. The LXD9781 plugs
into a SmartBits Advanced Multi-port Performance Test Box via eight standard 40-pin MII cables
that are not included on the board. Eight external NIC cards directly connect to the SmartBits test
box and plug into the LXD9781 through RJ45 connections. Each port’s operating speed can be set
individually for evaluation of 10 Mbps, 100 Mbps, and auto-negotiation capabilities using all eight
ports.

LXD9781 PQFP Demo Board
8Developer Manual
Figure 2. Typical Test Setup
UTP
MII
Connectors
SmartBits
Advanced Multi-port
Performance
Tester
MII Cable
)
LXD9781
External
NIC
Cards
Smart
Windows
RS-232
Dual-High
RJ45

LXD9781 PQFP Demo Board
Developer Manual 9
Figure 3. LXD9781 MII Demo Board
MII Port 0
J2
MDIO
J1
S1
Intel

LXD9781 PQFP Demo Board
10 Developer Manual
3.0 Quick-Start Checklist
Use this quick-start procedure for easy setup of the LXD9781 demo board. This procedure sets all
ports to the default condition (Auto-Negotiation enabled, advertising dual-speed and full-duplex
capabilities).
1. Set the jumpers in accordance with Table 1.
2. Set switch S1 in accordance with Table 2.
3. Connect the eight demo board MII ports to the SmartBits test box via MII connector/cables.
Male-to- male connectors are required to interface the SmartBits test box to the LXD9781 and
are available from Newark (.5m cable - Newark P/N 91F9746).
4. Connect the twisted-pair ports to external NIC cards via UTP cables. Each NIC card plugs
directly into the SmartBits test box.
5. Connect a +3.3V DC power supply to VCC, VCCD, and VCCIO. Connect all three power
supply return lines to GND.
6. With the demo board appropriately configured, apply power to the LXD9781 and press Reset
switch S3.
7. Proceed with evaluation as desired.
Table 1. Quick-Start Jumper Settings
Jumper / Label Setting Configuration
JP2 / MDIO Jumper
pins 2 - 3 Route MDIO through MII Port 0.
JP3 / MDC Jumper
pins 2 - 3 Route MDC through MII Port 0.
JP29 Jumpered Supply 3.3V to magnetic center-taps.
JP63 / EXT_OSC Open Use on-board oscillator for Quick Status clock.
JP64 / DIV 2 Jumpered Divide quick status clock by 2.
JP65 / Manual Port Speed Open Set Eprom Speed Select to Automatic.
JP39 - JP62 / CFG BITS 1-3 Jumper
pins 1 - 2 Set Port Configuration to Auto-Negotiation, 10/100, Full-Duplex.
JP66 - JP70 / ADD_0-4 Open Set MII base address to 00000.
Table 2. Quick-Start Switch Settings
Switch / Label Setting Configuration
S1-1 / TXSLEW_0 0Set output driver slew rate to 3.7 ns.
S1-2 / TXSLEW_1 1
S1-3 / PAUSE_0 0Disable Pause function.
S1-4 / PWRDWN 0Disable Power-down function.
S1-5 / MDDIS 0Enable MDIO channel.
S1-6 / CIMENA 0Normal Operation.

LXD9781 PQFP Demo Board
Developer Manual 11
4.0 Optional Configurations
4.1 Global Operating Configurations
Switch S1 configures operating characteristics on all ports of the LXD9781. Each switch can be set
manually by toggling the switch either to 1 or 0. Set switch S1 to the desired configuration
according to Table 3.
4.2 LED/CFG Configurations
Three control jumpers for each port pull the associated port configuration pins High or Low to
select the desired mode (auto-negotiation, speed, and duplex). Each port may be configured
independently by setting the three control jumpers shown in Table 4. For Auto-Negotiation, select
the desired advertising configuration from Table 5. For forced operation, set the desired
configuration according to Table 6. Refer to the LXT9781/61 Data Sheet for specific register
definitions and functions.
Table 3. Global Configuration Settings (Switch S1)
Switch / Label Description
TXSLEW_0
TXSLEW_1
TX Output Slew Control. Selects TX output slew rate (rise and fall time).
TXSLEW_1 TXSLEW_0 Slew Rate
0 0 2.5 ns
0 1 3.1 ns
1 0 3.7 ns
1 1 4.3 ns
S1-3 / PAUSE_0 Pause - Enable Pause capability on all ports.
1 = Pause enabled.
0 = Pause disabled.
S1-4 / PWRDWN Power-Down - Enable global power-down Mode.
1 = All ports power-down.
0 = Normal operation.
S1-5 / MDDIS Management Disable - Disables MDIO Access.
1 = MDIO is disabled. (no read or write capability)
0 = MDIO is read/write capable (normal operation).
S1-6 / CIMENA Reserved.
Table 4. LED/CFG_nPort Configuration Jumpers
Port Jumpers
CFG Bit 1 CFG Bit 2 CFG Bit 3
0 JP39 JP41 JP43
1 JP46 JP48 JP50
2 JP40 JP42 JP44

LXD9781 PQFP Demo Board
12 Developer Manual
4.3 MII Address Configurations
The ADDR <4:0> pins are used to configure the MII address by setting the five control jumpers
(JP66, JP67, JP68, JP69 an JP70) as shown in Table 7.
3 JP45JP47JP49
4 JP51JP53JP55
5 JP58JP60JP62
6 JP52JP54JP56
7 JP57JP59JP61
Table 5. Configuration Settings for Auto-Negotiation
Desired Configuration LED/CFG_0
(Bit 1) LED/CFG_1 (Bit 2) LED/CFG_2 (Bit 3)
Auto Negotiation - Advertise 100 HD 1 0 0
Auto Negotiation -Advertise 100 HD/FD 1 0 1
Auto Negotiation -Advertise 10/100 HD 1 1 0
Auto Negotiation -Advertise 10/100 HD/FD 1 1 1
1. To set CFG Bit = 1, jumper pins 1 and 2.
To set CFG Bit = 0, jumper pins 2 and 3.
Table 6. Configuration Settings for Forced Operation
Desired Configuration LED/CFG_0
(Bit 1) LED/CFG_1 (Bit 2) LED/CFG_2 (Bit 3)
Forced 10 Mbps HD 0 0 0
Forced 10 Mbps FD 0 0 1
Forced 100 Mbps HD 0 1 0
Forced 100 Mbps FD 0 1 1
1. To set CFG Bit = 1, jumper pins 1 and 2.
To set CFG Bit = 0, jumper pins 2 and 3.
Table 4. LED/CFG_nPort Configuration Jumpers
Port Jumpers
CFG Bit 1 CFG Bit 2 CFG Bit 3

LXD9781 PQFP Demo Board
Developer Manual 13
4.4 Alternate MDIO Routing Configuration
The MDIO and MDC signals may be routed either through the 40-pin connector for MII Port 0 (the
standard configuration) or through a pair of RJ-11 connectors (J1 and J2), as shown in Table 8. In
either configuration the MII registers can be accessed for each port by setting the correct PHY
address. Refer to the LXT9781 Data Sheet for specific register definitions and functions. The
standard configuration is to route MDIO through the Port 0 MII connector to the SmartBits Test
Box by setting JP2 and JP3 to 2 - 3.
.
4.5 Alternate Power Supply Configuration
The LXT9781 transmitter requires a current source at the center tap of the output transformer. In
the standard configuration (JP29 jumper installed) this source is supplied from the common 3.3V
power supply. However, the LXD9781 supports center-tap voltages down to 2.5V for reduced
power applications. For evaluation in a reduced-power configuration, remove JP29 and apply 2.5V
to post two of the jumper.
Table 7. PHY Address Configuration Settings (Jumpers JP66 - JP70)
Jumper / Label Description
JP66 / ADD_0 Address <4:0> - Sets base address. Each port adds its port number (starting with 0) to this
address to determine its PHY address.
Jumper “open”sets address bit to 0.
Jumper “Installed”sets address bit to 10.
Note: Do not select a base address higher than 24 to make all ports accessible within the 0 - 31
PHY address range.
Port 0 = Base + 0
Port 1 = Base + 1
Port 2 = Base + 2
Port 3 = Base + 3
Port 4 = Base + 4
Port 5 = Base + 5
Port 6 = Base + 6
Port 7 = Base + 7
JP67 / ADD_1
JP68 / ADD_2
JP69 / ADD_3
JP70 / ADD_4
Table 8. MDIO Routing
Jumper Port 0 MDIO Comm
Port Description
JP3 2 - 3 1 - 2 MDC. Management Data Clock. Clock for the MDIO serial channel. Maximum
frequency is 8.0 MHz.
JP2 2 - 3 1 - 2 MDIO. Management Data I/O. Bidirectional serial data channel for PHY/STA
communication.

LXD9781 PQFP Demo Board
14 Developer Manual
4.6 Alternate MII Speed Configuration
In the normal configuration (JP65 open), U41 monitors the Quick Status bit stream to
automatically determine proper MII port speeds. For added flexibility, designers can manually set
the MII port speed via JP65 (jumpered) and Switch (S6) as shown in Table 11.
Note: Do not use this option if the associated network port is set for auto-negotiation.
Table 9. Twisted-Pair Transmit Driver Supply
Jumper Description
JP29 Magnetic Source Voltage. Accesses magnetic transmit pair center-tap voltage source. Jumpered = provides 3.3V to the center-tap of the transmit magnetic.
Open = provides path for reduced power source.
Table 10. MII Port Speed Select
Jumper Description
JP65 Selects automatic or manual MII port speed function. Open = Automatic RMII/MII converter speed select via quick status register (Address 17.15:0).
Jumpered = Manual MII speed select via Switch S6
Table 11. Manual MII Speed Settings (Switch S6)
MII Port # Description
0
Manual MII Speed Select. Manually sets each MII port speed when JP65 = Jumpered.
0 = 10 Mbps
1 = 100 Mbps
Switch S6 controls port speed for the RMII/MII converter FPGAs only. Ensure the MII speed selected by
Switch S6 matches the network port speed selected by the LED/CFG jumpers. MII speed settings must
match the network port speed or the device will be unable to establish a valid link.
1
2
3
4
5
6
7

LXD9781 PQFP Demo Board
Developer Manual 15
5.0 LEDs
5.1 Quick Status LEDs
The QSTAT FPGA (see U41B in Figure 20 on page 35), converts the serial output on the LXT9781
to an LED function. LEDs D126 - D139 provide a continuous, real-time status of several different
attributes and modes via the Quick Status Register and the QSTAT pin.
The Quick Status LEDs reflect the status of a single port. Port selection is set via push-button
switch S7 (Quick status port select). The displayed port is indicated on the 7-segment display,
DP1. The QSTAT clock source is set via jumpers JP63 and JP64 as shown in Table 12.
5.2 Serial LEDs
The LXD9781 provides eight serial LED outputs (LEDS 7:0). There are eight data bits (one per
port) in each serial stream, for a total of 64 LED indicators.
Each serial output reports a specific status condition for all ports. Ports 0 through 7 are assigned
bits 0:7 in each stream. The serial outputs are active Low and report the following conditions for
each port:
Table 12. Quick Status Clock Settings
Jumper Description
JP63 Selects either an external (BNC or BNC1) clock or (Y2) on-board 25 MHz oscillator to retrieve quick status.
Open = Use on-board oscillator for quick status clock.
Jumpered = Supply external quick status clock to BNC1 (25 MHz Max).
JP64 Selects quick status clock division.
Open = Divide quick status clock by 1.
Jumpered = Divide quick status clock by 2.
Table 13. Serial LED Outputs
Serial Output Condition Status
LEDS_7 Speed 0 = 100 Mbps
1 = 10 Mbps
LEDS_6 Transmit 0 = Transmit active
1 = Transmit inactive
LEDS_5 Receive 0 = Receive active
1 = Receive inactive
LEDS_4 Collision 0 = Collision active
1 = Collision inactive
LEDS_3 Link 0 = Link active
1 = Link inactive
1. LEDs are configured active Low.

LXD9781 PQFP Demo Board
16 Developer Manual
5.3 Direct Drive LEDs
The LXD9781 provides three programmable LED drivers per port. Each LED can display one of
several available status conditions as selected by the LED Configuration Register (Address 20)
shown in Table 14.
Programmable LEDs (LED_1, LED_2, LED_3) are set in default mode and are programmable via
the MDIO pin. Register address 20 also provides optional LED pulse stretching up to 100 ms.
Register bits 20.3:2 select one of three possible stretch times.
LEDS_2 Duplex 0 = Full Duplex
1 = Half Duplex
LEDS_1 Polarity (10 Mbps) 0 = Switched Polarity
1 = Normal Polarity
LEDS_0 Activity 0 = Active
1 = Inactive
Table 13. Serial LED Outputs
Serial Output Condition Status
1. LEDs are configured active Low.

LXD9781 PQFP Demo Board
Developer Manual 17
Table 14. Direct Drive LED Configuration Settings (Register 20)
LED Bits Program Bits Description
LED1 LED2 LED3
15:12 11:8 7:4
0000 Indicates 100 Mbps operation. (Default for LED1)
0001 Indicates transmit (stretched).
0010 Indicates receive (stretched). (Default for LED3)
0011 Indicates collision. (stretched)
0100 Indicates active link (continuous). (Default for LED2)
0101 Indicates full-duplex.
0110 Reserved.
0111 Indicates receive or transmit activity.
1000 Test Mode. Turn LED on (continuous).
1001 Test Mode. Turn LED off (continuous).
1010 Test Mode. Blink LED fast (continuous).
1011 Test Mode. Blink LED slow (continuous).
1100 Indicates link and receive status combined.1(Stretched)2
1101 Indicates link and activity status combined.1(Stretched)2
1110 Indicates duplex and collision status combined.3 (Stretched)2
1111 Reserved.
1. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up. The secondary LED driver (receive,
activity, or isolate) causes the LED to change state (blink).
2. Combined event LED settings are not affected by bit 20.1 (Pulse Stretch). These settings are stretched regardless of the
value of 20.1.
3. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full-duplex. Collision status is the
secondary LED driver. The LED changes state (blinks) when a collision occurs.
Table 15. LED Pulse Stretch Settings (Register 20)
Bit Name Description Type Default
20.3:2 LEDFREQ
00 = Stretch LED events to 30 ms.
01 = Stretch LED events to 60 ms.
10 = Stretch LED events to 100 ms.
11 = Reserved
R/W 00
20.1 PULSE-
STRETCH 0 = Disable pulse stretching of all LEDs. 1 = Enable pulse stretching of all LEDs. R/W 1

LXD9781 PQFP Demo Board
18 Developer Manual
6.0 Fiber Setup
6.1 Fiber Modules
The LXT9781 supports eight combination twisted-pair/fiber ports for 100BASE-FX operation.
Two Pseudo-ECL (PECL) interfaces are provided on the LXD9781 MII demo board for connection
to external fiber optic transceiver modules.
To setup the LXD9781 for 100BASE-FX evaluation, five external blue-wire connections and a
fiber-optic transceiver module (HP’s HFBR-5903 or AMP’s 269147-2) are required. Port
connections are shown in Table 16.
•Remove the associated twisted-pair transformer(s) and termination resistors. Once removed,
all associated ports will not operate in TP mode.
•Connect ports 0 - 3 by removing transformer (T2) and termination logic (R272, R277, R280,
R285, R288, R293, R296, R301).
•Connect ports 4 - 7 by removing transformer (T1) and termination logic (R240, R245, R248,
R253, R256, R261, R264, R269). Replace C220 - C235 with 0Ωresistors.
•Two fiber-module headers(JP37 and JP38) areprovided for the blue-wire connection. Connect
ports 0 - 3 to fiber header JP37 and connect ports 4 - 7 to fiber header JP38.
•Solder the fiber modules on the board. Fiber module F1 supports ports 0 - 3. Fiber module F2
supports ports 4 - 7.
•Configure the port MDIO registers for Fiber Mode.
Table 16. MII Port Connections for Fiber Module Operation
Port Header Termination Logic Transformer Fiber
Header Fiber Module
0 JP36 R296, R301, C222, C223
T2 JP37 F1
1 JP35 R288, R298, C220, C221
2 JP34 R280, R285, C226, C227
3 JP33 R272, R277, C224, C225
4 JP32 R264, R269, C230, C231
T1 JP38 F2
5 JP31 R256, R261, C228, C229
6 JP30 R248, R245, C234, C235
7 JP28 R240, R245, C232, C233

LXD9781 PQFP Demo Board
Developer Manual 19
7.0 Board Schematics and Bill of Materials
f
Figure 4. LXT97x1 Power (Board Revision B1)
VCCIO VCCA
GNDAGND
VCC
VCC
GND
GND
VCC
VCC
GND
VCC
GNDA GND
VCCIO
GNDA GND
VCCAVCCD
GNDGNDA GNDGNDA
VCCD
VCC
LEDCLK LEDLAT LEDS0 LEDS1 LEDS2 LEDS3 LEDS5 LEDS6 LEDS7 LEDS4
QCLK
RESET
QSTAT
REF_CLK[4..0]
SPARE_1 SPARE_0
MDIO_1
MDC_1
MDC
REF_CLK[4..0]
MDINT MDIO
REF_CLK4
TDI
MDC
CIMENA MDDIS
TCK
RESET
PWRDWN PAUSE_0
TSLEW_1
TMS TDO
TSLEW_0
TRST
MDIO
JP1
HEADER 4X2
12 34 56 78
R27 4.7k
R30 4.7k
R28 4.7k
R26 4.7k
R29 4.7k
R12 100K
S1 SW DIP-8
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9R10 22K
R2 10k
R5 10k
R6 10k
R4 10k
R3 10k
R7 10k
S3 SW-NO
21
3
TP3
1
D2
1N914 U2B
74HC14
3 4
U2A 74HC14
1 2
R14 100
R13 10K
+
C1
10uF
R11220D1
LED RD
TP1
1
J1
RJ11
1 2 3 4 5 6 J2
RJ11
1 2 3 4 5 6
BN2
RED
1
BN4
BLACK
1
D4
DIODE
+
C7
10uF
+
C8
100uF TANT
+
C9
1.0uF TANT BN3
RED
1
D5
DIODE
+
C10
10uF
+
C11
100uF TANT
+
C12
1.0uF TANT
+
C3
100uF TANT
+
C4
1.0uF TANT
+
C2
10uF
BN1 RED
1
D3
DIODE
+
C5
10uF TANT
FB1
+
C6
.01uF
TP2
1
JP70 JP69 JP68 JP67 JP66
R8 10k
R9 10k
R10 ohm
R220 ohm R210 ohm R200 ohm R190 ohm
R180 ohm R170 ohm R160 ohm R150 ohm
U1I
LXT97x1
1
16
15
31
32
48
49
50
51 52
53 67
68
72
73
74
75
80
81
91
87 88
89
103
106
109
112
113
116
117
120
123 126
127
130
131
134
135
138
144
145
148
149
152
155
158
141
178
179
192
193
208
70 71 76 77
78
79 82 83 84 85 90 92
93 94 95 96 97
102
177 176 175 174 173 172 171 170 163 164 165 166 167
207
86
206
168 169
GNDD
GNDD
VCCIO
VCCIO
GNDD
GNDD
GNDD
GNDD
GNDD VCCIO
GNDD VCCIO
GNDD
GNDD
GNDD
GNDD
GNDD
VCCD
GNDD
GNDD
GNDD VCCD
GNDD
GNDA
VCCR
GNDA
VCCT
VCCR
GNDA
GNDA
VCCR
GNDA VCCT
VCCR
GNDA
GNDA
VCCR
VCCT
GNDA
GNDA
GNDA
VCCR
VCCT
GNDA
VCCR
GNDA
VCCR
GNDD
VCCD
GNDD
VCCIO
VCCIO
MDC MDIO TxSLEW_0 TxSLEW_1
GNDSUB
PAUSE PWRDWN RESET MDINT MDDIS CIMENA REFCLK
ADD_0 ADD_1 ADD_2 ADD_3 ADD_4
RBIAS
LEDS0 LEDS1 LEDS2 LEDS3 LEDS4 LEDS5 LEDS6 LEDS7
TDI
TDO
TMS TCK
TRST
QCLK
GNDD
QSTAT
LEDCLK
LEDLAT
R240 ohm R230 ohm
R250 ohm
R433 4.7k
JP2
HEADER 3_1
1
2 3
JP3
HEADER 3_1
1
2 3
JTAG PORT
VCC
MDINT
OUT
IN
BANANA JACK
+
BANANA JACK
-
3.3 VOLTS
+
BANANA JACK
BANANA JACK
+

LXD9781 PQFP Demo Board
20 Developer Manual
Figure 5. MII Ports 0 and 1
GND
VCC
GND
GND
GND
VCC
GND
GND
MDIO_1
MDC_1
LED/CFG0_3 LED/CFG0_2 LED/CFG0_1 LED/CFG1_3 LED/CFG1_2 LED/CFG1_1 TPFOP0 TPFON0 TPFIP0 TPFIN0 TPFON1 TPFOP1 TPFIP1 TPFIN1 SD0 SD1
CL_0
R3_0 RE_0 R2_0 TC_0 RV_0 RC_0
T0_0 T1_0 T2_0 T3_0 TE_0 TN_0
CL_1
R3_1 RE_1 R2_1 TC_1 RV_1 R1_1 RC_1 R0_1
T2_1 T3_1 T0_1 T1_1 TN_1 TE_1
R1_0 R0_0
CR_0 CR_1
P1 MII 40 PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
R38 50 1% R36 50 1% R44
50 1%
R56 22 R57 22
U6 SN74LVC244A
2 4 6 8 11 13 15 17 1 19
18 16 14 12
9 7 5 3
1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4
1G 2G
1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4
TP5 1
TP7 1
TP10 1
TP11 1
TP4 1
TP14
1
TP16
1TP15
1
TP6 1
R34 50 1% R32 50 1% R33 50 1%
R54 50 1% R55 50 1%
TP17
1
R52 50 1% R51 50 1% R50 50 1% R49 50 1% R53 50 1% R48 50 1%
TP13
1
R46
22
TP19
1
R45
22
TP18
1
TP12
1
R37
22
R43
22
R47
22
R35
22
R66 50 1% R64 50 1% R62 50 1% R70
50 1%
R82 22 R83 22
U8 SN74LVC244A
2 4 6 8 11 13 15 17 1 19
18 16 14 12
9 7 5 3
1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4
1G 2G
1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4
TP21 1
TP23 1
TP24 1
TP25 1
TP26 1
TP27 1
TP20 1
TP30
1
TP32
1TP31
1
TP22 1
R60 50 1% R68 50 1% R58 50 1% U7
SN74LVC244A
2 4 6 8 11 13 15 17 1 19
18 16 14 12
9 7 5 3
1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4
1G 2G
1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4
R59 50 1%
R80 50 1% R81 50 1%
TP33
1
R78 50 1% R77 50 1% R76 50 1% R75 50 1% R79 50 1% R74 50 1%
TP28
1
R71
22
R61
22
TP35
1
R63
22
R65
22
TP29
1
R73
22
R72
22
R69
22
R67
22
TP34
1
R41
22
R39
22
TP8 1
TP9 1
R457 50 1% R458 50 1% R459 50 1% R460 50 1%
R463 50 1% R462 50 1% R461 50 1%
R464 50 1% R465 50 1% R466 50 1% R467 50 1%
R470 50 1% R469 50 1% R468 50 1%
R40 50 1%
U3
SN74LVC244A
2 4 6 8 11 13 15 17 1 19
18 16 14 12
9 7 5 3
1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4
1G 2G
1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4
R42 50 1%
U4A EPF10K10ATC144-1
128 130 131 132 133 135 137 138 140 142 143 144
7 8 9
10
46 48 51 37 39 41 43
RXD0_3 RXD0_2 RXD0_1 RXD0_0 RX_DV0 RX_CLK0 RX_ER0 TX_ER0 TX_CLK0 TX_EN0 TXD0_0 TXD0_1 TXD0_2 TXD0_3 COL0 CRS0
CRS_DV0_RMII
RXD0_RMII_0 RXD0_RMII_1
TXD0_RMII_1 TXD0_RMII_0
TX_RMII_EN0
RX_RMII_ER0
U4B EPF10K10ATC144-1
98 99
100 101 102 109 111 112 114 116 117 118 119 120 121 122
68 70 72 59 62 64 67
RXD1_3 RXD1_2 RXD1_1 RXD1_0 RX_DV1 RX_CLK1 RX_ER1 TX_ER1 TX_CLK1 TX_EN1 TXD1_0 TXD1_1 TXD1_2 TXD1_3 COL1 CRS1
CRS_DV1_RMII
RXD1_RMII_0 RXD1_RMII_1
TXD1_RMII_1 TXD1_RMII_0
TX_RMII_EN1
RX_RMII_ER1
U1A
LXT97x1
61 62 63 64 65 66 69
203 204 205 101 104 105 107 108
RXD0_1 RXD0_0 CRS_DV0 RXER0 TXEN0 TXD0_0 TXD0_1
LED/CFG0_1 LED/CFG0_2 LED/CFG0_3
SD0
TPFIP0
TPFIN0
TPFOP0
TPFON0
U1B
LXT97x1
54 55 56 57 58 59 60
200 201 202 100 115 114 111 110
RXD1_1 RXD1_0 CRS_DV1 RXER1 TXEN1 TXD1_0 TXD1_1
LED/CFG1_1 LED/CFG1_2 LED/CFG1_3
SD1
TPFIP1
TPFIN1
TPFOP1
TPFON1
P2 MII 40 PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40