Inventronik Suska-III-C User manual

Operating Manual for the Suska-III-C Hardware
as Target for the Realization
of Retro-Computers
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Have Fun!
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Jens Carroll
Wolfgang Förster
Inventronik GmbH 2009
Revision History:
Rev. 1.0 07-2009: initial release, subject to change without notice.
Rev. 1.1 12-2009: minor enhancements.
Rev. 1.2 02-2010: IDE cable select infos.
Atari is a registered trademark of Infogames Entertainment
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Amiga is a registered trademark of Amiga Inc.
Table Of Contents
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Index of Tables
Table 1: Address Offsets of the Flash Memory.............................................................................15
Table 2: Assignment of the I2C Interface X2................................................................................41
Table 3: Assignment of the ACSI Interface X4.............................................................................42
Table 4: Assignment of the SCSI Interface X5.............................................................................43
Table 5: Assignment of the VGA connector X8............................................................................44
Table 6: Assignment of the Atari Video Connector X9.................................................................44
Table 7: Assignment of the MIDI Plug X19...................................................................................45
Table 8: Assignment of the MIDI-In Plug X20...............................................................................45
Table 9: Assignment of the MIDI-Out Plug X21............................................................................45
Table 10: Assignment of the ROM Selects Connector X22..........................................................46
Table 11: Assignment of the Atari Keyboard Connector X23........................................................46
Table 12: Assignment of the AUX1 Interface X24.........................................................................46
Table 13: Assignment of the Joyport2 Interface X25....................................................................47
Table 14: Assignment of the Joyport1 Interface X25....................................................................48
Table 15: Assignment of the Extension Connector X27...............................................................50
Table 16: Assignment of the Cartridge Connector X28................................................................52
Table 17: Assignment of the Floppy Connector X29.....................................................................52
Table 18: Assignment of the Printer Port X30...............................................................................53
Table 19: Assignment of the Connector for the serial Interface X31............................................53
Table 20: Assignment of the RTC Alarm Connectors X32...........................................................53
Table 21: Assignment of the AUX2 Interface X33........................................................................54
Table 22: Assignment of the Ethernet Plug X34...........................................................................54
Table 23: Assignment of the AUX3 Interface X36........................................................................55
Table 24: Assignment of the PS/2 Mouse Connector X37...........................................................55
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Table 25: Assignment of the PS/2 Micro Controller Debugging Interface X39............................55
Table 26: Assignment of the PS/2 Keyboard Plug X40................................................................56
Table 27: Assignment of the SDC Micro Controller Debugging Connector X43..........................56
Table 28: Assignment of the LCD Interface X44..........................................................................56
Table 29: Assignment of the AUX-USB Interface X45..................................................................57
Table 30: Assignment of the SYS Micro Controller Debugging Interface X47..............................57
Index of Figures
Figure 1: The heart of the Suska-III-C: Cyclone-II FPGA device..................................................11
Figure 2: Suska-III-C Printed Circuit Board (Prototype with small Differences to the Series)......12
Figure 3: Right Hand Side of Suska-III-C with the DC Plug (left to the center)............................14
Figure 4: Backside of Suska-III-C, the original Monitor Plug is optional.......................................15
Figure 5: Flash Memory with Configuration Switch SW1..............................................................16
Figure 6: Configuration Switch SW2 "SCSI-ID"............................................................................17
Figure 7: Configuration Switch SW3 – (Meets the switch of the Mega STEs).............................18
Figure 8: Selection Switch for general System Settings...............................................................19
Figure 9: Solder Pads SJ1 and SJ2 on the PCB's Solder Side....................................................20
Figure 10: Solder Pads SJ3 to SJ8 on the PCB's Solder Side.....................................................21
Figure 11: Solder Pad SJ9 on the PCB's Top Side.......................................................................22
Figure 12: The System Micro Controller.......................................................................................23
Figure 13: Der PS2 Micro Controller.............................................................................................24
Figure 14: The SD Card Micro Controller......................................................................................26
Figure 15: Pushbuttons of Suska-III-C..........................................................................................29
Figure 16: Front View of Suska-III-C.............................................................................................30
Figure 17: Suska-III-C View from the left......................................................................................31
Figure 18: Suska-III-C View from the right....................................................................................32
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Figure 19: Suska-III-C View to the Back Side...............................................................................33
Figure 20: Connecting a USB Blaster to the Active Serial Interface............................................37
Figure 21: Configuration Interface JTAG (left) and Active Serial Programming Interface............38
Figure 22: Connecting the AVR Programmer to Suska-III-C........................................................39
Figure 23: Suska-III-C Top View PCB Layout...............................................................................56
Figure 24: Suska-III-C Bottom View PCB Layout.........................................................................57
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Introduction:
Suska-III-C is a universal digital electronic device based on a Cyclone-II FPGA (Field Programmable
Gate Array) manufactured by the Altera corporation. The device type is EP2C35F484 (Figure 1). The
FPGA can be understood as a universal configurable digital electronic device and is therefore the heart
of Suska-III-C. The board is reconfigurable hardware that allows, in principle the creation of electronic
devices with very different features. In particular the Suska-III-C board was developed as an Atari
ST/STE compatible computer. All interfaces of the original Atari machines are available on the
Suska-III-C and there are interfaces foreseen to allow the use of modern peripheral devices
such as USB or CF card memory. The following presentation is made with respect to the use of
this hardware as an Atari ST/STE compatible computer.
In it's current version of the Suska-III-C IP core, the operating systems TOS1.00, TOS1.04, TOS1.62,
TOS2.05, TOS2.06 and emuTos are tested and working. TOS1.02 is not working due to the high
processing speed of the IP core. As shown in Figure 2 the complete electronic design consists of the
FPGA device in the middle of the picture, of the SDRAM left to the FPGA, of the operating system Flash
device to the right of the FPGA, some other electronic devices and last but not least a high number of
interface connectors.
The philosophy behind Suska is to realize electronic modules or functions inside the FPGA wherever it is
possible. To do this, the parts of the electronic circuits are described abstractly using an appropriate
standard language. The complete Suska project, means all logic modules is written VHDL (Very High
Speed integrated Circuits Hardware Description Language). These descriptions, roughly speaking are
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Figure 1: The heart of the Suska-III-C: Cyclone-II FPGA device

translated by a compiler to a configuration file which, once downloaded to the FPGA, provides the
functionality. Nearly all parts of the Atari ST or STE computers are provided as open source descriptions;
named IP cores, where IP stands for Intellectual Property. The most recent version are available for
download at www.experiment-s.de.
Functions which could not be realized in the FPGA, like digital analog conversion, the audio codec, the
system memory, analog devices or the power management are equipped as discrete integrated circuits
on the Suska-III-C board.
Suska-III-C also features a very low power consumption and has excellent operation using
rechargeable batteries. All different operation voltages are provided on board from a single
7VDC to 12VDC supply. The three main power supplies are located on the right hand of the
FPGA above the Flash device a shown in Figure 2. The hardware is an 8 layer printed circuit
board with a form factor of 234 * 140 mm². The overall height is given by the original Atari SST
monitor plug and measures 27mm.
Besides the Atari ST/STE computers it is possible to implement other applications like Amiga
relevant computer clones, as an example. The final decision regarding the FPGA and it's
interfaces was made with an eye to creating the most flexible hardware possible. A clear
difference between Suska-III-C and the majority of FPGA development boards available on the
market today.
Equipping Suska-III-C with a slim operating system (MINT) to highlight a trend in the interaction
between hardware and software is under consideration. Thanks to a large variety of interfaces,
the board would then be suitable for a huge number of control applications.
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Figure 2: Suska-III-C Printed Circuit Board (Prototype with small Differences to the Series)

Important Notice
The Suska-III-C hardware is intended for a power supply voltage of 7VDC to 12VDC.
Please use only only power supplies suitable for this application and with the necessary
approvals. Do not exceed the absolute parameters for the operating voltage; please refer to the
'Technical Data'. Please avoid a reverse polarity. For more information on this refer to
paragraph.
On the 8 layer printed circuit boards are devices with small dimensions and filigree structures.
Please take absolute care not to apply mechanical stress to the printed circuit board for example
by bending, torsion or strong forces to any connectors. Not respecting this point can lead to
irreparable contact failures of the FPGA.
Take care when inserting programmer cables to the connectors on the top of the printed circuit
boards. It is recommended to support the respective connectors on the solder side of the PCB
to avoid mechanical stress.
Please be sure to use the printed circuit board (without a case) on an isolated surface and
remove small particles like tin, wires or paper clips which could lead to short circuits.
Concerning this Documentation
The system's properties as described in this documentation depend on the implementation of
the hardware in the FPGA. Because the model of the hardware is open source, the following
description does not claim a fault-free system.
Error corrections and enhancements of the functionality are available through a simple update
of the FPGA configuration. Especially when there is active development with numerous updates
of the FPGA, it is possible that the system is running more or less stable depending on the
success of the compilation and the fitting process. The reason for such instabilities is the timing
behavior of the FPGA implementation itself. The printed circuit board and not responsible for
such effects.
The manufacturer of the Suska-III-C hardware will not give a guarantee for any compilations of
IP cores. Inventronik GmbH seeks to provide stable IP core updates in form of configuration
files.
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Initial Operation of the System
To operate the Suska-III-C hardware, there are some prerequisites necessary as described in
the following paragraphs. The description given is a required minimum.
The Power Supply
Suska-III-C is operated from a power supply of 7VDC bis 12VDC. Use for example a wall cube
adapter with a current of about 1.5A. Connect it to the power supply plug on the right-hand of
the printed circuit board Figure 3. The positive terminal is the center pin of the power supply
connector.
Suska-III-C is protected against reverse polarity. This can lead to a melted fuse F1 (2,5AT) on
the PCB. Replace this if required against an identical type (Shurter OMT 2,5A/125V).
Connection of the minimal required Peripheral Devices
To use the Suska-III-C hardware as Atari STE compatible computer clone it is required to
connect a keyboard, a monitor and, where appropriate, a floppy disk drive.
The choice for the keyboard is either an original Mega STE or Mega ST type or a PS/2 version.
It is not possible to use both keyboards at the same time. The keyboard is connected to it's
respective interface, for the original Atari keyboards this is the Western type connector right to
the power supply and for the keyboard it is the purple PS/2 type connector. Also for the monitors
there are different choices: Either original Atari monitors SM124, SC1225 or others which are
connected to the original 13 position connector in the middle of the back side of the PCB or on
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Figure 3: Right Hand Side of Suska-III-C with the DC Plug (left to the center).

the other hand VGA compatible monitors or TFTs connected to the VGA besides the Atari
monitor connector (see Figure 4).
Please be aware, that the support for the original monitors is given in any case. Due to the very
limited availability of the Atari monitor connectors and the optional mounting of the 13 position
Atari plug it might be necessary to equip the Suska-III-C PCB later with such a device.
Satisfactory use of VGA compatible monitors or TFTs, will depend on the frequencies the
monitor can handle.
The Suska-III-C IP core is already equipped with additional video modes capable of driving
TFTs or CRTs. Further enhancements will be available by configware updates.
The floppy disk drive is connected via a 'high density' D-SUB connector with Suska-III-C. It is
the second connector to the right as shown in Figure 4. The terminal assignment of the
connector cable is given in the appendix of this documentation.
System Configuration
Because the complete Atari compatible IP core is realized in the FPGA, enhancements beyond
the original functionality are easy. To preserve the compatibility and to activate or deactivate
special features, it is possible to configure switches or solder pads on the printed circuit board.
The switches are used for system configurations which may change from time-to-time. The
solder pads are for configuration of features which accompany different versions of micro
controller firmware or FPGA configurations and are changed only once or seldom.
Attention: switch off the Suska-III-C and disconnect it from the power supply to open or close
the solder pads.
Configuration Switch FLASH_OFFSET (SW1)
The Flash device used on the Suska-III-C hardware has 64MBit of free memory, which are
arranged in 4MWords16. While the lower 524288 Words16 are addressable by the FPGA, The
upper address lines A19 to A21 of the Flash device are connected to the configuration switch
(switch position 2 to 4). The switch position 1 of SW1 is not used, see Figure 5, (on the right
hand of the picture, there is located the 'Shurter' fuse F1). In this way, the different switch
positions locate special address ranges as given in the following table.
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Figure 4: Backside of Suska-III-C, the original Monitor Plug is optional.

Switch 2 Switch 3 Switch 4 Adress
Offset
Off Off Off 0x000000
Off Off On 0x080000
Off On Off 0x100000
Off On On 0x180000
On Off Off 0x200000
On Off On 0x280000
On On Off 0x300000
On On On 0x380000
Table 1: Address Offsets of the Flash Memory
A practical application of this feature is the selection of different operating systems which are
located at the respective address boundaries. For more information refer to the paragraphs
Loading the Operating System via the Bootloader Mechanism or Loading the Operating System
via SD Card .
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Figure 5: Flash Memory with Configuration Switch SW1.

Configuration Switch SCSI_ID (SW2)
SW2 has 4 Switches. The SCSI-ID of the SCSI host controller is selectable by the switches 1 to
3. The arrangement is chosen in a way resulting in a binary representation. An example: 1=On,
2=Off, 3=Off refers to the SCSI-ID 4.
Switch number 4 is intended to switch the PS/2 functionality. Refer to the paragraph The PS/2
Micro Controller for more information.
The position of the switch is given in Figure 6.
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Figure 6: Configuration Switch SW2 "SCSI-ID"

Configuration Switch MST_Config (SW3)
The function of SW3 is identical to the 8 position switch which can be found in original Mega STs
and is intended for general system configuration. Because of the high degree of freedom
concerning the development of the Suska-III-C IP core in conjunction with the FPGA and the
resulting numerous 'selection free' improvements over the original machines, currently this
switch is mostly not used. It is intended for future use.
One exception exists for newer TOS versions which use the switch number 7 to indicate
whether DD or HD floppy disk drives are used. If 'on' the operating system handles HD-floppy
disk drives otherwise DD types. One can see this in the dialog box of the formatting routine
which shows the additional entry 'High Density' when HD drives are selected.
The IP core is in this point an improvement over the original hardware. The HD information is
not indicated to the floppy drive but indicated by the floppy drive. So setting switch number 7 is
less important. Formatting floppies can sometimes lead to better results when used in
conjunction with the option 'High Density' for HD type floppies thanks a better selection of
stepping rates for the drives provided by the operating system depending on the setting on
switch 7. HD type floppies which are formatted without the option 'High Density' show 726K of
free disk space. This is a faulty information. HD type floppies always have a capacity of 1,44MB
after formatting. More information concerning the configuration switch SW3 can be found in the
Appendix 3: Mega STE Configuration Switch.
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Figure 7: Configuration Switch SW3 – (Meets the switch of the Mega STEs).

Configuration Switch SYS-Config (SW4)
This switch provides six selection switches which are used by the Suska-III-C IP core as follows
(for more information refer to the IP core source code):
Switch 1:
Selects the system speed. While original STs are driven with a CPU clock of 8MHz, the Suska-
III-C IP core is driven with a CPU clock of 16MHz. This is necessary to provide the correct video
bandwidth for multi-sync monitors. The high frequency leads to incompatibilities with software
which for example implements time delays in NOP loops. Also affected are the old TOS versions
1.00, 1.02 and 1.04. Setting this switch to '1' reduces the CPU speed resulting in better
compatibility (unfortunately not 100%).
Switches 2 and 3:
These two switches are intended to select enhanced video modes. Depending on the connected
monitor type the selection are for example 'legacy mode' for the original Atari monitors (both
switches off), the multi-sync modes and the multi-sync monochrome mode (both switches on).
Play around with the settings to find the best result.
Switch 4:
This switch selects the available memory used by the IP core. 'Off' means 4MB memory like in
STs or STEs and 'On' means 14MB memory used in the Falcon.
Switch 5:
For the compatibility to original ST(E) machines, the setting ACSI interface active must be
selected (switch is off). If the switch is in position 'ON', ACSI is deactivated and the ACSI to
SCSI conversion via the ACSI to SCSI bridge is active. In this case, the SCSI interface is in
operation.
Switch 6:
This switch selects the base address for the operating system. Switched off, the base address
is 0x00FCxxxx and therefore suitable for the operating systems TOS 1.00 bis TOS 1. 04. For
TOS1.62, TOS 2.05, TOS 2.06 and emuTos the base address 0x00E0xxxx must be selected by
switching S6 on.
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Solder Pads SJ1 and SJ2
The MIDI interface is connected to a 6850 compatible ACIA (Asynchronous Communication
Interface Adapter) which is implemented as IP core in the FPGA. It has inputs for the Clear To
Send (CTSn) and the Data Carrier Detect (DCDn) Signals. These are not used in original ST
machines and therefore connected to GND. Opening these solder pads gives the freedom to
introduce enhancements to the IP core or operating systems which use these signals.
The two solder pads are closed by default see Figure 9. The exact location of these solder pads
can be taken from the layout of the solder side of the printed circuit board in the appendix.
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Figure 9: Solder Pads SJ1 and SJ2 on the PCB's Solder
Side.
Figure 8: Selection Switch for general System Settings

Solder Pads SJ3 to SJ8
The color graphic modes of the STEs allow a maximum of 4 bits per color. The Suska-III-C
hardware uses a video AD converter with 8 bits per color. The two least significant bits D1 and
D0 are connected to GND for each color and the respective four most significant bits D7 to D4
are connected to the graphics controller of the Suska-III-C IP core.
The bits D3 and D2 can be connected via the solder pads alternatively. Connected to GND
results in a color resolution like in STE machines with 4 bits resulting in a maximum of 4096
different colors. Connected to XFF827E_D7 to XFF827E_D2, coming from the FPGA, the color
resolution is, in principle, 6 bits resulting in 262144 different colors.
To use this feature, it is necessary that the IP core provide enhanced video mode and the
signals XFF827E_D7 to XFF827E_D2, which refer to the respective ST-Book register are not
available outside the FPGA. See also the wiring if IC39 (system micro controller), X33 (Aux2
connector) and IC37 (SD card micro controller). Figure 10 Shows the location of the solder pads.
The detailed notation can be taken from the layout of the solder side of the printed circuit board
in the appendix.
The solder pads are are all connected in position 1-2 by default.
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Figure 10: Solder Pads SJ3 to SJ8 on the
PCB's Solder Side

Solder Pad SJ9
The SD card micro controller (IC37) is intended primarily for programming the FPGA boot device
or copying an operating system image to the Flash memory. In it's non-configured condition the
FPGA provides no functionality so the SD card micro controller must be driven with the 4MHz
clock on the PS/2 micro controller as this does not rely on the FPGA.
Once the FPGA is correctly configured, the signal SDC_AVR_CLK can be connected to the SD
card micro controller by clocking SJ9. In this way any desired clock frequency can be used for
IC37. The clock functionality for SDC_AVR_CLK must be provided by an appropriate IP core
module.
The FPGA I/O pads are high impedant in the case of a non-configured device, so the SD card
micro controller can be driven with the 4MHz PS/2 micro controller clock, even if SJ9 is closed.
In that case, the clock comes from the SD card micro controller via the resistor R295. If the
clock comes from the FPGA, the driver strength of the respective I/O pads on the FPGA is
sufficient to drive the clock against R295. In the case of a malfunction of SDC_AVR_CLK, it is
not possible to reconfigure the FPGA's boot device from the SD card micro controller because
the clock is missing. A workaround is to open SJ9 or to configure the FPGA via the Active Serial
Interface using a programmer.
The solder pad SJ9 is open by default.
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Figure 11: Solder Pad SJ9 on the PCB's Top Side.