IRF IRAUDAMP5 User manual

www.irf.com
IRAUDAMP5 REV 3.1
IRAUDAMP5
120W x 2 Channel Class D Audio Power Amplifier
Using the IRS2092S and IRF6645
By
Jun Honda, Manuel Rodríguez and Jorge Cerezo
Fig 1
CAUTION: International Rectifier suggests the following guidelines for
safe operation and handling of IRAUDAMP5 Demo Board;
•Always wear safety glasses whenever operating Demo Board
•Avoid personal contact with exposed metal surfaces when operating
Demo Board
•Turn off Demo Board when placing or removing measurement probes

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IRAUDAMP5 REV 3.1
Table of Contents
Page
Introduction………………………………………………………………….. 2
Specifications………………………………………………………………… 3
Connection Setup……………………………………………………….…… 4
Test Procedure………………………………………………………………... 5
Typical Performance…………………………………………………………. 5-9
Theory of Operation…………………………………………………………. 9-10
IRS2092S System Overview………………………………………………… 10-11
Selectable Dead Time………………………………………………………… 11-12
Protection Features…………………………………………………………… 12-17
Efficiency…………………………………………………………………….. 17-18
Thermal Considerations……………………………………………………… 18
Click and Pop Noise Control…………………………………………………. 18-19
Startup and Shutdown Sequencing…………………………………………… 19-21
PSRR…………………………………………………………………………. 21-22
Bus Pumping………………………………………………………………….. 22-23
Input/Output Signal and Volume Control……………………………………. 23-26
Self Oscillating PWM Modulator…………………………………………….. 27
Switches and Indicators………………………………………………………. 28
Frequency Lock, Synchronization Feature…………………………………… 29
Schematics……………………………………………………………………. 32-36
Bill of Materials……………………………………………………………… 37-40
Hardware……………………………………………………………………… 41
PCB specifications……………………………………………………………. 42
Assembly Drawings…………………………………………………………... 43-49
Revision changes descriptions 50
END…………………………………………………………………………... 50

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IRAUDAMP5 REV 3.1
Introduction
The IRAUDAMP5 reference design is a two-channel, 120W half-bridge Class D audio power
amplifier. This reference design demonstrates how to use the IRS2092S Class D audio controller
and gate driver IC, implement protection circuits, and design an optimum PCB layout using the
IRF6645 DirectFET MOSFETs. The resulting design requires no heatsink for normal operation
(one-eighth of continuous rated power). The reference design provides all the required
housekeeping power supplies for ease of use. The two-channel design is scalable for power and
the number of channels.
Applications
AV receivers
Home theater systems
Mini component stereos
Powered speakers
Sub-woofers
Musical Instrument amplifiers
Automotive after market amplifiers
Features
Output Power: 120W x 2 channels,
Total Harmonic Distortion (THD+N) = 1%, 1 kHz
Residual Noise: 170μV, IHF-A weighted, AES-17 filter
Distortion: 0.005% THD+N @ 60W, 4Ω
Efficiency: 96% @ 120W, 4Ω, single-channel driven, Class D stage
Multiple Protection Features: Over-current protection (OCP), high side and low side
Over-voltage protection (OVP),
Under-voltage protection (UVP), high side and low side
DC-protection (DCP),
Over-temperature protection (OTP)
PWM Modulator: Self-oscillating half-bridge topology with optional clock
synchronization

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IRAUDAMP5 REV 3.1
Specifications
General Test Conditions (unless otherwise noted) Notes / Conditions
Supply Voltage ±35V
Load Impedance 8-4Ω
Self-Oscillating Frequency 400kHz No input signal, Adjustable
Gain Setting 26dB 1Vrms input yields rated power
Electrical Data Typical Notes / Conditions
IR Devices Used IRS2092S Audio Controller and Gate-Driver,
IRF6645 DirectFET MOSFETs
Modulator Self-oscillating, second order sigma-delta modulation, analog input
Power Supply Range ± 25V to ±35V Bipolar power supply
Output Power CH1-2: (1% THD+N) 120W 1kHz
Output Power CH1-2: (10% THD+N) 170W 1kHz
Rated Load Impedance 8-4ΩResistive load
Standby Supply Current ±100mA No input signal
Total Idle Power Consumption 7W No input signal
Channel Efficiency 96% Single-channel driven,
120W, Class D stage
.
Audio Performance *Before
Demodulator
Class D
Output Notes / Conditions
THD+N, 1W
THD+N, 10W
THD+N, 60W
THD+N, 100W
0.009%
0.003%
0.003%
0.008%
0.01%
0.004%
0.005%
0.010%
1kHz, Single-channel driven
Dynamic Range 101dB 101dB A-weighted, AES-17 filter,
Single-channel operation
Residual Noise, 22Hz - 20kHzAES17 170μV
170μV
Self-oscillating – 400kHz
Damping Factor 2000 170 1kHz, relative to 4Ωload
Channel Separation 95dB
85dB
75dB
90dB
80dB
65dB
100Hz
1kHz
10kHz
Frequency Response : 20Hz-20kHz
: 20Hz-35kHz
N/A ±1dB
±3dB 1W, 4Ω- 8ΩLoad
Thermal Performance Typical Notes / Conditions
Idling TC =30°C
TPCB=37°C
No signal input, TA=25°C
2ch x 15W (1/8 rated power) TC =54°C
TPCB=67°C
Continuous, TA=25°C
2ch x 120W (Rated power) TC =80°C
TPCB=106°C
At OTP shutdown @ 150 sec,
TA=25°C
Physical Specifications
Dimensions 5.8”(L) x 5.2”(W)

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IRAUDAMP5 REV 3.1
Note: Class D Specifications are typical
*Before demodulator refers to audio performance measurements of the Class D output power
stage only, with preamp and output filter bypassed this means performance measured before the
low pass filter.
Connection Setup
Typical Test Setup
Fig 2
Connector Description
CH1 IN J6 Analog input for CH1
CH2 IN J5 Analog input for CH2
POWER J7 Positive and negative supply (+B / -B)
CH1 OUT J3 Output for CH1
CH2 OUT J4 Output for CH2
EXT CLK J8 External clock sync
DCP OUT J9 DC protection relay output
Volume
J6 J5
J3 J4
J7
R113
S3 S2
TP1 TP2
CH1
Output CH2 Output
CH1
Input CH2
Input
G
Protection
Normal
S1
LED
35V, 5A DC supply
4 Ohm4 Ohm
35V, 5A DC supply
250W, Non-inductive Resistors
J8
J9
Audio Signal Generator

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IRAUDAMP5 REV 3.1
Test Procedures
1. Connect 4Ω, 250W load to outputs connectors, J3 and J4 and Audio Precision analyzer
(AP).
2. Connect Audio Signal Generator to J6 and J5 for CH1 and CH2 respectively (AP).
3. Connect a dual power supply to J7, pre-adjusted to ±35V, as shown in Figure 2 above.
4. Set switch S3 to middle position (self oscillating).
5. Set volume level knob R108 fully counter-clockwise (minimum volume).
6. Turn on the power supply. Note: always apply or remove the ±35V at the same time.
7. Orange LED (Protection) should turn on almost immediately and turn off after about 3s.
8. Green LED (Normal) then turns on after orange LED is extinguished and should stay on.
9. One second after the green LED turns on; the two blue LEDS on the Daughter Board
should turn on and stay on for each channel, indicating that a PWM signal is present at
LO
10. With an Oscilloscope, monitor switching waveform at test points TP1 and TP2 of CH1
and CH2 on Daughter Board.
11. If necessary, adjust the self-oscillating switching frequency of AUDAMP5 to 400KHz
±5kHz using potentiometer R29P. For IRAUDAMP5, the self-oscillating switching
frequency is pre-calibrated to 400 KHz. To modify the AUDAMP5 frequency, change the
values of potentiometers R21 and R22 for CH1 and CH2 respectively.
12. Quiescent current for the positive supply should be 70mA ±10mA at +35V.
13. Quiescent current for the negative supply should be 100mA ±10mA at –35V.
14. Push S1 switch, (Trip and Reset push-button) to restart the sequence of LEDs indicators,
which should be the same as noted above in steps 6-9.
Audio Tests:
15. Apply 1 V RMS at 1KHz from the Audio Signal Generator
16. Turn control volume up (R108 clock-wise) to obtain an output reading of 100Watts for
all subsequent tests as shown on the Audio Precision graphs below, where measurements
are across J3 and J2 with an AES-17 Filter
Typical Performance
The tests below were performed under the following conditions:
±B supply = ±35V, load impedance = 4Ωresistive load, 1kHz audio signal,
Self oscillator @ 400kHz and internal volume-control set to give required output with 1Vrms
input signal, with AES-17 Filter, unless otherwise noted.

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IRAUDAMP5 REV 3.1
THD versus Power:
0.001
10
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
%
100m 200200m 500m 1 2 5 10 20 50 100
W
Blue, CH1 - 4 Ohm
Red, CH2 - 4 Ohm
Figure 18. Total Harmonics Distortion + Noise (THD+N) versus power output
Fig 3
-10
+4
-9
-8
-7
-6
-5
-4
-3
-2
-1
-0
+1
+2
+3
d
B
r
A
20 50 100 200 500 1k 2k 5k 10k 20k 50k
Hz 200k100k
Frequency Response:
Red CH1 - 4 Ohm, 2V Output
Blue CH1 - 8 Ohm, 2V Output
Frequency Characteristics vs. Load Impedance
Fig 4

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IRAUDAMP5 REV 3.1
.
THD versus Frequency:
0.0001
100
0.0005
0.001
0.01
0.05
0.1
1
5
10
50
%
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Pink CH1, 1W Output
Blue CH1, 10W Output
Cyan CH1, 50W Output
Green CH1, 100W Output
THD+N Ratio vs. Frequency
Fig 5
.
Frequency Spectrum :
-110
+0
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
V
10 20k20 50 100 200 500 1k 2k 5k 10k
Hz
Red CH1, 1V, 1kHz, Self Oscillator @ 400kHz
Blue CH2, 1V, 1kHz, Self Oscillator @ 400kHz
Fig 6 Frequency Spectrum

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IRAUDAMP5 REV 3.1
.
Floor Noise:
-140
+20
-120
-100
-80
-60
-40
-20
+0
d
B
V
10 20k20 50 100 200 500 1k 2k 5k 10k
Hz
Red CH1 - ACD, No signal, Self Oscillator @ 400kHz
Blue CH2 - ACD, No signal, Self Oscillator @ 400kHz
Fig 7 Residual Noise (ACD)
.
Channel Separation:
-120
+0
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Red CH1 – CH2, 60W
Blue CH2 – CH1, 60W
Fig 8 Channel Separation vs. Frequency

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IRAUDAMP5 REV 3.1
.
Clipping Characteristics:
60W / 4 Ω , 1kHz, THD+N=0.008% 174W / 4 Ω , 1kHz, THD+N=10%
Measured Output and Distortion Waveforms
Fig 9
.
IRAUDAMP5 Theory of Operation
Referring to Fig 10 below, the input error amplifier of the IRS2092S forms a front-end second-
order integrator with C1, C21, C23 and R21. This integrator also receives a rectangular feedback
waveform from R31, R33 and C17 into the summing node at IN- from the Class D power stage
switching node (connection of DirectFET Q3 and DirectFET Q4). The quadratic oscillatory
waveform of the switch node serves as a powered carrier signal from which the audio is
recovered at the speaker load through a single-stage LC filter. The modulated signal is created by
the fluctuations of the analog input signal at R13 that shifts the average value of this quadratic
waveform through the gain relationship between R13 and R31 + R33 so that the duty cycle varies
according to the instantaneous signal level of the analog input signal at R13.
R33 and C17 act to immunize the rectangular waveform from possible narrow noise spikes that
may be created by parasitic impedances on the power output stage. The IRS2092S input
integrator then processes the signal from the summing node to create the required triangle wave
amplitude at the COMP output. The triangle wave then is converted to Pulse Width Modulation,
or PWM, signals that are internally level-shifted Down and Up to the negative and positive
supply rails. The level shifted PWM signals are called LO for low output, and HO for high
output, and have opposite polarity. A programmable amount of dead time is added between the
gate signals to avoid cross conduction between the power MOSFETs. The IRS2092S drives two
IRF6645 DirectFET MOSFETs in the power stage to provide the amplified PWM waveform. The
amplified analog output is reconstructed by demodulating the powered PWM at the switch node,
called VS. (Show as VS on the schematic)This is done by means of the LC low-pass filter (LPF)
formed by L1 and C23A, which filters out the Class D switching carrier signal, leaving the audio
powered output at the speaker load. A single stage output filter can be used with switching
Red Trace: Total Distortion + Noise Voltage
Green Trace: Output Voltage

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IRAUDAMP5 REV 3.1
frequencies of 400 kHz and greater; lower switching frequencies may require additional filter
components.
+VCC is referenced to –B and provides the supply voltage to the LO gate driver. D6 and C5 form
a bootstrap supply that provides a floating voltage to the HO gate driver. The VAA and VSS
input supplies are derived from +B and -B via R52 and C18, and R50 and C12, respectively.
Thus, a fully functional Class D PWM amplifier plus driver circuit is realized in an SO16
package with just a few small components.
+
-
.
.
.
R13
IN-
COMP
C23
.
R33
-VSS
+VAA
IRS2092S
LO
VS
VCC
C5
D6
VB 0V
0V
C1
R21
C17
R52
C3
HO
C23A
INPUT
C21
R31
C12
R50
+VCC
Integrator
COM
R30
Modulator
and
Shift level
GND
0V
-B
DirectFet
0VLP Filter
L1
DirectFet
C18
R32
+B
IRF6645
Q4
IRF6645
Q3
Simplified Block Diagram of IRAUDAMP5 Class D Amplifier
Fig 10
System overview
IRS2092S Gate Driver IC
The IRAUDAMP5 uses the IRS2092S, a high-voltage (up to 200V), high-speed power MOSFET
PWM generator and gate driver with internal dead-time and protection functions specifically
designed for Class D audio amplifier applications. These functions include OCP and UVP. Bi-
directional current protection for both the high-side and low-side MOSFETs are internal to the
IRS2092S, and the trip levels for both MOSFETs can be set independently. In this design, the
dead time can be selected for optimized performance by minimizing dead time while preventing
shoot-through. As a result, there is no gate-timing adjustment on the board. Selectable dead time
through the DT pin voltage is an easy and reliable function which requires only two external
resistors, R11 and R9 as shown on Fig11 below.

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IRAUDAMP5 REV 3.1
.
.
CH1
Feedback
R19
.
R18 R13
.
AUDIO_INPUT
+VCC
-B
+B
R5
VS
HO
VB
CSH
DT
COM
LO
VCC
IN-
COMP
VAA
GND
CSD
VREF
VSS
CSLO
IRS2092S
System-level View of Class D Controller and Gate Driver IRS2092S
Fig 11
Selectable Dead-Time
The dead time of the IRS2092S is based on the voltage applied to the DT pin. (Fig 12) An
internal comparator determines the programmed dead time by comparing the voltage at the DT
pin with internal reference voltages. An internal resistive voltage divider based on different ratios
of VCC negates the need for a precise reference voltage and sets threshold voltages for each of
the four programmable settings. Shown in the table below are component values for
programmable dead times between 15 and 45 ns. To avoid drift from the input bias current of the
DT pin, a bias current of greater than 0.5mA is suggested for the external resistor divider circuit.
Resistors with up to 5% tolerance can be used.
Selectable Dead-Time
Dead-time mode Dead time R5 R13 DT voltage
DT1 ~15ns 3.3k 8.2k 0.71 x Vcc Default
DT2 ~25ns 5.6k 4.7k 0.46 x Vcc
DT3 ~35ns 8.2k 3.3k 0.29 x Vcc
DT4 ~45ns open <10k 0 x Vcc
Vcc0.89xVcc0.57xVcc0.36xVcc0.23xVcc
Shutdown
45nS
35nS
25nS
15nS
Operational Mode
Dead-time
VDT
Fig 12 Dead-time Settings vs. VDT Voltage
Default

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IRAUDAMP5 REV 3.1
Over-Current Protection (OCP)
In the IRAUDAMP5, the IRS2092S gate driver accomplishes OCP internally, a feature discussed
in greater detail in the “Protection” section.
Offset Null (DC Offset)
The IRAUDAMP5 is designed such that no output-offset nullification is required, thanks to
closed loop operation. DC offsets are tested to be less than ±20mV.
Protection
The IRAUDAMP5 has a number of protection circuits to safeguard the system and speaker as
shown in the figure 13 below, which fall into one of two categories – internal faults and external
faults, distinguished by the manner in which a fault condition is treated. Internal faults are only
relevant to the particular channel, while external faults affect the whole board. For internal faults,
only the offending channel is stopped. The channel will hiccup until the fault is cleared. For
external faults, the whole board is stopped using the shutdown sequencing described earlier. In
this case, the system will also hiccup until the fault is cleared, at which time it will restart
according to the startup sequencing described earlier.
. .
D4
OCREF
OCREF
5.1V
CSD
Trip
RESET
OCSET
+
.
UVP
LO
VS
VCC
VB
CSH
R41
OVP
OTP
R25
D1
BAV19
DCP
LP Filter
Green
Yellow
LEDs
R18
HO
To next channel
OCSET COM
10R
R30
CSD
R43
1.2V
+B
R19
10R
R32
-B
IRF6645
Q4
IRF6645
Q3
Functional Block Diagram of Protection Circuit Implementation
Fig 13

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IRAUDAMP5 REV 3.1
Internal Faults
OCP and OTP are considered internal faults, which will only shutdown the particular channel by
pulling low the relevant CSD pin. The channel will shutdown for about one-half a second and
will hiccup until the fault is cleared.
Over-Temperature Protection (OTP, Fig 14)
A separate PTC resistor is placed in close proximity to the high-side IRF6645 DirectFET
MOSFET for each of the amplifier channels. If the resistor temperature rises above 100°C, the
OTP is activated. The OTP protection will only shutdown the relevant channel by pulling the
CSD pin low and will recover once the temperature at the PTC has dropped sufficiently. This
temperature protection limit yields a PCB temperature at the MOSFET of about 100°C, which is
limited by the PCB material and not by the operating range of the MOSFET.
R31
100K
Rp1
100C
-B
C28
47nF
R48
1K
R47
100K
Q7
OTP CH1
-B
OTP1
Rp1 is thermally connected with Q3
32
1
2 3
Q3
IRF6645
Fig 14
Over-Current Protection (OCP)
The OCP internal to the IRS2092S shuts down the IC if an OCP is sensed in either of the output
MOSFETs. For a complete description of the OCP circuitry, please refer to the IRS2092S
datasheet. Here is a brief description:
Low-Side Current Sensing
Fig 15 shows the low side MOSFET as is protected from an overload condition by measuring the
low side MOSFET drain-to-source voltage during the low side MOSFET on state, and will shut
down the switching operation if the load current exceeds a preset trip level. The voltage setting on
the OCSET pin programs the threshold for low-side over-current sensing. Thus, if the VS voltage
during low-side conduction is higher than the OCSET voltage, the IRS2092S will trip and CSD
goes down. It is recommended to use VREF to supply a reference voltage to a resistive divider
(R19 and R18 for CH1) to generate a voltage to OCSET; this gives better variability against VCC
fluctuations. For IRAUDAMP5, the low-side over-current trip level is set to 0.65V. For IRF6645
DirectFET MOSFETs with a nominal RDS-ON of 28mOhms at 25°C, this results in a ~23A
maximum trip level. Since the RDS-ON is a function of temperature, the trip level is reduced to
~15A at 100°C.

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IRAUDAMP5 REV 3.1
.
OCREF
OCREF
5.1V
CSD
OCSET
+
.
LO
VS
VCC
VB
CSH
R41 R25
D1
BAV19
LP Filter
R18
HO
OCSET COM
10R
R30
CSD
R43
1.2V
+B
R19
10R
R32
-B
IRF6645
Q4
IRF6645
Q3
Simplified Functional Block Diagram of High-Side and Low-Side Current Sensing (CH1)
Fig 15
High-Side Current Sensing (Fig15)
The high-side MOSFET is protected from an overload condition and will shutdown the switching
operation if the load current exceeds a preset trip level. High-side over-current sensing monitors
detect an overload condition by measuring the high side MOSFET’s drain-to-source voltage
(VDS) through the CSH and VS pins. The CSH pin detects the drain voltage with reference to the
VS pin, which is the source of the high-side MOSFET. In contrast to the low-side current sensing,
the threshold of CSH pin to engage OC protection is internally fixed at 1.2V. An external
resistive divider R43+R25 and R41 (for Ch1) can be used to program a higher threshold. An
additional external reverse blocking diode (D1 for CH1) is required to block high voltage feeding
into the CSH pin during low-side conduction. By subtracting a forward voltage drop of 0.6V at
D1, the minimum threshold which can be set for the high-side is 0.6V across the drain-to-source.
For IRAUDAMP5, the high-side over-current trip level is set to 0.6V across the high-side
MOSFET. For the IRF6645 MOSFETs with a nominal RDS-ON of 28 mOhms at 25°C, this results
in a ~21A maximum trip level. Since the RDS-ON is a function of temperature, the trip level is
reduced to ~14A at 100°C.
For a complete description of calculating and designing the over-current trip limits, please refer to
the IRS2092S datasheet.
Positive and Negative Side of Short Circuit, versus switching output shut down:
The plots below show the speed that the IRS2092S responds to a short circuit condition. Notice
that the envelope behind the sine wave output is actually the switching frequency ripple. Bus
pumping naturally affects this topology.

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IRAUDAMP5 REV 3.1
Positive and Negative side of Short Circuit, versus switching output shut down:
OCP Waveforms Showing Load Current and Switch Node Voltage (VS)
Fig 16
.
Short Circuit Response:
OCP Waveforms Showing CSD Trip and Hiccup
Fig 17
External Faults
OVP, UVP and DCP are considered external faults. In the event that any external fault condition
is detected, the shutdown circuit will disable the output for about three seconds, during which
time the orange AUDAMP5 “Protection” LED will turn on. If the fault condition has not cleared,
the protection circuit will hiccup until the fault is removed. Once the fault is cleared, the green
“Normal” LED will turn on. There is no manual reset option.
Over-Voltage Protection (OVP Fig 18)
OVP will shut down the amplifier if the bus voltage between GND and -B exceeds 40V. The
threshold is determined by the voltage sum of the Zener diode Z105, R140, and VBE of Q109. As
a result, it protects the board from hazardous bus pumping at very low audio signal frequencies
by shutting down the amplifier. OVP will automatically reset after three seconds. Since the +B
and –B supplies are assumed to be symmetrical (bus pumping, although asymmetrical in time,
Load current
CSD
p
in
VS
p
in
Load current
CSD
p
in
VS
p
in
Load current
CSD
p
in
Load current
VS
p
in
CSD
p
in
VS
p
in
Load current
CSD
p
in
Load current
VS
p
in
CSD
p
in
VS
p
in
Load current
VS
p
in
Load current
VS
p
in

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IRAUDAMP5 REV 3.1
will pump the bus symmetrically in voltage level over a complete audio frequency cycle), it is
sufficient to sense only one of the two supply voltages for OVP. It is therefore up to the user to
ensure that the power supplies are symmetrical.
Q109 Over-Voltage Protection (OVP)
R141
47k
S1
SW-PB
Q109
MMBT5551
R139
47k
-B
SD
D105
1N4148
Z107
18V
R145
47K
R146
47K
Q110
MMBT5551
R144
10k
Trip and restart
R140
10k
Z105
39V
OVP
DCP
R149
47K
C119
0.1uF, 50V
UVP
OT
OT
Q110 Under-Voltage Protection (UVP)
Fig 18
Under-Voltage Protection (UVP, Fig18)
UVP will shutdown the amplifier if the bus voltage between GND and -B falls below 20V. The
threshold is determined by the voltage sum of the Zener diode Z107, R145 and VBE of Q110. As
with OVP, UVP will automatically reset after three seconds, and only one of the two supply
voltages needs to be monitored.
Speaker DC-Voltage Protection (DCP, Fig 19)
DCP is provided to protect against DC current flowing into the speakers. This abnormal condition
is rare and is likely caused when the power amplifier fails and one of the high-side or low-side
IRF6645 DirectFET MOSFETs remain in the ON state. DCP is activated if either of the outputs
has more than ±4V DC offset (typical). Under this fault condition, it is normally required to
shutdown the feeding power supplies. Since these are external to the reference design board, an
isolated relay P1 is provided for further systematic evaluation of DC-voltage protection. This
condition is transmitted to the power supply controller through connector J9, whose pins are
shorted during a fault condition.

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IRAUDAMP5 REV 3.1
R124
10k
R121
47k
R122
47k
CH1 O
CH2 O
Q106
MMBT5401
Q104
MMBT5401
C116
100uF, 16V R123
1K
Q105 MMBT5551
R125
10K
R126
100K
+B
R129
6.8k
DC protection
DCP
R127
6.8k
R128
6.8k
R130
47K
R131
47K
From CH1 Output
From CH2 Output
-B
To DCP
Fig 19
Efficiency
Figs 20 demonstrate that IRAUDAM5 is highly efficient, due to two main factors:
a.) DirectFETs offer low RDS(ON) and very low input capacitance, and b). The PWM operates as
Pulse Density Modulation.
0.0%
10.0%
20.0%
30.0%
40.0%
50.0%
60.0%
70.0%
80.0%
90.0%
100.0%
0 20 40 60 80 100 120 140 160 180
Output Power (W)
Power Stage Efficiency (%)
Efficiency vs. Output Power, 4 Ω Single Channel Driven, ±B supply = ±35V, 1kHz Audio Signal
Fig20

www.irf.com Page 18 of 50
IRAUDAMP5 REV 3.1
Thermal Considerations
The daughter-board design can handle one-eighth of the continuous rated power, which is
generally considered to be a normal operating condition for safety standards. Without the addition
of a heatsink or forced air-cooling, the daughter board cannot handle fully rated continuous
power. A thermal image of the daughter board is as shown in Fig 21 below.
Thermal Distribution
Thermal image of Daughter-Voard
Two-Channel x 1/8th Rated Power (15W) in Operation, TC = 54°C at Steady State
±B supply = ±35V, 4 Ω Load, 1kHz audio signal, Temp ambient = 25°C
Fig 21
Click and POP noise:
One of the most important aspects of any audio amplifier is the startup and shutdown procedures.
Typically, transients occurring during these intervals can result in audible pop- or click-noise
from the output speaker. Traditionally, these transients have been kept away from the speaker
through the use of a series relay that connects the speaker to the audio amplifier only after the
startup transients have passed and disconnects the speaker prior to shutting down the amplifier.
Thanks to the click and pop elimination function in the IRS2092S, IRAUDAMP5 does not use
any series relay to disconnect the speaker from the audible transient noise.
54°C
67°C
54°C
67°C

www.irf.com Page 19 of 50
IRAUDAMP5 REV 3.1
Click-Noise Reduction Circuit (Solid-State Shunt)
IRS2092S controller is relatively quiet with respect to class AB, but for additional click or POP
noise reduction you may add a shunt circuit that further attenuates click or pop transients during
turn on sequencing. The circuit is not populated on the present demo board; for implementation
details, please refer to the IRAUDAMP4 user’s manual at http://www.irf.com/technical-
info/refdesigns/audiokits.html
Startup and Shutdown Sequencing (Fig 22)
The IRAUDAMP5 sequencing is achieved through the charging and discharging of the CStart
capacitor C117. Along with the charging and discharging of the CSD voltage (C10 on daughter
board for CH1) of the IRS2092S, this is all that is required for complete sequencing. The startup
and shutdown timing diagrams are show in Figure 22A below:
Click Noise Reduction Sequencing at Trip and Reset
Fig 22A
For startup sequencing, the control power supplies start up at different intervals depending on the
±B supplies. As the +/-B supplies reach +5 volts and -5 volts respectively, the +/-5V control
supplies for the analog input start charging. Once +B reaches ~16V, VCC charges. Once –B
reaches -20V, the UVP is released and CSD and CStart (C117) start charging. The Class D
amplifier is now operational, but the preamp output remains muted until CStart reaches Ref2. At
this point, normal operation begins. The entire process takes less than three seconds.
CStart
CSD
External trip
CSD= 2/3VDD
CStart Ref1
CStart Ref2
SP MUTE
CHx_O
A
udio MUTE
Class D shutdown
Time
Music shutdown Class D startup Music startup
CStart Ref1 CStart Ref2
Reset
CStart Ref1
CStart Ref2