JYTEK PXIe-2722 User manual

PXIe-2722 Chassis
User Manual
User Manual Version: V1.0.2
Revision Date: Nov 8 2021

Table of Contents
1. Introduction............................................................................................................... 1
Overview...........................................................................................................1
Main Features...................................................................................................1
2. Hardware....................................................................................................................2
Backplane Overview......................................................................................... 2
2.1.1 PXIe-2722G3 Backplane Architecture................................................... 2
2.1.2 PXIe-2722G2 Backplane Architecture................................................... 3
2.1.3 System Controller Slot...........................................................................4
2.1.4 Peripheral Slot....................................................................................... 4
2.1.5 PXI Trigger Bus.......................................................................................5
2.1.6 PXI Local Bus..........................................................................................6
2.1.7 System Reference Clock and Synchronization Signal............................6
Specifications....................................................................................................8
2.2.1 Basic.......................................................................................................8
2.2.2 Electrical................................................................................................ 9
2.2.3 System Synchronization Clock.............................................................10
2.2.4 Physical and Enviornment................................................................... 11
Mechanical Dimensions..................................................................................12
Front and Rear Panels.................................................................................... 16
2.4.1 Front Panel.......................................................................................... 16
2.4.2 Rear Panel............................................................................................17
2.4.3 Inhibit/Voltage Monitoring DB-9 Connector.......................................18
2.4.4 Inhibit Switch.......................................................................................18
2.4.5 FAN Switch...........................................................................................19
2.4.6 Chassis Status LED............................................................................... 19
2.4.7 Fan Mode.............................................................................................19
Chassis Cooling Considerations...................................................................... 22
2.5.1 PXI/PXIe Modules Cooling................................................................... 22
2.5.2 Power Supply Cooling..........................................................................23
3. Performance.............................................................................................................24
PCI Bus Throughput........................................................................................ 24
PCIe Bus Throughput...................................................................................... 28
3.2.1 PXIe-2722G3 PCIe Bus Throughput..................................................... 28
3.2.2 PXIe-2722G2 PCIe Bus Throughput..................................................... 31
Compatibility test........................................................................................... 34
4. Software...................................................................................................................37
Introduction to JYDM..................................................................................... 37
Installation and use of JYDM.......................................................................... 37
Chassis environment monitoring in JYDM..................................................... 39
Chassis cooling control in JYDM..................................................................... 40

Reference Clock Status Display in JYDM........................................................ 42
Trigger Bus Routing Control in JYDM............................................................. 43
Chassis identification in NI MAX.....................................................................45
5. Using PXIe-2722 Chassis.......................................................................................... 47
Using PXIe-2722 with JYTEK PXI/PXIe Peripheral Modules............................47
Using PXIe-2722 with National Instruments PXI/PXIe Peripheral Modules...47
5.2.1 Use National Instruments PXI/PXIe Peripheral Modules without
synchronization:........................................................................................... 47
5.2.2 Use National Instruments PXI/PXIe Peripheral Modules with
synchronization:........................................................................................... 47
6. Optional Equipment................................................................................................ 49
Rack Mount Kits..............................................................................................49
7. About JYTEK............................................................................................................. 50
JYTEK China.....................................................................................................50
JYTEK Korea and JYTEK In Other Countries.................................................... 50
JYTEK Hardware Products...............................................................................50
JYTEK Software Platform................................................................................ 51
JYTEK Warranty and Support Services........................................................... 51
8. Statement.................................................................................................................52
Figure 1 PXIe-2722 Gen3 Backplane Architecture................................................. 2
Figure 2 PXIe-2722 Gen2 Backplane Architecture................................................. 3
Figure 3 PXIe-2722 Peripheral Slot Compatible Modules......................................4
Figure 4 PXI Trigger Bus Connectivity Diagram......................................................5
Figure 5 Trigger Bus Buffer Routing....................................................................... 6
Figure 6 System Reference Clock Default Behavior...............................................7
Figure 7 Front View.............................................................................................. 12
Figure 8 Left Side View......................................................................................... 12
Figure 9 Right Side View.......................................................................................13
Figure 10 Rear View............................................................................................. 13
Figure 11 Top View...............................................................................................14
Figure 12 Bottom View.........................................................................................15
Figure 13 Front Panel........................................................................................... 16
Figure 14 Rear Panel............................................................................................ 17
Figure 15 Inhibit/Voltage Monitoring DB-9 Connector........................................18
Figure 16 Inhibit Switch........................................................................................18
Figure 17 FAN Switch........................................................................................... 19
Figure 18 Fan Control Curve.................................................................................20
Figure 19 Position of temperature sensors..........................................................20
Figure 20 PXI/PXIe Modules Cooling....................................................................22

Figure 21 Power Supply Cooling...........................................................................23
Figure 22 PCI Bus Throughput for segment 1...................................................... 25
Figure 23 PCI Bus Throughput for segment 2...................................................... 26
Figure 24 PCI Bus Throughput for segment 3...................................................... 27
Figure 25 Install the JYDM....................................................................................37
Figure 26 JYDM GUI application program............................................................38
Figure 27 Monitoring the Chassis Power Rails.....................................................39
Figure 28 Monitoring the Chassis Temperature Sensors.....................................39
Figure 29 Monitoring the Chassis Fan Speed.......................................................39
Figure 30 Chassis Cooling Control in JYDM.......................................................... 40
Figure 31 Factory default Target Temperature setting........................................40
Figure 32 Change Target Temperature to 40°C................................................... 41
Figure 33 Reference Clock Status Display for default setting..............................42
Figure 34 Reference Clock Status Display for external clock source................... 42
Figure 35 Change PXI Trigger Manager Setting To JYTEK.................................... 43
Figure 36 Trigger Bus Routing Control................................................................. 44
Figure 37 Install NI MAX.......................................................................................45
Figure 38 Change PXI Trigger Manager Setting....................................................45
Figure 39 NI MAX GUI display JYTEK chassis and modules.................................. 46
Figure 40 Trigger Routing.....................................................................................47
Figure 41 DAQmx Export Signal........................................................................... 48
Figure 42 DAQ Synchronization Reference Code.................................................48
Figure 43 PXIe-2722 rack mount kits dimension................................................. 49
Table 1 PXIe-2722 series model name................................................................... 1
Table 2 Reference Clock Priority............................................................................ 6
Table 3 Basic Specification..................................................................................... 8
Table 4 Electrical Specification.............................................................................10
Table 5 System Synchronization Clock.................................................................11
Table 6 Physical and Environment....................................................................... 11
Table 7 Front Panel.............................................................................................. 16
Table 8 Rear Panel................................................................................................17
Table 9 Chassis Status LED................................................................................... 19
Table 10 Fan Mode...............................................................................................19
Table 11 PCI Bus Throughput............................................................................... 24
Table 12 PXIe-2722G3 PCIe Bus Throughput....................................................... 28
Table 13 PXIe-2722G2 PCIe Bus Throughput....................................................... 31
Table 14 Compatibility test.................................................................................. 36

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1. Introduction
Overview
PXIe-2722 series are flexibility and high performance 18-slot all-hybrid PXIe chassis
which features up to 24 GB/s system bandwidth and 58 W of power and cooling in
every slot.
Depanding on PCIe link speed capability, PXIe-2722 series provide two models as
shown inTable 1.
Model Name
PCIe Link Speed
Capability
System Bandwidth
Slot Bandwidth
PXIe-2722G3
Gen3
24 GB/s
8 GB/s
PXIe-2722G2
Gen2
8 GB/s
4 GB/s
Table 1 PXIe-2722 series model name
Note:
system bandwidth defined as data rate between controller and chassis
backplane.
slot bandwidth defined as data rate between peripheral module and chassis
backplane.
Main Features
PXI-5 PXI Express hardware specification Rev.1.0 compliant
High data throughput 18-slot PCIe Gen2 (PXIe-2722G2) or Gen3 (PXIe-2722G3)
PXIe chassis
Up to 24 GB/s (PCI Express 3.0 x8 and x16 link) system bandwidth (PXIe-2722G3)
Up to 8 GB/s (PCI Express 3.0 x8 link) bandwidth for all peripheral slots
(PXIe-2722G3)
High clock accuracy and low phase jitter
Low power ripple-noise
Specially designed for cost effective PXI/PXIe applications
0°C to 55°C extended operating temperature range
Ideal for OEM vendors

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2. Hardware
Backplane Overview
2.1.1 PXIe-2722G3 Backplane Architecture
All of the PXIe peripheral slots can support PCIe Gen3 x8 link providing a maximum
slot bandwidth of 8 GB/s. The system slot can support PCIe Gen3 x24 link (x8 + x16)
and has a maximum system bandwidth of 24 GB/s.
Figure 1 PXIe-2722 Gen3 Backplane Architecture

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2.1.2 PXIe-2722G2 Backplane Architecture
The system slot can support PCIe Gen2 x16 link (x8 + x8), it has a maximum system
bandwidth of 8 GB/s. Four of the PXIe peripheral slots have a PCIe Gen2 x8 link
providing a maximum slot bandwidth of 4 GB/s. The 13 remaining peripheral slots
have a PCIe Gen2 x4 link providing a maximum slot bandwidth of 2 GB/s.
Figure 2 PXIe-2722 Gen2 Backplane Architecture
Note:
Slot2, slot6, slot11 and slot15 can support PCIe Gen2 x8,the remaining
peripheral slots can support PCIe Gen2 x4.

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2.1.3 System Controller Slot
The System Controller slot is a fixed PCIe 2-Link configuration. Link 1 and Link 2 are
routed to PCIe switch board, and then downstream to every peripheral slot. The
chassis can accommodate a maximum 4-slot width PXIe controller.
2.1.4 Peripheral Slot
PXIe-2722 provides seventeen hybrid peripheral slots. It can accept the following
peripheral modules:
PXI Express Peripheral Module
CompactPCI Express Type-2 Peripheral Module
Hybrid slot compatible PXI-1 Peripheral Module
CompactPCI 32-bit Peripheral Module
Figure 3 PXIe-2722 Peripheral Slot Compatible Modules
Each peripheral slot PCIe link can support Gen3 x8 (PXIe-2722G3) or Gen2 x8
(PXIe-2722G2), providing maximum single-direction bandwidth of 8GB/s or 4GB/s.
And each peripheral slot can also support 32bit PCB bus, providing maximum
single-direction bandwidth of 132MB/s.

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2.1.5 PXI Trigger Bus
Three trigger bus segments on the PXIe-2722 consist of a first segment from 1st to
6th slots, a second from 7th to 12th slots, and a third from 13th to 18th slots, with
each trigger bus segment containing 8 trigger lines connecting all slots on the same
segment, providing inter-module synchronization.
Trigger bus buffers can connect or disconnect the trigger lines of adjacent segments.
As shown in Figure 5, eight combinations of trigger bus segment connections are
possible between the three bus segments, with any applicable to each of the eight
trigger lines.
Figure 4 PXI Trigger Bus Connectivity Diagram

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Figure 5 Trigger Bus Buffer Routing
Note:
The triangle shown represents the direction of the trigger.
The trigger bus buffer routing can be configured via the JYDM utility.
2.1.6 PXI Local Bus
The local bus on PXIe-2722 is a daisy-chained bus that connects each peripheral slot
with adjacent peripheral slots to the left and right, which by routing PXI Local Bus 6
signal between adjacent peripheral slots.
2.1.7 System Reference Clock and Synchronization Signal
The PXIe-2722 backplane supplies 10MHz reference clock (PXI_CLK10), 100MHz
reference clock (PXIe_CLK100) and synchronization signal (PXIe_SYNC100) to each
peripheral slot for inter-module synchronization.
The PXI_CLK10 and PXIe_CLK100 clocks are in-phase according to the PXI-5
specification. A phase-lock loop (PLL) circuit on the backplane synchronizes the
PXI_CLK10 and PXIe_CLK100 clock.
There are two 10 MHz reference clock source:
Built-in 10 MHz clock source on backplane.
External 10 MHz clock through front panel’s SMA connector.
The PXIe-2722 automatically selects the 10 MHz reference clock source and its
priority as follows.
SMA Connector on Front Panel
10MHz Clock Source of Peripheral Slots
No clock present
Backplane’s local oscillator
10MHz clock present
SMA connector
Table 2 Reference Clock Priority
The PXIe-2722 has the default timing relationship of PXI_CLK10, PXIe_CLK100 and
PXIe_SYNC100 as show in Figure 4 which comply with PXI-5 specification.