JYTEK PXIe-2519 User manual

PXIe-2519 Chassis
User Manual
User Manual Version: 1.0.3
Revision Date: September 10, 2021

Table of Contents
1.Introduction................................................................................................................1
Overview.......................................................................................................... 1
Main Features.................................................................................................. 1
2.Hardware.................................................................................................................... 2
Backplane Overview.........................................................................................2
2.1.1 Backplane Architecture......................................................................... 2
2.1.2 System Controller Slot...........................................................................3
2.1.3 Peripheral Slot....................................................................................... 3
2.1.4 PXI Trigger Bus.......................................................................................4
2.1.5 PXI Local Bus..........................................................................................4
2.1.6 System Reference Clock and Synchronization Signal............................4
Specifications....................................................................................................5
2.2.1 Basic.......................................................................................................5
2.2.2 Electrical................................................................................................ 5
2.2.3 System Synchronization Clock...............................................................6
2.2.4 Continuous Current Capability..............................................................7
2.2.5 Physical and Enviornment.....................................................................8
Mechanical Dimensions................................................................................... 9
Front and Rear Panels.................................................................................... 13
2.4.1 Front Panel.......................................................................................... 13
2.4.2 Rear Panel........................................................................................... 14
2.4.3 Chassis Status LED............................................................................... 14
2.4.4 Fan Mode............................................................................................ 15
Chassis Cooling Considerations......................................................................16
2.5.1 PXI/PXIe Modules Cooling...................................................................16
2.5.2 Power Supply Cooling..........................................................................17
3.Performance Test..................................................................................................... 18
PCI Bus Throughput........................................................................................18
PCIe Bus Throughput......................................................................................20
4.Software....................................................................................................................23
Introduction to JYDM..................................................................................... 23
Installation and use of JYDM..........................................................................23
Chassis environment monitoring in JYDM..................................................... 26
Chassis cooling control in JYDM..................................................................... 27
Chassis identification in NI MAX.................................................................... 29
5.Using PXIe-2519 Chassis...........................................................................................31
Using PXIe-2519 with JYTEK PXI/PXIe Peripheral Modules............................31
Using PXIe-2519 with National Instruments PXI/PXIe Peripheral Modules.. 31

5.2.1 Use National Instruments PXI/PXIe Peripheral Modules without
synchronization:........................................................................................... 31
5.2.2 Use National Instruments PXI/PXIe Peripheral Modules with
synchronization:........................................................................................... 31
6.Optional Equipment................................................................................................. 33
Rack Mount Kits............................................................................................. 33
7.About JYTEK.............................................................................................................. 34
JYTEK China.....................................................................................................34
JYTEK Korea and JYTEK In Other Countries.................................................... 34
JYTEK Hardware Products.............................................................................. 34
JYTEK Software Platform................................................................................ 35
JYTEK Warranty and Support Services........................................................... 35
8.Statement................................................................................................................. 36
Figure 1 PXIe-2519 Gen3 Backplane Architecture................................................. 2
Figure 2 PXIe-2519 Gen2 Backplane Architecture................................................. 2
Figure 3 Front View (PXIe-2519 Gen 3/Gen 2).......................................................9
Figure 4 Left Side View (PXIe-2519 Gen 3/Gen 2)..................................................9
Figure 5 Right Side View (PXIe-2519 Gen 3/Gen 2)............................................. 10
Figure 6 Rear View (PXIe-2519 Gen 3/Gen 2)...................................................... 10
Figure 7 Top View (PXIe-2519 Gen 3/Gen 2)....................................................... 11
Figure 8 Bottom View (PXIe-2519 Gen 3/Gen 2)................................................. 12
Figure 9 Front Panel............................................................................................. 13
Figure 10 Rear Panel............................................................................................ 14
Figure 11 PCI Bus Throughput for segment 1...................................................... 18
Figure 12 PCIe Bus Throughput............................................................................21
Figure 13 Install the JYDM....................................................................................23
Figure 14 Monitoring the Chassis Power Rails.....................................................26
Figure 15 Monitoring the Chassis Temperature Sensors.....................................26
Figure 16 Monitoring the Chassis Fan Speed.......................................................26
Figure 17 Chassis Cooling Control in JYDM.......................................................... 27
Figure 18 Install NI MAX.......................................................................................29
Figure 19 Change PXI Trigger Manager Setting....................................................29
Figure 20 Trigger Routing.....................................................................................31
Figure 21 DAQmx Export Signal........................................................................... 32
Figure 22 DAQ Synchronization Reference Code.................................................32
Table 1 Basic Specification..................................................................................... 5

Table 2 Electrical Specification...............................................................................6
Table 3 System Synchronization Clock...................................................................7
Table 4 Continuous Current Capability.................................................................. 7
Table 5 Environment.............................................................................................. 8
Table 6 Acoustic Emissions.....................................................................................8
Table 7 Backplane...................................................................................................8
Table 8 Chassis Size and Weight............................................................................ 8
Table 9 Front Panel.............................................................................................. 13
Table 10 Rear Panel..............................................................................................14
Table 11 PCI Bus Throughput............................................................................... 19
Table 12 PCIe Bus Throughput............................................................................. 20

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1. Introduction
Overview
PXIe-2519 is a high performance cost-effective 9-slot all hybrid PXI/PXIe chassis. It
complements JYTEK PXIe-62509 9-slot sturdy all hybrid chassis with the new
mechanical design that appeals to customers who wish to lower system cost but
retain the high performance.
Depanding on PCIe link speed capability, PXIe-2519 series provide two models as
shown in Table 1.
Table 1 PXIe-2519 series model name
Note:
system bandwidth defined as data rate between controller and chassis
backplane.
slot bandwidth defined as data rate between peripheral module and chassis
backplane.
Main Features
High data throughput 9-slot PCIe Gen2 (PXIe-2519G2) or Gen3 PXIe chassis
(PXIe-2519G3)
High clock accuracy and low phase jitter
Low power ripple noise
Specially designed for cost effective PXI/PXIe applications
Ideal for OEM vendors

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2. Hardware
Backplane Overview
2.1.1 Backplane Architecture
Figure 1 PXIe-2519 Gen3 Backplane Architecture
Figure 2 PXIe-2519 Gen2 Backplane Architecture

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2.1.2 System Controller Slot
The System Controller slot is a fixed PCIe 4-Link configuration. Link 1, 2 and 3 are
routed to slot2, slot3 and slot4 repectively. Link 4 is routed to PCIe switch and
downstream to slot5~slot9 and PCI bus. The chassis can accommodate a maximum
4-slot width PXIe controller.
2.1.3 Peripheral Slot
PXIe-2519 provides eight hybrid peripheral slots. It can accept the following
peripheral modules:
PXI Express Peripheral Module
CompactPCI Express Type-2 Peripheral Module
Hybrid slot compatible PXI-1 Peripheral Module
CompactPCI 32-bit Peripheral Module
Figure 3 PXIe-2519 Peripheral Slot Compatible Modules
Each peripheral slot PCIe link can support Gen3 x4 (PXIe-2519G3) or Gen2 x4
(PXIe-2519G2), providing maximum single-direction bandwidth of 4GB/s or 2GB/s.
And each peripheral slot can also support 32bit PCB bus, providing maximum
single-direction bandwidth of 132MB/s.

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2.1.4 PXI Trigger Bus
All slots on PXIe-2519 share eight trigger lines, peripheral module can deliver trigger
or clock via the trigger bus to synchronize the data acquisition operation.
2.1.5 PXI Local Bus
The local bus on PXIe-2519 is a daisy-chained bus that connects each peripheral slot
with adjacent peripheral slots to the left and right, which by routing PXI Local Bus 6
signal between adjacent peripheral slots.
2.1.6 System Reference Clock and Synchronization Signal
The PXIe-2519 supplies 10MHz reference clock (PXI_CLK10), 100MHz reference clock
(PXIe_CLK100) and synchronization signal (PXIe_SYNC100) to each peripheral slot for
inter-module synchronization.
The PXIe-2519 has the default timing relationship of PXI_CLK10, PXIe_CLK100 and
PXIe_SYNC100 as show in Figure 4 which comply with PXI-5 specification.
Figure 4 PXIe-2519 System Reference Clock Default Behavior

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Specifications
2.2.1 Basic
Table 1 Basic Specification
2.2.2 Electrical

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Table 2 Electrical Specification
2.2.3 System Synchronization Clock