Kenwood Trc-70 User manual

TAC

70

KENWOOD

SERVICE

MANUAL

©

1989-11

PRINTED

IN

JAPAN

B51-8038-00

(O)

588

Knob

(POWER

SW)

Metallic

cabinet

Knob

Front

glass

Panel

ass'y

(DRESSING

PANEL)

(K29-4540-14)

(K29-4519-04)

{A01-1087-02)

(K29-4540-14)

(B10-1129-14)

|

(A20-7061-04)

Knob

(K29-4540-14)

x

4

S68

AAG

OTE

EPHONE

Microphone

Phone

jack

Label

Knob

(MAIN

DIAL)

Foot

Knob

(T91-0388-05)

(E11-0440-05)

(B42-3379-04)

(K29-4538-03)

(J02-0323-05)

x

4

(K29-4539-04)

x

2

CONTENTS

MAINTENANCE

AND

ADJUSTMENT

............cccccee

2

CONTROL

UNIT

(X53-3280-21)

.......ccccceensereenees

85

INSTALLATION

INSTRUCTIONS.

...........cscsceseners

5

TX-RX

UNIT

(X57-3470-21)

oc

eccscceccceenssenseresens

93

CIRCUIT

DESCRIPTION

..........cessessscscesteseneserseeserses

6

FINAL

UNIT

(X45-3370-21)

..........0csseeceereseereees

101

DESCRIPTION

OF

COMPONENTS

..........ccccseeess

27

SCHEMATIC

DIAGRAM

...........ssscsssseecerseeseeeeensees

105

PARTS

LIST

0.00...

ccseececeseeeeeeeseeseeseesnesecerseuanseentesees

33

MAT-100

(AUTOMATIC

ANTENNA

TUNER)

EXPLODED

VIEW.............:cecccsscsseussessectencecssseeeseeenes

63

Circuit

Description

........cccccccsseneceeereeeseeneneees

108

PACKING

........:.cscsesceceerceseeseserensecsereresucuarsseseesseeses

65

Block

Diagram

..........scssssscsnsssne

cecceneesenereenes

122

ADJUSTMENT

........csssscsessecsseseecercscerscesscenseevsuensass

66

Description

of

Components

.........-:cccecesseceee

123

LEVEL

DIAGRAM

...........::.scssecseessseeescencerstsseeseresees

76

Parts

List

...........-cessscsssorssessesssecessse

cnseneceserensenss

124

BLOCK

DIAGRAM

..........:ssccossscsnsssssneesessresseeeeses

77

Exploded

View

.......:..:cssscssssssesesesesssceenseeeeeees

129

TERMINAL

FUNCTION

............:ccssssssssssestssssseseeses

81

PC

Board

View

CIRCUIT

DIAGRAMS

/

PC

BOARD

VIEWS

LED

UNIT

(W02-0844-08)

...........:0ccreccceeeeees

130

LCD

ASS'Y

(B38-0324-05)

.........:cssessesseesseeerees

83

ANT

MODULE

UNIT

(W02-0883-08)

...........

131

VCO

(X58-3720-10)

.......sccsscstsssesnsenseessceeersneeses

83

Schematic

Diagram

..........ccsesseseeccccceeesneseeees

133

SIDE

TONE

(X59-1060-00)

.........c.csccsssneseesees

84

Installation

INStructiONS

..........cceeeeeeeeeneeneneees

136

DC-DC

(X59-1100-O0)

........scscssscccssesssseseeeesees

84

Manual

Tuning

.............---.:cecsseecenneneeeeeeresereees

140

FAN

&

TEMP

PROTECTION

(X59-3370-00)

.....

84

Specifications

..........ccccccssecseseseen

cnnesssecesseeeees

141

VCO

(X59-3440-00)

.......:ccssescsssesessseeeenenenecses

84

SPECIFICATIONS.

.......sccecsssssessereerersees

.

BACK

COVER

TRC-70

MAINTENANCE

AND

ADJUSTMENT

Service

Your

SSB

radiotelephone

has

been

factory

aligned

and

tested

to

specification

before

shipment.

Under

normal

circumstances

the

SSB

radiotelephone

will

operate

in

accordance

with

these

instructions.

All

adjustable

trimmers

and

coils

in

your

SSB

radiotelephone

has

been

adjusted

at

the

factory

and

should

only

be

readjusted

by

a

qualified

technician

with

proper

test

equipment.

Attempting

service

or

alignment

without

factory

authorization

can

void

the

SSB

radiotelephone’s

warranty.

When

operated

properly,

the

SSB

radiotelephone

will

provide

many

years

of

service

without

requiring

realignment.

The

information

in_

this

section

gives

some

general

service

procedures

which

can

be

accomplished

without

sophisticated

test

equipment.

Should

it

ever

become

necessary

to

return

the

equipment

to

your

dealer

or

service

center

for

repair,

pack

it

in

its

original

box

and

packing,

and

include

a

full

description

of

the

problems

involved.

Also

include

your

telephone

number.

You

need

not

return

accessory

items

unless

directly

the

service

problem.

Service

note

:

If

you

desire

to

correspond

on

a

technical

or

operational

problem,

please

make

your

note

short,

complete,

and

to

the

point,

and

PLEASE

make

it

readable.

Please

list:

Model

and

Serial

Number

The

problem

you

are

having.

Please

give’

sufficient

detail

to

diagnose.

Information

such

as

other

equipment

in

the

station,

meter

readings

and

anything

else

you

feel

might

be

useful

in

attempting

diagnosis

.

Caution

:

Do

not

pack

the

equipment

in

crushed

newspapers

for

shipment.

Extensive

damage

may

result

during

shipment.

Notes

:

1.

Record

the

Date

of

Purchase,

Serial

Number

and

Dealer

from

whom

purchased.

2.For

your

own

information,

retain

a

written

record

of

any

maintenance

performed

on

the

unit.

3.

When

claiming

warranty

service,

a

photocopy

of

the

bill

of

sale,

or

other

proof

of

purchase

showing

the

date

of

sale

must

accompany

the

radio.

TRC-70

MAINTENANCE

AND

ADJUSTMENT

Top

cover

g

Adjustment

1-1.

Cover

removal

Caution

Before

removing

the

cover,

turn

the

DC

power

supply’s

power

switch

OFF

and

disconnect

the

power

cable.

Do

not

pinch

wiring

when

opening

or

closing

cases.

Remove

the

top

cover

(8

screws),

and

the

bottom

cover

(4

screws)

from

radiotelephone.

1-2.

Sub

chassis

removal

Remove

the

4

screws

as

shown

in

the

diagram.

Open

in

a

counterclockwise

direction.

1-3.

Beep

tone

level

Turn

VR7

to

the

desired

BEEP

tone

level.

VR6

TONE

(ALARM)

1-4.

Tone

level

VR7

_1.

Press

the

TONE

key.

2.

Turn

VR6

to

the

desired

TONE

level.

TRC-70

MAINTENANCE

AND

ADJUSTMENT

1-5.

Microphone

connector

Front

view

MIC

@

GND

(MIC)

ss@

SPS

oO

DOWN

@

®

8M

GND

©

@

uP

@

MIC

impedance

approx.6000

@ss

Stand-by

switch

@DOWN

Frequency

or

Memory

channel

number

decrease

@upP

Frequency

or

Memory

channel

number

increase

@8M

8V(

Max.100mA)

@®SPS

Receive

audio

output

@GND(MIC)

Mic

ground

(GND

Ground

1-6.

13.6

VDC

Power

input

connector

\—@

DC

13.6

V

\___©

eno

1-7.

Antenna

coupler

connector

NC

@

AC2@

TS

©

@NC

Not

used

@TT

Control

signal

input/output

@GND

Ground

@aAC2

Antenna

current

input

@Ts

Control

signal

input/output

@FSB

Power.output

for

antenna

coupler

TRC-70

INSTALLATION

INSTRUCTIONS

Microphone

hanger

Tapping

screw

-

Microphone

hanger

Connection

This

radiotelephone

requires

a

maximum

of

30

A

at

13.6VDC

+

15%

when

transmitting

at

full

power.

Do

not

exceed

the

length

of

the

supplied

power

cable.

=—_—_

To

Antenna

“To

Antenna

tuner

(MAF-100)

.

Supplied

DC

cable

To

vessel's

battery

Wing

bolt

We

©

ss

To

antenng

Ground.

ye

@

©

iC)

Ei)

<n

terminal)

oy

|

©

Supplied

External

Speaker

plug

To

Externa!

speaker

1

Without

antenna

coupler

The

type

of

antenna

that

is

used

will

greatly

affect

the

performance

of

the

equipment.

Use

a

properly

‘adjusted

antenna,

of

good

quality,

to

enable

your

equipment

to

perform

at

its

best.

The

antenna

input

impedance

is

50

ohms.

Use

50

ohm

coaxial

‘cable

such

as

RG-8U

or

8D-2V

for

this

connection.

If

the

antenna

is

far

from

the

transceiver

the

use

of

low

loss

coaxial

cable,

such

as

RG-8U

is

recommended.

Match

the

impedance

of

the

coaxial

cable

and

that

of

the

antenna

so

that

the

SWR

is

less

than

1.5.

The

protection

circuit

in

the

transceiver

will

activate

if

the

SWR

is

particularly

poor

(greater

than

3

).

High

SWR

values

wili

cause

the

transmitter

output

to

drop.

Antenna

tuner

(MAT-

100)

With

antenna

coupler

A

wire

antenna

must

be

in

the

range

from

2

to

24

MHz

and

having

a

total

length

of

12 to

23

meters.

When

the

radiotelephone

is

operated

only

on

low

frequencies,

a

longer

antenna

is

preferable.

The

antenna

should

be

erected

as

high

as

possible.

The

insulator

should

be

able

to

withstand

high

transmitter

power

levels

without

leakage.

Typical

installation

and

connection

Connect

the

Antenna

connector

of

the

radiotelephone

to

the

RF

IN

jack

with

the

coaxial

cable,

such

as

RG-8U

are

recommended.

Connect

the

6P

connector

of

the

supplied

control

cable

to

the

radiotelephone.

Please

refer

to

the

MAT-100

Instruction

Manual

to

connect

with

the

cable

to

the

MAT-100.

TRC-70

CIRCUIT

DESCRIPTION

Frequency

Configuration

The

second

IF

signal

(10.695

MHz)

passes

through

a

crystal

filter,

and

is

then

applied

to

IC2

:

KCD03

where

the

signal

is

demodulated.

The

demodulated

audio

output

is

amplified

by

the

AF

preamplifier

and

power

amplifier

to

drive

the

speaker.

The

TRC-70

operates

as

a

double

conversion

sys-

tem

for

both

transmission

and

reception.

(See

Figure

1.)

*

Receiver

system

The

receive

signal

from

the

ANT

terminal

passes

through

the

final

unit

and

the

TX-RX

unit

LPF

and

is

applied

directly

to

mixers

Q9

and

Q10

(2SK125-5).

Here

the

signal

is

mixed

with

the

first

local

oscillator

frequency

(71.395~101.295

MHz)

from

the

PLL

in

or-

der

to

generate

the

first

IF

signal

of

71.295

MHz.

The

receive

frequency

may

be

fine

tuned

with

the

clarifier

by

varying

the

first

local

oscillator

frequency.

The

71.295

MHz

first

IF

signal

passes

through

a

monolithic

filter

(MCF)

and

is

mixed

with

the

second

local

oscillator

frequency

(60.6

MHz)

by

MIX

FETs

013

and

O14

(2SK520(K44))

to

generate

a

10.695

MHz

second

IF

signal.

The

second

local

oscillator

signal

is

generated

by

the

TX-RX

unit

Q90

and

Q91

(2SC2714(Y))

and

is

then

doubled

by

Q56

(2SC2714(Y)).

*

Transmitter

system

The

audio

signal

from

the

microphone

is

amplified

by

mic

amplifiers

O37

and

038

:

2SC3324(G),

and

is

then

combined

with

the

carrier

oscillator

in

the

bal-

anced

modulator,

(IC6

:

4PC1037A)

to

generate

the

TX

first

IF

(10.695

MHz).

In

the

H3E

mode,

a

carrier

signal

is

added

to

the

TX

first

IF

(10.695

MHz).

The

TX

first

IF

is

then

mixed

win

the

second

local

oscillator

frequency

(60.6

MHz)

by

|C7

:

SN16913P

in

the

same

manner

as

the

receiver

sys-

tem,

to

produce

a

71.295

MHz

signal.

This

signal

is

then

mixed

with

the

PLL

first

local

oscillator

frequency

in

order

to

generate

a

transmit

signal.

10.695MHz

SSB.CW.XF2

SP

Q29:2$C332.4

(GR)

IC2:KCOO03

Q13.14:2SK520(K44)

=

71.295MHz

Q9.10:2SK125-5

LPF

IC5:pPC1242H

OFT

2nd

MIXER

MCF

ist

MIXER

AF

10.695MHz

AMP

H3E_XF

BPF

ANT

0.\~3OMHz

XF3

TT

~~

7

ist

Local

freq.

CAR

71.395~101.295

MHz

USB

|

10.6965

MHz

|

USB:

+1.5

KHz

LSB

:10.6935MHz

PLL

LSB:

—1

5

KHz

RX:

CW:4+0.7KHz

CW-RxX

:

10.69

65MHz

osec2sceTiacy)

|

SYSTEM

|

CW-TX:

10.6957MHz

Q90.9I:

27iay)

H3E-RX:

O

KHz

H3E~-TX:

10.6965MHz

Zz

9

(x2)

|_|

|

HSE-TX:

445.5

KHz

=

a

2nd

local

|

"

a

G0.

6MHz

L_.

—_

—_J

10.695MHz

SSB.CW

H3E:ON

XF

(Shored

by

receiver

ystem)

—

71.295

MHz

MCF

(Shored

by

receiver

10.695MHz

H3E

+

y

=

FINAL.

MIC

XF

(Shared

by

:

+

NIT

pL

P.F

}—

AMP

receiver

system)

Thess

U

MIC

Q37.38

TX

BM

MIXER

Qi

Q4.5:

28028791(0,Y)

[28C3324(G)

!c6

=

IC7

:

SN16913P

Q51.52

:

2SC197I

1

PCIO37HA

:3SKI7T9(L)

022

3

CSI33

Fig.

1

Frequency

configuration

TRC-70

CIRCUIT

DESCRIPTION

The

reference

frequency

for

loops

A,

B,

and

C

is

10.1

MHz.

This

frequency

is

generated

by

dividing

the

30.3

MHz

reference

oscillation

frequency

by

3.

There-

PLL

(Phase

Locked

Loop)

The

TRC-70

PLL

is

divided

into

a

HET

loop

and

a

CAR

loop.

The

HET

loop

consists

of

loop

A

and

loop

B,

fore,

the

frequency

accuracy

of

the

HET

and

CAR

is

determined

by

the

30.3

MHz

oscillation

circuit.

and

the

CAR

loop

consists

of

loop

C.

Figures

2

and

3

show

a

block

diagram

of

the

HET

and

CAR

loops.

The

following

paragraphs

describe

loops

A,

B,

and

C.

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TRC-70

CIRCUIT

DESCRIPTION

Loop

B

generates

a

37.5~39.5

MHz

signal

via

IC6

Frequency

(CXD1225M)

with

a

1

kHz

comparison

frequency.

The

_|

Function

O.1~7MHz

|

7~14MHz

|

14~22MHz

|

22~3OMH2

37.5~39.5

MHz

signal

is

generated

by

VCO6

(X59-

Microprocessor

|

V1

0

1

0

1

3440-00),

then

divided

by

100

in

C7

:

M54459L

to

gen-

control

signal

|

V2

0 0

1 1

erate

a

10

Hz

steps.

Fine-frequency

adjustment

by

means

of

the

clarifier

is

added

to

loop

B

under

micro-

processor

control.

The

375~395

kHz

output

signal

that

was

divided

by

100

by

IC7

is

mixed

with

the

30.3

MHz

BPF

BPFI

|

BPFI

|

BPF2

signal

by

IC8

:

SN16913P

in

order

to

generate

a

wo

as

30.675~30.695

MHz

signal.

This

frequency

passes

Table

1

Switching

of

Loop

A

VCO

and

BPF

through

MCF

(XF1;

30.685

MHz)

and

enters

IC5

vcoO

vco1

vCO2

VCO3

VvCO4

BPF2

(SN76514N).

Loop

A

generates

a

71.395~

101.295

MHz

signal

via

IC3

(CXD1225M)

with

a

comparison

frequency

of

20

J3E

USB.

CWR.

H3E=10.6965MHz

kHz.

This

signal

becomes

the

HET

oscillator

signal.

manana

ae

So

coese

The

loop

A

VCO

(X58-3720-10)

consists

of

four

sepa-

rate

VCO

circuits

which

are

selected

by

IC4

(TC4028)

AMP

{

FILTER

according

to

the

control

data

from

the

microprocessor.

UNLOCK

—sf

22?

cri

(See

Table

1.)

Part

of

the

loop

A

VCO

output

passes

2sc2714

{Y)

through

the

buffer

amplifier

of

Q9

:

28C2714(Y)

and

is

LPF

mix

4

applied

to

|C5.

The

signal

is

then

mixed

with

the

signal

x

1c11

from

loop

B

in

IC5

:

SN76514N

(40.72~70.62

MHz).

~~

SN16913P

The

resulting

40.72~70.62

MHz

signal

passes

through

v0}

10.1MHz

BPF1

and

BPF2.

VCO1

and

VCO2

pass

the

signal

through

BPF1,

and

VCO3

and

VCO4

pass

it

through

Wet

a50L

BPF2.

The

signal

passing

through

the

BPF

is

amplified

by

Q10

and

Q11

:

28C2714(Y)

and

is

then

applied

to

—22*

ot

a

PLL

IC3

(CXD1225™).

73

ws

Loop

C

generates

a

59.3~59.7

MHz

via

IC9

X59-3440-00

FMU1

(CXD1225M)

with

a

2

kHz

comparison.

This

VCO

out-

put

is

divided

by

100

by

IC10

:

M54459L,

and

is

mixed

LPF

i

with

10.1

MHz

by

IC11

:

SN16913P

to

generate

a

022,

23,

24

10.693~10.697

MHz

signal.

The

10.693~10.697

MHz

28C3325(G)

signal

passes

through

ceramic

filter

CF1

to

become

—_—

|—

——

—f—

the

CAR

signal.

The

CAR

signal

changes

with

the

[

L

mode.

It

is

amplified

by

Q27

and

is

then

sent

to

the

|

uN

Lt

pc

—»

C-U

TX-RX

unit.

|

N=29650~29850

{

1

|

1/5100

|

Ic9

:

CXD1225M

Fig.

3

Block

diagram

of

PLL

CAR

loop

TRC-70

CIRCUIT

DESCRIPTION

*

CAR

stop

circuit

in

AM

receive

mode

In

the

CW

and

SSB

modes,

the

8

V

DC

power

for

the

last

mixer

IC

(IC11

:

SN16913P)

of

the

CAR

loop

is

supplied

through

Q26

:

2SC2712(Y).

In

the

H3E

re-

ceive

mode,

8

V

is

applied

to

3

of

the

TX-RX

unit

shift

register

C10

(TC9174F)

according

to

the

data

supplied

from

the

microprocessor.

The

8

V

is

supplied

to

the

control

unit

via

the

CAR

coaxial

cable.

This

sets

028

:

DTC114EK

on,

changes

Q26

from

on

to

off,

disables

1C11,

and

stops

CAR.

¢

Unlock

circuit

Normally

8

V

(8C)

is

fed

to

the

HET

and

CAR

transis-

tors

O8

and

Q27

via

Q21.

(Q21

is

on.)

When

any

of

the

PLL

loops

(loop

A,

B,

and

C)

should

unlock,

8

of

the

corresponding

PLL

IC

(IC3,

IC6,

IC9

:

CXD1225M)

will

go

H

(5V).

This

causes

Q19

to

switch

on,

and

Q20

and

Q21

to

switch

off.

This

action

causes

the

voltage

applied

to

Q8

and

Q27

to

be

removed.

Meanwhile

Q29

switches

on,

and

LED

D10

turns

on

to

indicate

the

unlocked

state.

(cll

ouT

vcc

10.1IMHz

—-—_

LV

8S

a

7

SIG

kd

593~597

KHz

CFI

Vv

R92

Q27

CONTROL

UNIT

(PLL)

””

‘

(X53-3280-21)

1

|

R36

|

HET|

|

a8

|

i

|

r----

_

[o-oo

TX-RX

UNIT

(X57-3470-21)

RX:AM

MODE

8V

SHIFT

REGISTER

(170)

Fig.

4

CAR

stop

circuit

in

AM

receive

mode

and

PLL

unlock

circuit

TRC-70

CIRCUIT

DESCRIPTION

Control

Unit

¢

Control

unit

configuration

The

main

LSI

chips

in-the

control

unit

include

CPU

:

IC302,

ROM

:

1C310,

EEPROM

:

1C311,

and

extended

YO

IC

:

IC300.

The

CPU

reads

the

program

from

the

ROM,

reads/

writes

memory

channel

data

to

EEPROM,

and

inputs

and

outputs

signals

from

the

CPU

ports

or

extended

I/

O

IC

ports.

The

address

signal

(8

low-order

bits)

required

for

the

CPU

to

access

the

ROM,

EEPROM,

and

extended

1/0

iC

is

multiplexed

with

other

data

and

output

to

the

bus

line.

The

address

is

maintained

for

the

necessary

period

of

time

by

latching

1C303.

The

chip

select

(CS)

signal,

which

selects

a

the

desired

device

(ROM,

EEPROM,

etc.},

is

supplied

to

each

device

by

decoding

the

address

signal

by

C304

:

10

*

Bus

operation

The

ROM

(IC310),

EEPROM

(1C311),

and

extended

I/O

IC

(IC300)

are

connected

to

the

CPU

(IC302)

via

the

bus

line.

When

the

CPU

accesses

these

ICs

(iC310,

1C311,

and

1C300),

the

address

signals

(A13

to

A15)

output

from

the

CPU

are

decoded

by

1C304,

and

the

IC

is

specified

by

the

CS

signal.

1C310

(ROM)

uses

the

CPU

address

signal

A15

as

a

CS

signal.

Table

2

is

a

truth

table

for

IC304.

This

bus

is

a

multiplexed

bus

onto

which

an

address

code

and

data

are

output

alternately.

Therefore,

when

the

CPU

accesses

one

of

the

ICs,

the

necessary

ad-

dress

signal

is

latched

by

IC303.

This

latch

uses

the

positive

pulse

applied

to

the

ALE

pin,

after

the

CPU

outputs

an

address.

TC74HC138AF.

INPUT

OUTPUT

AlB|cC1¥o!¥1

1

Y2!

3]

Ya

|

Ys

|

Ye

|

Y7

oj;/o;o;otl1}7}1/111

71 41

o;/oj1);1/o0;1]/14)1)15111

ofi};olr}1}o0%r1f}4]144

41

olfi}airir}+riorprtr1)

14d

ass}

10304

7/o0/}o};1}1]71]1)/o0

47141

41

(decoder)

1

0

1 |

| 1

1

0

4 1

TC74HCI3Z8AF

7/1704]

47477

$7

$1)

041

1/1)

a7r)1]a]r74faqgia]o

ABA5

1c

302

TAble

2

Truth

table

for

IC304

:

TC74HC138AF

(CPU)

A0-7

IC303

(Latch)

sPD7BCIOAG-36

TC74HCS73AF

N—p

CS

00~7

Ke

IC3IO

A0-I3

(ROM)

27CI28-20

cs

<<

|s{

is)

IC3Il

2

ST

Taoctol|

(EEPROM)

w

m

g

MSM28C16

A-20RS

[cs

kK

Ic300

AO-2

(Extended

{/0)

CXxDIO95Q

Fig.

5

Control

unit

block

diagram

TRC-70

CIRCUIT

DESCRIPTION

«

Key

scan

matrix

Scan

input

Active

L

pulses

are

output

from

SO

(PCO

11)

to

KO

K1

K2

K3

K4

S6

(PC7

18),

in

the

order

listed,

and

input

through

So

|

ENT

MOD

3

2

1

ports

KO

(PB3

5)

to

K4

(PB7

9).

Which

switch

S1|

SCN

6

5

4

has

been

pressed

is

determined

by

finding

where

the

$2

|

C/FUNC

)

9 8

7

lines

intersect

on

the

matrix.

Scan

|

S3|

TUNE

SQL

NB

DIMMER

|

TONE

.

output|

S4

«

Display

$5

The

CPU

calculates

the

display

data

and

transfers

$6

|

DIP1

DIP2

DIP3

DIP4

112-bit

serial

data

to

the

LCD

module.

The

LCD

driver

$7

|

D311

D312

D313

D314

IC

in

the

LCD

module

lights

the

LCD

dynamically

with

50%

duty

cycle.

Figure

6

shows

the

serial

data

waveform.

10302

4;

=o

19

CL

EL

i

LJ

L_

Pc2

-———_

>

17

DL

LCD

reo

fot

of

ef

oS

LS

1

FLIFL

LS

WL

PC4

«

JO0OGRE000000

&

)

.<

_

.

aa

52bit

Fig.

6

Serial

data

waveform

LcD1I

LU1568

R3

360

S|

3

=

N

|

Ra

360)

5

3

RS

360

d

R6

360

1C1

o—w—-#

LC7582A

R7

360

4

(a)

aq

o

o1z

Oo Ww

xX

ok&

aA

BLzSsFba

8

Yeo

8

Bl

By

8]

Bl

Sl

ols

BLii6AY

CN1

sfolEt

gl

ofch

ah

ofot

sl

oft?

:

sl

ofts

23

a)

ope

etal

s[st

:

§

~

=

3|

of

sie,

81

a.

=

81

8L

SL

2lo0

Ls

>

rT)

©

:

3

AME

s]

sf

sl

se]

87

[

sts]

8]

Fig.

7

LCD

module

circuit

diagram

1

TRC-70

CIRCUIT

DESCRIPTION

«

Backup

The

TRC-70

backs

up

data

in

two

ways.

The

first

is

a

semipermanent

backup

that

backs

up

memory

chan-

nel

data

in

the

nonvolatile

memory

EEPROM.

The

second

is

a

lithium

cell

that

backs

up

the

operation

status

in

the

CPU

RAM.

The

CPU

backup

is

performed

by

monitoring

the

CB

(13.6

V)

line.

If

the

voltage

falls

below

the

prescribed

level,

the

CPU

STOP

is

activated

and

CPU

power

consumption

is

reduced.

When

the

power

consump-

tion

is

low,

the

CPU

stops

generating

clock

signal,

which

places

each

port

is

at

a

high

impedance

level.

WwW

a

u

©

sToP

CPU

4

5V

pt

84)

vce

BA300

¢

System

reset

circuit

IC305

(M51951BML)

is

the

system

reset

!C

that

monitors

the

power

supply

voltage.

If

the

voltage

falls

below

the

prescribed

level,

it

outputs

a

reset

signal

to

®

the

main

CPU

to

stop

execution

and

inhibit

memory

LA-

-----4t----t%-

write

functions.

°

If

the

power

supply

voltage

again

exceeds

the

pre-

®

|!

scribed

level

when

the

power

is

on,

the

reset

signal

is

/

released,

the

main

CPU

is

initialized,

and

execution

is

resumed

after

the

time

constant

of

R375

and

C379

has

elapsed.

©

RES

RESET

|

RESET

—e—

5V

1€305

(MSISSIBML)

IC306

IC307

_—_—

{se

2

1c302

CPU

RESET

©

To

IC3tl

WR

through

[C308

Fig.

9

Reset

circuit

and

timing

chart

12

TRC-70

CIRCUIT

DESCRIPTION

«

Clarifier

When

the

clarifier

knob

is

turned

a

DC

voltage

corre-

sponding

to

the

rotation

angle

is

produced.

The

input

voltage

is

A/D

converted

by

the

CPU

and

PLL

data

is

controlled.

The

data

is

controlled

in

the

CPU

so

that

the

curve

C302

=

R388

CPU

CLARFIERS

4

vrR200

>"

PLANO

A

VW

a

ww

@

~“

Fig.

10-1

Clarifier

circuit

*«

Encoder

When

the

encoder

is

turned,

a

pulse

having

a

90-

degree

phase

shift

is

input

to

the

CPU.

The

EN1

pulse

is

applied

to

PC3

of

20

and

INT1

of

26.

The

CPU

detects

the

trailing

edge

of

the

waveform

via

PC3

and

the

leading

edge

by

INT1

and

begins

interrupt

op-

eration.

It

checks

PC1

of

18,

judges

the

rotational

direction,

counts

1,

then

performs

up/down

process-

ing

of

the

frequency

and

channel

data.

Since

the

encoder

is

a

mechanical

device,

it

pro-

duces

chattering,

but

it

is

designed

not

to

malfunction

by

software

means.

20

PCS

EN!

INTL

10302

Encoder

18

CPU

>

-ENa

PC!

Fig.

11

Encoder

circuit

shown

in

Figure

10-2

is

obtained.

Operation

of

the

circuit

is

improved

by

enlarging

the

zero

area

at

the

center

of

the

rotation

angle.

The

zero

point

of

the

clarifier

is

adjusted

by

setting

the

knob

to

the

mechanical

center,

then

setting

zero

with

VR303.

Fine

adjustment

frequency

4

+f

l

_i.

L

1

lL

—

Center

Rotation

angle

>

Effective

operation

range

ii-

<@

pa

>

atl

Physical

rotation

range

Fig.

10-2

*

Receive

signal

switching

The

MU

signal

switches

the

AF

signal

and

the

BLK

signal

switches

the

RF

signal.

When

switching

from

one

PLL

loop

to

another

an

active

H-pulse

is

generated

to

supress

any

noise.

In

the

TX

mode

and

during

memory

write

operation,

the

MU

signal

is

output

continuously

to

cut

off

the

audio.

13

TRC-70

CIRCUIT

DESCRIPTION

open

squelch.

When

the

SQL

SW

is

on

and

the

VSQ

signal

is

H,

the

SOS

signal

goes

H.to

close

squelch.

If

the

VSQ

signal

is

L,

the

SOS

signal

goes

L.

*

Squelch

control

The

CPU

inputs

the

SOL

SW

status

by

means

of

a

key

scan.

When

the

SQL

SW

is

off,

the

SQS

signal

goes

L

to

|

{C302

(CPU)

|

R305

3

|

PA2

| |

R359

|

dvsa

r

|

-—e

al

|

D0~D7

|

1C3

SQL

|

KCXO2

so

|

ah

>

SQL

R310

KIS]

554

pa

22

‘i

|

4

|

C146

PC3

|

$3

1¢300

|

TX-RX

UNIT

xs7s470-21)

|

_

CONTROL

UNIT

(X53-3280-21)

|

sx.2x

UNIT

(X57-3470-21)

Fig.

12

Squelch

control

circuit

*

Noise

bianker

switching

1C302

The

CPU

inputs the

NB

SW

status

by

key

scan.

PAa3}¢-—+w——

ae

NBI

When

the

NB

SW

is

pressed,

the

display

changes

from

OFF

to

NB1

to

NB2

to

OFF,

and

the

NB1/NB2

port

is

controlled

as

listed

in

Table

3.

R307

When

the

display

is

NB2,

both

NB1

and

NB2

oper-

pc7}eww-———

NB2

ate.

Display

|

NB1

NB2

Ot

KS

PB6

OFF

L

NB1

H

L

D

$3.

PC3

NB2

H

Table

3

1€300

Fig.

13

Noise

blanker

switching

circuit

14

TRC-70

CIRCUIT

DESCRIPTION

«

Dimmer

Brightness

PAG

PAS

PA4

Each time

the

DIMMER

SW

is

pressed,

it

changes

MAX

L

H

from

MAX

to

MEDIUM

to

MIN

to

OFF

to

MAX.

Table

MED

L

H

L

4

lists

the

PA4

to

PA6

outputs.

MIN

H

L

OFF

L L L

Table

4

CB

@

LCD

module

;

1303

=

“—o

al

1C301

R356

He

46

LED

|

PAG

62

~

W-

mis

lamp

array

|

L_

—

_I

R355

pas

[ote

WMA

+

|

>

A

PAd

La

W-

>

2

>

Fig.

14

Dimmer

circuit

1C300

R363

*

Tone

output

pp7

on

M—e-—>

ALM

The

1500

Hz

tone

by

the

TONE

SW

is

output

by

|

2K

$

|

=

3

generating

a

pseudo

sine

wave

by

D/A

output

and

PDs

|

7}

>

passing

it

through

the LPF.

This

tone

has

a

step

wave-

aes

|

form

with

a

1/11

cycle.

|

7

PDS

l

MM

|

=

|

CP300

PD4

|

WW

|

it

PD3

AM

|

PD2

Ww-

|

PDI

W-

:

PDO

:

Wy

|

cS

Lj

15

Fig.

15

Tone

output

circuit

>

TRC-70

16

¢

Terminal

functions

1)

CXD10950

:

Control

unit

1C300

CIRCUIT

DESCRIPTION

Portname

|

No.

Name

|

1/0

Function/operation

PAO

54

MU

O

|

AF

mute.

During

memory

input.

PAI

55

Sas

O

|

Squelch

contro!.

When

squelch

is

closed.

PA2

56

HRL

O

|

HS

relay

control.

When

the

speaker

is

switched

to

the

external

speaker.

PA3

59

TTO

O

|

Through

instruction.

When

through

operation

is

instructed

to

AT.

PA4

60

DM2

O

|

Dimmer

control.

See

page

16.

PA5

61

DM1

e)

PA6

62

DMO

e)

PA7

63

O

|

Unused.

PBO

64

PTT

|

MIC

PTT.

When

PTT

SW

is

on.

PB1

3

|

Unused.

PB2

4

|

Unused.

PB3

5

KO

|

Key

scan

output.

When

SW

is

pressed.

PB4

6

Ki

I

PB5

7

K2

I

PB6

8

K3

{

PB7

9

K4

|

PCO

11

SO

O

|

Key

scan

output.

When

the

key

scan

strobe

pulse

output.

PC1

12

$1

fe)

PC2

13

$2

0

PC3

14

$3

e)

PC4

15

$4

16)

PC5

16

$5

e)

PCE

17

sé

ie)

PC7

18

S7

e)

PDO

20

O

|

Tone

D/A.

When

tone

is

output.

PD1

21

(@)

PD2

22

16)

PD3

23

fe)

PD4

24

O

PDS

27

(e)

PD6

28

ie)

PD7

29

ie)

PEO

49

DS

O

|

Serial

data.

PE1

50

cS

O

|

Serial

CK.

PE2

52

ES2

O

|

Enable.

PE3

53

ES1

oO

Vss

10

GND.

Vss

25

GND.

VDD

26

Power

input

pin.

DO

30

Bus

pin.

D1

31

Bus

pin.

D2

32

Bus

pin.

D3

35

Bus

pin.

D4

36

Bus

pin.

D5

37

Bus

pin.

D6

38

Bus

pin.

D7

39

Bus

pin.

CLR

40

Unused.

Fixed

to

H

for

data

write.

ODEON

4)

Unused.

Fixed

to

H

for

data

write.

Vss

42

GND.

WR

43

Strobe

input

for

data

write.

RD

44

Strobe

input

for

data

read.

CIRCUIT

DESCRIPTION

TRC-70

Port

name

|

No.

Name

1/0

Function/Operation

CS

45

Chip

select

input.

AO

46

Address

input

for

selection

of

port

and

control

register.

Al

47

Address

input

for

selection

of

port

and

control

register.

A2

48

Address

input

for

selection

of

port

and

control

register.

Vss

57

GND.

Vop

58

Power

input

pin.

2)

uPD78C10AG-36

:

Control

unit

IC302

Port

name

|

No.

Name

0

Function/Operation

PCO

17

DL

O

|

Serial

data

for

LCD.

PC1

18

EN2

|

Encoder

CK2.

PC2

19

CL

O

|

Serial

CK

for

LCD.

PC3

20

EN1

{

|

Encoder

CK1.

PC4

21

EL

O

|

LCD

enable.

PCS

22

KEY

|

Key.

When

marked.

PC6

23

BZ

O

|

Buzzer.

PC7

24

NB2

O

|

NB

switching.

When

NB2

operates.

PDO

55

DO

YO

|

Bus.

PD1

56

D1

VO

|

Bus.

PD2

57

D2

/O

|

Bus.

PD3

58

D3

/O

|

Bus.

PD4

59

D4

YO}

Bus.

PDS

60

D5

VO

|

Bus.

PD6

61

D6

(0

|

Bus.

PD7

62

D7

1/0

|

Bus.

PFO

47

A8

O

|

Address.

PF1

48

AQ

O

|

Address.

PF2

49

A10

O

|

Address.

PF3

50

Alt

O

|

Address.

PF4

51

Al2

O

|

Address.

PF5

52

Al3

O

|

Address.

PF6

53

Ai4

O

|

Address.

PF7

54

A158

O

|

Address.

MNI

25

l

Unused.

INT1

26

EN1

|

Encoder

CK1.

ANO

34

CL2

|

Clarifier.

AN1

35

M

|

Level

meter.

AN2

36

PLSB

|

LSB

correction.

AN3

37

PUSB

{

|

USB

correction.

AN4

38

DLY

|

Delay

VR.

AN5

39

|

Unused.

AN6

40

UP

|

MIC

UP,

When

SW

is

on.

AN7

Aj

DW

|

MIC

DOWN.

When

SW

is

on.

PAO

1

STT

O

|

TX

8T

switching.

In

TX

mode.

PA1

2

BLK

O

|

RF

mute.

When

PLL

is

switched.

PA2

3

VSQ

|

Audio

squelch.

When

an

audio

signal

is

present.

PA3

4

NB1

O

|

NB

switching.

When

NB1

and

NB2

operate.

PA4

5

TSO

O

|

AT

tune

start.

PA5

6

TTI

|

AT

tune

end.

PAS

7

V2

O

|

VCO

switching.

PA?

8

V1

0)

PBO

9

EP2

O

j

PLLIC

enable.

PBI

10

EP3

fe)

PB2

11

EP1

ie)

17

TRC-70

18

CIRCUIT

DESCRIPTION

Portname

|

No.

Name

0

Function/Operation

PB3

12

cP

O

|

Serial

CK

for

PLL

IC.

PB4

13

DP

O

|

Serial

data

for

PLL

IC.

PB5

14

STR

O

|

RX

8R

switching.

In

RX

mode.

PB6

15

O

|

Unused.

PB7

16

TSI

©

|

AT

through

response.

MODE

1

27

|

Specify

the

size

of

the

external

memory.

Fixed

to

H

level.

RESET

28

|

Reset

input.

Usually

H.

MODE

0

29

|

Specify

the

size

of

the

external

memory.

Fixed

to

H

level.

X2

30

|

Crystal

connection

for

internal

clock

generation.

x1

31

|

Crystal

connection

for

internal

clock

generation.

Vss

32

1

|

GND.

A

Vss

33

{

|

A/D

converter

GND

pin.

VAREF

42

|

AVD

converter

reference

voltage

input

pin.

A

Vop

43

|

A/D

converter

power

pin.

RD

44

O

|

Strobe

signal

output

for

external

memory

read

operation.

WR

45

©

|

Strobe

signal

output

for

external

memory

write

operation.

ALE

46

©

|

Strobe

signal

to

externally

latch

the

low-order

address

output

to

pins

PDO

to

PD7

to

access

the

external

memory.

STOP

63

{

|

Control

input

in

the

hardware

stop

mode.

Vop

64

|

Go

L

for

backup.

3)

TC9174F

:

TX-RX

unit

IC9

Portname

|

No.

Name

i/o

Function/Operation

OP1

2

B8

Q

|

BPF

switching

signal.

OP2

3

B7

(e)

OP3

4

B6

io)

OP4

5

BS

6)

OP5

6

B4

oO

OP6

7

B3

ie)

OP7

8

B2

ie)

OP8

9

Bi

‘s)

OPg

10

O

+

Unused.

OP10

11

TUNE

O

|

Power

control

at

AT.

During

tune

transmission,

4)

TC9174F

:

TX-RX

unit

IC10

Portname

|

No.

Name

/0

Function/Operation

OP1

2

O

|

Unused.

OP2

3

AM

O

|

In

H3E

mode.

OP3

4

CW

O

|

In

CW

mode.

OP4

5

ALS

OQ

|

Tone

mute.

When

tone

is

output.

OP5

6

FL3

O

|

LPF

switching

signal.

OP6

7

FL2

oO

OP7

8

FLA

O

OP8

9

O

|

Unused.

OPS

10

M-POW

|

O

|

Power

control.

OP10

11

L-POW

|

O

TRC-70

CIRCUIT

DESCRIPTION

Receiving

Circuit

Configuration

BPF

NO.

|

Frequency

(MHz)

Bi

0.1~1.5999

B2

1.6~2.9999

B3

3.0~4.9999

B4

5.0~6.9999

BS

7.0~8.9999

B6

9.0~13.9999

B7

14.0~17.9999

BS

18.0~29.9999

Tabie

5

Receiving

bandpass

bilter

table

+

Automatic

gain

control

(AGC)

circuit

The

output

of

final-stage

intermediate-frequency

(IF)

amplifier

Q15

(83SK131(M))

is

amplified

by

IF

hybrid

IC2

(KCDO3)

to

produce

an

AGC

voltage

with

a

voltage

doubler

rectifier.

This

AGC

voltage

is

fed

to

a

two-

stage

!F

amplifier

in

|C2

and

the

second

gates

of

FETs

Q12

and

Q15

(8SK131(M))

to

control

the

gain.

¢

Squelch

circuit

The

detected

output

of

IC2

is

partially

sent

to

hybrid

IC3

(KCX02)

and

is

used

as

a

squelch

circuit

signal.

A

high

or

low

digital

VSQ

signal

is

output

from

hybrid

IC3,

then

input

to

the

CPU.

The

CPU

outputs

an

SQS

signal

and

mutes

it

using

audio

frequency

(AF)

preamplifier

Q29

(2SC3324(G))

for

squelch

control.

¢

Noise

blanker

(NB)

circuit

The

input

of

the

NB

circuit

is

extracted

from

the

outputs

of

second-stage

RX

mix

FETs

Q13

and

Q14

(2SK520(K44))

and

is

applied

to

the

NB

hybrid

1C1

(KCX01).

The

input

signal

is

amplified

and

detected

by

IC1

then

output

as

a

noise

blanking

signal.

The

opera-

tion

of

IF

arnplifier

Q15

(83SK131(M))

is

stopped

by

NB

switching

transistor

Q16.

Noise

components

are

then

eliminated.

NB1

is

used

for

short-duration

pulses

such

as

igni-

tion

noise.

NB7

is

used

for

longer-duration,

long

dura-

tion

pulse

noise

such

as

the

woodpecker.

Transmitting

Circuit

Configuration

The

transmitter

utilizes

a

double-conversion

system.

An

audio

signal

from

the

microphone

is

amplified

by

microphone

amplifiers

Q37

and

Q38

(2SC3324(G))

and

modulated

by

double-balanced

mixer

(BM)

IC6

(uPC1037A).

The

modulated

output

is

converted

to

a

DSB

signal,

passed

through

10.695

MHz

single-side-

band

(SSB)

filter

XF2,

then

converted

to

an

SSB

signal.

The

SSB

signal

is

then

amplified

by

TX

IF

amplifier

Q45

(3SK131(M))

in

the

first

stage.

An

ALC

voltage

is

applied

to

the

second

gate

of

Q45

by

a

dual

MOS

FET

iF

amplifier

to

control

the

transmitter

output.

Audio

signals

in

the

H3E

mode

are

also

modulated,

like

an

SSB

signal,

passed

through

a

filter,

then

ampli-

fied

by

Q45.

A

carrier

signal

is

added

to

the

amplified

signal

by

a

circuit

consisting

of

Q48

and

O49

producing

an

HGE

signal.

The

10.695

MHz

signal

amplified

by

Q45

is

mixed

with

a

60.6

MHz

signal

by

second-stage

mixer

IC7

(SN16913P),

then

converted

to

a

71.295

MHz

signal.

Spurious

components

in

the

71.295

MHz

signal

are

eliminated

by

a

monolithic

crystal

filter

(MCF)

(XF1).

The

resultant

signal

is

amplified

by

dual

gate

MOS

FET

amplifier

Q50

(8SK129(L)).

When

a

high

SWR

is

felt

at

the

antenna,

the

ALC2

voltage

at

the

second

gate

of

Q50

is

reduced

and

the

transmitting

output

level

is

lowered

to

protect

the

transistor

in

the

final

stage.

The

amplified

transmitting

IF

signal

is

input

to

a

double-

balanced

mixer

consisting

of

FETs

Q51

and

Q52

(3SK179(L)),

then

converted

to

the

desired

transmit-

ting

frequency.

The

converted

signal

is

passes

through

a

low-pass

filter

to

eliminate

higher

harmonic

compo-

nents

and

is

then

amplified

to

the

signal

level

required

for

a

finalstage

drive

circuit

by

transistor

Q53

(2SC2053).

The

drive

output

is

sent

to

the

final-stage

unit

and

amplified

to

a

sufficient

output

level

by

wideband

pre-

drive

amplifier

Q1

(2SC1971),

wideband

push-pull

drive

amplifiers

Q2

and

Q3

(2$C3133),

and

wideband

push-

pull

amplifiers

Q4

and

Q5

(2$C2879(0,Y))

in

the

final

stage.

Predrive

amplifier

Q1

has

a

fixed

bias

and

is

ther-

mally

coupled

with

diode

D1.

The

bias

currents

of

drive

amplifiers

Q2

and

Q3

and

fina!l-stage

amplifiers

Q4

and

O5

are

adjusted

by

VR1

and

VR2.

Diode

D2

is

thermally

coupled

with

Q2,

D3

with

Q4,

and

D4

with

Q6.

Diodes

D1

through

D4

compensate

for

the

tem-

perature

in

each

stage

and

prevent

thermal

runaway.

19

TRC-70

20

CIRCUIT

DESCRIPTION

|

The

outputs

of

04

and

QO5

in

the

final

stages

passes

through

low-pass

filters

for

each

band

to

eliminate

higher

harmonic

components.

The

low-pass

filter

out-

puts

passes

through

transmit

relay

K115

and

is

applied

to

the

antenna

terminal.

The

ALC

voltage

is

detected

by

L121,

and

the

antenna

current

is

detected

by

L123.

For

bandwidth

information,

the

3-bit

information

items

(FL1

through

FL3)

sent

from

the

TX-RX

unit

are

converted

to

7

bits

by

decoder

IC101.

Q107

through

Q113

turn

on

and

relays

K101

through

K114

are

changed

over

for

bandwidth

selection.

The

bandwidth

informa-

tion

can

be

checked

by

checking

that

test

points

LPF1

through

LPF7

are

high

(5

V).

The

band

select

relay

can

also

be

checked

by

checking

that

LPF1B

through

LPF7B

are

5

V.

The

table

6

outlines

the

bandwidth

informa-

tion.

Transmission

and

reception

can

be

checked

when

test

points

TX

and

RX

are

5

V.

FL1/FL2|/FL3;

LPF

NO.

|

Frequency

(MHz)

H

|

HH

1

1.6050~2,9999

L

|

H

|

H

2

3.0000~4.9999

H

|

L

|

H

3

5.0000~6.9999

L

jb

|H

4

7.0000~8.9999

H}|Hy]L

5

9.0000~13.9999

Lj}

HL

6

14,0000~17.9999

Hi

LIL

7

18.0000~27,9999

Table

6

Bandwidth

information

ANT

Ql

Q2.3

Q4.5

2SC197!

28C3133

28C2879

(0,Y)

KIS

PRE

a

ORIVE

FINAL

LPF

ont

P

>

a

8

zs

96

-

La

wy,

PA

vee

BIAS

—

LPF7

=

4

a

8T

a

IC1O}

FSB

7

DECODE

—_—

FLi-3

Fig.

16

Transmitting

circuit

configuration

¢

ALC

voltage

detector

and

antenna

current

detector

circuits

The

ALC

voltage

is

detected

by

L121.

Forward

waves

are

detected

by

D102,

converted

to

an

AC

voltage,

then

sent

to

the

TX-RX

unit.

The

voltage

is

ap-

proximately

10

V

in

the

low-

to

high-band

range

with

respect

to

the

47

kQ

load

of

R112.

Reflected

waves

are

detected

by

D101

and

sent

to

the

TX-RX

unit.

The

reflected

waves

are

adjusted

by

TC101

so

that

the

VSR

voltage

is

minimum

(approximately

0.5

V)

when

a

4

MHz

frequency

is

output

at

110

W.

For

antenna

current

detection,

the

voltage

detected

by

L123

is

detected

by

D103

and

fed

to

the

TX-RX

unit.

The

voltage

is

approximately

6

V

in

the

low-

to

high-

band

range

with

respect

to

the

47

kQ

load.

ANT

OANT

Fig.

17

ALC

voltage

and

antenna

current

detection

Kenwood TRC-70 User manual

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