Lime Microsystems LMS7002MR3 Use and care manual

Lime Microsystems Limited
Surrey Tech Centre
Occam Road
The Surrey Research Park
Guildford, Surrey GU2 7YG
United Kingdom
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e-mail: [email protected]
LMS7002M –Multi-Band, Multi-Standard MIMO
RF Transceiver IC
- Programming and Calibration Guide -
Chip version:
LMS7002M
Mask revision:
01
Document version:
3.01
Document revision:
4

1
Contents
1. Serial Port Interface ............................................................................................................ 3
1.1 Description ................................................................................................................. 3
2. LMS7002Mr3 Memory Map Description.......................................................................... 5
2.1 LMS7002Mr3 Memory Map...................................................................................... 5
2.2 General Control, LimeLightTM and IO Cell Configuration Memory ......................... 8
2.3 NCO Configuration Memory ................................................................................... 17
2.4 TxTSP(A/B) Configuration Memory ....................................................................... 20
2.5 RxTSP(A/B) Configuration Memory....................................................................... 23
2.6 RX/TX GFIR1/GFIR2 Coefficient Memory............................................................ 26
2.7 RX/TX GFIR3 Coefficient Memory ........................................................................ 27
2.8 RFE(1, 2) Configuration Memory............................................................................ 28
2.9 RBB(1, 2) Configuration Memory ........................................................................... 32
2.10 TRF(1, 2) Configuration Memory............................................................................ 35
2.11 TBB(1, 2) Configuration Memory ........................................................................... 37
2.12 TRX Gain Configuration Memory........................................................................... 39
2.13 AFE Configuration Memory .................................................................................... 41
2.14 BIAS Configuration Memory................................................................................... 42
2.15 SXR, SXT Configuration Memory .......................................................................... 43
2.16 CGEN Configuration Memory................................................................................. 47
2.17 XBUF Configuration Memory ................................................................................. 50
2.18 LDO Configuration Memory ................................................................................... 51
2.19 EN_DIR Configuration Memory ............................................................................. 60
2.20 SXR, SXT and CGEN BIST Configuration Memory .............................................. 61
2.21 CDS Configuration Memory.................................................................................... 62
2.22 mSPI Configuration Memory................................................................................... 64
2.23 DC Calibration Configuration Memory ................................................................... 65
2.24 RSSI, PDET and TEMP measurement Configuration Memory .............................. 70
2.25 Analog RSSI Calibration Configuration Memory ................................................... 72
3. SPI Procedures................................................................................................................... 73
A1.1 SPI READ/WRITE Pseudo Code ............................................................................ 73
4. Control Block Diagrams ................................................................................................... 75
A2.1 RFE Control Diagrams............................................................................................. 76
A2.2 RBB Control Diagrams ............................................................................................ 78
A2.3 TRF Control Diagrams............................................................................................. 80
A2.4 TBB Control Diagrams ............................................................................................ 82
A2.5 AFE Control Diagram .............................................................................................. 84
A2.6 BIAS Control Diagram............................................................................................. 85
A2.7 SXR and SXT Control Diagrams ............................................................................. 86
A2.8 CGEN Control Diagram........................................................................................... 88
A2.9 XBUF Control Diagram ........................................................................................... 89
A2.10 LDOs Control Diagram........................................................................................ 90
A2.11 CDS Control Diagram.......................................................................................... 91
A2.12 IO Cell Control Diagram...................................................................................... 91
A2.13 TxTSP(A/B) Control Diagram ............................................................................. 92
A2.14 RxTSP(A/B) Control Diagram............................................................................. 93
A2.15 SXR, SXT and CGEN BIST Control Diagram .................................................... 94

2
A2.16 TxTSP(A/B) BIST Control Diagram ................................................................... 95
A2.17 RxTSP(A/B) BIST Control Diagram ................................................................... 95
A2.18 LimeLightTM Control Diagram............................................................................. 96
A2.19 DC offset correction Control Diagram................................................................. 97
A2.20 Measurement block Control Diagram .................................................................. 98
5. Calibration algorithms ...................................................................................................... 99
A3.1 VCO coarse tuning ................................................................................................... 99
A3.2 Main resistor (bias) calibration .............................................................................. 102
A3.3 RBB calibration...................................................................................................... 104
A3.3.1 RBB Low Band Calibration ........................................................................... 104
A3.3.2 RBB High band Calibration ........................................................................... 106
A3.4 Nested algorithms................................................................................................... 107
A3.4.1 Algorithm A ................................................................................................... 107
A3.4.2 Algorithm B.................................................................................................... 107
A3.4.3 Algorithm F .................................................................................................... 109
A3.5 TBB calibration ...................................................................................................... 111
A3.6 TBB Low Band Calibration ................................................................................... 111
A3.7 TBB High Band Calibration................................................................................... 114
A3.8 Nested algorithms................................................................................................... 115
A3.8.1 Algorithm A ................................................................................................... 115
A3.8.2 Algorithm B.................................................................................................... 115
A3.8.3 Algorithm C.................................................................................................... 115
A3.8.4 Algorithm D ................................................................................................... 117
A3.8.5 Algorithm E.................................................................................................... 117

1
Revision History
Version 31r00
Released: 23 Jan, 2017
Initial version. Build based on LMS7002M Programming and Calibration Guide v2.24.
New register HBD_DLY[2:0] added (address 0x404[15:13]).
Table 1 updated.
Chapters 2.24 and 2.25 added.
New register CMIX_GAIN[2] added (address 0x40C[12]).
Description of register CMIX_GAIN[1:0] changed (address 0x40C[15:14]).
New register CMIX_GAIN[2] added (address 0x208[12]).
Description of register CMIX_GAIN[1:0] changed (address 0x208[15:14]).
RESRV_CGN[3:1] changed to RESRV_CGN[2:1] (address 0x008D[2:0]).
New register CMPLO_CTRL_CGEN added (address 0x008B[14]).
Default value of ICT_VCO_CGEN[4:0] register (address 0x008B[13:9]) changed to 15.
New register ISINK_SPIBUFF[2:0] added (address 0x00A6[15:13]).
New register R5_LPF_BYP_TBB_(1, 2) added (address 0x010B[0]).
New register RZ_CTRL_(SXR, SXT)[1:0] added (address 0x0122[15:14]).
New register CMPLO_CTRL_(SXR, SXT) added (address 0x0122[13]).
Chapter 1.1 updated.
New register LML2_TRXIQPULSE added (address 0x0022[15]).
New register LML2_SISODDR added (address 0x0022[14]).
New register LML1_TRXIQPULSE added (address 0x0022[13]).
New register LML1_SISODDR added (address 0x0022[12]).
Description of registers at addresses 0x0024, 0x0027 updated.
Register name LML1_TX_PST changed to LML1_BB2RF_PST, description updated
(address 0x0025[12:8]).
Register name LML1_TX_PRE changed to LML1_BB2RF_PRE, description updated
(address 0x0025[4:0]).
Register name LML1_RX_PST changed to LML1_RF2BB_PST, description updated
(address 0x0026[12:8]).
Register name LML1_RX_PRE changed to LML1_RF2BB_PRE, description updated
(address 0x0026[4:0]).
Register name LML2_TX_PST changed to LML2_BB2RF_PST, description updated
(address 0x0028[12:8]).
Register name LML2_TX_PRE changed to LML2_BB2RF_PRE, description updated
(address 0x0028[4:0]).
Register name LML2_RX_PST changed to LML2_RF2BB_PST, description updated
(address 0x0029[12:8]).
Register name LML2_RX_PRE changed to LML2_RF2BB_PRE, description updated
(address 0x0029[4:0]).
Register name LML_FIDM2 changed to LML2_FIDM (address 0x0023[5]).
Register name LML_TXNRXIQ2 changed to LML2_RXNTXIQ, description updated
(address 0x0023[4]).
Register name LML_MODE2 changed to LML2_MODE (address 0x0023[3]).
Register name LML_FIDM1 changed to LML1_FIDM (address 0x0023[2]).
Register name LML_TXNRXIQ1 changed to LML2_RXNTXIQ, description updated
(address 0x0023[1]).
Register name LML_MODE1 changed to LML1_MODE (address 0x0023[0]).

2
LimeLight Control Diagram updated.
New register MCLK2_INV added (address 0x002B[9]).
New register MCLK1_INV added (address 0x002B[8]).
Description of registers at addresses 0x002C updated.
New register FCLK2_DLY[1:0] added (address 0x002A[15:14]).
New register FCLK1_DLY[1:0] added (address 0x002A[13:12]).
Section 1.1 updated (few typo errors fixed).
Figure 4 updated –SXT and SXR added.
Description of registers GFIR3_L (addresses 0x0207[10:8] and 0x0407[10:8]) updated –error
in the formula fixed.
New register RSSI_MODE[1:0] added (address 0x040A[15:14]).
New register CAPSEL_ADC[12] added (address 0x0400[12]).
Description of registers CAPD[31:0] (addresses 0x040E and 0x40F) and CAPSEL[1:0]
(address 0x0400[14:13]) updated.
New register DCLOOP_BYP added (address 0x040C[8]).
Version 31r01
Released: 6 Mar, 2017
Register DCLOOP_BYP (address 0x040C[8]) renamed to DCLOOP_STOP, description
changed.
Version 31r02
Released: 27 Mar, 2017
New register TRX_GAIN_SRC added (address 0x0081[15]).
New chapter 2.12 with new registers at addresses 0x0125 and 0x0126 added.
MASK register default value updated.
Version 31r03
Released: 03 Aprl, 2017
Figure 19 updated (pin naming corrected to match the datasheet pin naming)
Version 31r04
Released: 24 Apr, 2017
Updated 2.23, 2.24 and 2.25 section register description. Some of registers were separated
into individual register descriptions;
Various minor register description updates and fixed;
Updated Figure 5, Figure 6, Figure 11, Figure 12, Figure 15, Figure 16, Figure 17 and Figure
19 according to MASK=1 features.
Added sections A2.19 and A2.20.
Version 31r05
Released: 19 Jul, 2017
Updated Figure 19: Digital Padring pad names corrected, VDD12_AFE renamed to
VDD_AFE;

3
1
1
Serial Port Interface
1.1 Description
The functionality of LMS7002Mr3 transceiver is fully controlled by a set of internal registers
which can be accessed through a serial SPI port interface. Both write and read operations are
supported. The serial SPI port can be configured to run in 3 or 4 wire mode with the following
pins used:
SEN SPI serial port enable, active low, output from master;
SCLK SPI serial clock, output from master;
SDIO SPI serial data in/out (Master Output Slave Input (MOSI) / Master
Input Slave Output (MISO)) in 3 wire mode, serial data input (MOSI) in 4 wire mode;
SDO SPI serial data out (MISO) in 4 wire mode, don’t care in 3 wire mode.
SPI serial port key features:
Operating as slave;
Operating in SPI Mode 0: data is captured on the clock's rising edge, while data is
shifted on the clock's falling edge (i.e. clock polarity CPOL = 0 and clock phase
CPHA = 0);
32 serial clock cycles are required to complete write operation;
32 serial clock cycles are required to complete read operation;
Multiple write/read operations are possible without toggling serial enable signal.
All configuration registers are 16-bit wide. Write/read sequence consists of 16-bit instruction
followed by 16-bit data to write or read. MSB of the instruction bit stream is used as SPI
command where CMD = 1 for write and CMD = 0 for read. Next 4 bits are reserved
(Reserved[3:0]) and must be zeroes. Next 5 bits represent block address (Maddress[4:0]) since
LMS7002Mr3 configuration registers are divided into logical blocks as shown in
Table 1. Remaining 6 bits of the instruction are used to address particular registers
(Reg[5:0]) within the block as described in Section 2. Maddress and Reg compiles global 11-

4
bit register address when concatenated ((Maddress << 6) | Reg). Use global address values for
particular register from the tables provided in Section 2.
Write/read cycle waveforms are shown in Figure 1, Figure 2 and Figure 3. Note that
write operation is the same for both 3-wire and 4-wire modes. Although not shown in the
figures, multiple byte write/read is possible by repeating instruction/data sequence while
keeping SEN low.
SCLK Don’t care
SEN
SDIO Don’t care A141 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Write instruction Data
Don’t care
Don’t care
tES tDS tDH tEH
Figure 1 SPI write cycle, 3-wire and 4-wire modes
SCLK Don’t care
SEN
SDIO Don’t care A140 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Read instruction
Don’t care
Don’t care
tES tDS tDH tEH
SDO Don’t care
Output Data
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Don’t care
tOD
Figure 2 SPI read cycle, 4-wire mode (default)
SCLK Don’t care
SEN
SDIO Don’t care A140 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Read instruction
Don’t care
tES tDS tDH tEH
Output Data
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Don’t care
tOD
Figure 3 SPI read cycle, 3-wire mode

5
2
2
LMS7002Mr3 Memory Map Description
2.1 LMS7002Mr3 Memory Map
All the LMS7002Mr3 configuration space is accessible via serial SPI interface. All the
configuration space is divided to logical block types:
Other
Top
TRX
TX
RX
LMS7002Mr3 chip is MIMO, hence it have two channels called A and B. So, some
analogue/digital modules appears in MIMO channel A as well as B (from TRX, TX and RX
blocks). The rest of moduleMr3s (from Other and Top logical block types) are controlled only
from one memory block. All the logical blocks are summarized in
Table 1.
To save the addressing space and speed-up write operation the following trick is used
for the TRX, TX and RX logical block types. There is a register called MAC[1:0] (address of
this register is 0x0020[1:0]) which selects MIMO channel A or/and B. MIMO channel select
logic depends on MAC[1:0] register as described below (see Figure 1 for reference):
11 –SPI write operation possible only. The same data are written to the A and B
MIMO channels at the same time. Note, that read operation will corrupt read data
when MAC[1:0] is set to "11".
01 –SPI read/write operation possible. Data may be written to or read from the MIMO
channel A only.
10 –SPI read/write operation possible. Data may be written to or read from the MIMO
channel B only.

6
Using the MAC register simplifies programming for MIMO. As an example, the
addresses of registers controlling TBBA and TBBB are the same, but the individual A or B
channels are identified using the MAC[1:0] register.
Let us consider the write operation to the G_TIA_RFE_A[1:0] register. This register
controls the RFE module within MIMO channel A. To write to the G_TIA_RFE_A[1:0]
register, we have to set MAC[1:0] to the "01". If we set MAC[1:0] to the "11" then the same
value will be written to the registers G_TIA_RFE_A[1:0] and G_TIA_RFE_B[1:0] at the
same time (i.e. only one write operation is required, hence time saved). Similarly, if we want
to write to the G_TIA_RFE_B[1:0] register only, we have to set MAC[1:0] to "10".
The special case is frequency synthesizers SXR and SXT. Register addresses are the
same for SXR and SXT. To control SXT we have to set MAC[1:0] to the "10" and MAC[1:0]
to the "01" for SXR.
Modules from the Top and Other logical blocks (see Table 1) are not controlled by the
MAC[1:0] register.
TRXA
Block
TXA
Block
RXA
Block
TRXB
Block
TXB
Block
RXB
Block
Top
Block
Other
Block
SPI Bus
MAC[0]
MAC[1]
MIMO channel A
control enable
MIMO channel B
control enable
SXR
SXT
Figure 4 Access logic of configuration modules
The memory mapping is shown in Table 1. There are five basic logical blocks. These
are:
a) Other, controlling the microcontroller and LimeLightTM interface;
b) Top, controlling the top level bias, clock synthesizers, buffers, LDOs and BIST;
c) TRX, controlling the Transmit and Receive RF functions;
d) TX, controlling the transmit digital functions;
e) RX, controlling the receive digital functions.