Linear Technology LTC6804-1 User manual

LTC6804-1/LTC6804-2
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Typical applicaTion
FeaTures DescripTion
Multicell Battery Monitors
The LTC
®
6804 is a 3rd generation multicell battery stack
monitor that measures up to 12 series connected battery
cellswithatotalmeasurementerroroflessthan1.2mV.The
cell measurement range of 0V to 5V makes the LTC6804
suitable for most battery chemistries. All 12 cell voltages
can be captured in 290µs, and lower data acquisition rates
can be selected for high noise reduction.
Multiple LTC6804 devices can be connected in series,
permittingsimultaneouscellmonitoringoflong, highvolt-
age battery strings. Each LTC6804 has an isoSPI interface
for high speed, RF-immune, local area communications.
Using the LTC6804-1, multiple devices are connected in
a daisy-chain with one host processor connection for all
devices. Using the LTC6804-2, multiple devices are con-
nected in parallel to the host processor, with each device
individually addressed.
Additionalfeaturesincludepassivebalancingfor each cell,
an onboard 5V regulator, and 5 general purpose I/O lines.
In sleep mode, current consumption is reduced to 4µA.
The LTC6804 can be powered directly from the battery,
or from an isolated supply.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered and isoSPI is a
trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Protected by U.S. patents, including 8908799, 9182428, 9270133.
Total Measurement Error
vs Temperature of 5 Typical Units
applicaTions
n Measures Up to 12 Battery Cells in Series
n Stackable Architecture Supports 100s of Cells
n Built-In isoSPI™ Interface:
1Mbps Isolated Serial Communications
Uses a Single Twisted Pair, Up to 100 Meters
Low EMI Susceptibility and Emissions
n 1.2mV Maximum Total Measurement Error
n 290µs to Measure All Cells in a System
n Synchronized Voltage and Current Measurement
n 16-Bit Delta-Sigma ADC with Frequency Program-
mable 3rd Order Noise Filter
n Engineered for ISO26262 Compliant Systems
n Passive Cell Balancing with Programmable Timer
n 5 General Purpose Digital I/O or Analog Inputs:
Temperature or other Sensor Inputs
Configurable as an I2C or SPI Master
n 4μA Sleep Mode Supply Current
n 48-Lead SSOP Package
n Electric and Hybrid Electric Vehicles
n Backup Battery Systems
n Grid Energy Storage
n High Power Portable Equipment
LTC6820
LTC6804-1
MPU
IP
•
•
•
•
• • • •
SPI
IM
IPA
IMA
680412 TA01a
IPB
IMB
LTC6804-1
IMA
IPA
ILP
IPB
IMB
LTC6804-1
IMA
IPB
IMB
IPA
12S1P
+
+
+
+
+
+
TEMPERATURE (°C)
–50
MEASUREMENT ERROR (mV)
1.5
25
680412 TA01b
0
–1.0
–25 0 50
–1.5
–2.0
2.0
1.0
0.5
–0.5
75 100
125
CELL VOLTAGE = 3.3V
5 TYPICAL UNITS

LTC6804-1/LTC6804-2
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Table oF conTenTs
Features..................................................... 1
Applications ................................................ 1
Typical Application ........................................ 1
Description.................................................. 1
Absolute Maximum Ratings.............................. 3
Pin Configuration .......................................... 3
Order Information.......................................... 4
Electrical Characteristics ................................. 4
Pin Functions .............................................. 17
Block Diagram............................................. 18
Operation................................................... 20
State Diagram.........................................................20
LTC6804 Core State Descriptions...........................20
isoSPI State Descriptions .......................................21
Power Consumption ...............................................21
ADC Operation........................................................21
Data Acquisition System Diagnostics .....................26
Watchdog and Software Discharge Timer ..............30
I2C/SPI Master on LTC6804 Using GPIOS ..............31
Serial Interface Overview........................................35
4-Wire Serial Peripheral Interface (SPI)
Physical Layer ........................................................36
2-Wire Isolated Interface (isoSPI) Physical Layer...36
Data Link Layer.......................................................44
Network Layer ........................................................44
Programming Examples .........................................54
Simple Linear Regulator .........................................58
Improved Regulator Power Efficiency.....................58
Fully Isolated Power................................................59
Reading External Temperature Probes....................59
Expanding the Number of Auxiliary
Measurements........................................................60
Internal Protection Features....................................60
Filtering of Cell and GPIO Inputs.............................60
Cell Balancing with Internal Mosfets.......................62
Cell Balancing with External MOSFETS...................62
Discharge Control During Cell Measurements ........62
Power Dissipation and Thermal Shutdown .............63
Method to Verify Balancing Circuitry ......................63
Current Measurement with a Hall Effect Sensor .....66
Current Measurement with a Shunt Resistor..........66
Using the LTC6804 with Less Than 12 Cells...........67
Package Description ..................................... 76
Revision History .......................................... 77
Typical Application ....................................... 78
Related Parts .............................................. 78

LTC6804-1/LTC6804-2
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absoluTe MaxiMuM raTings
Total Supply Voltage V+to V–....................................75V
Input Voltage (Relative to V–)
C0......................................................... –0.3V to 0.3V
C12 ........................................................ –0.3V to 75V
C(n).....................................–0.3V to MIN (8 •n, 75V)
S(n).....................................–0.3V to MIN (8 •n, 75V)
IPA, IMA, IPB, IMB ....................–0.3V to VREG + 0.3V
DRIVE Pin................................................ –0.3V to 7V
All Other Pins........................................... –0.3V to 6V
Voltage Between Inputs
V+to C12............................................................–5.5V
C(n) to C(n – 1) ........................................ –0.3V to 8V
S(n) to C(n – 1) ........................................ –0.3V to 8V
C12 to C8............................................... –0.3V to 25V
(Note 1)
pin conFiguraTion
C8 to C4................................................. –0.3V to 25V
C4 to C0................................................. –0.3V to 25V
Current In/Out of Pins
All Pins Except VREG, IPA, IMA, IPB, IMB, S(n)..10mA
IPA, IMA, IPB, IMB.............................................30mA
Operating Temperature Range
LTC6804I.............................................–40°C to 85°C
LTC6804H.......................................... –40°C to 125°C
Specified Temperature Range
LTC6804I.............................................–40°C to 85°C
LTC6804H.......................................... –40°C to 125°C
Junction Temperature ........................................... 150°C
Storage Temperature.............................. –65°C to 150°C
Lead Temperature (Soldering, 10sec)....................300°C
LTC6804-1 LTC6804-2
1
2
3
4
5
6
7
8
9
10
11
12
13
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TOP VIEW
G PACKAGE
48-LEAD PLASTIC SSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V+
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
S7
C6
S6
C5
S5
C4
S4
C3
S3
C2
S2
C1
IPB
IMB
ICMP
IBIAS
SDO (NC)*
SDI (NC)*
SCK (IPA)*
CSB (IMA)*
ISOMD
WDT
DRIVE
VREG
SWTEN
VREF1
VREF2
GPIO5
GPIO4
V–
V–**
GPIO3
GPIO2
GPIO1
C0
S1
TJMAX = 150°C, θJA = 55°C/W
*THE FUNCTION OF THESE PINS DEPENDS ON THE CONNECTION OF ISOMD
ISOMD TIED TO V–: CSB, SCK, SDI, SDO
ISOMD TIED TO VREG: IMA, IPA, NC, NC
**THIS PIN MUST BE CONNECTED TO V–
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
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TOP VIEW
G PACKAGE
48-LEAD PLASTIC SSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V+
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
S7
C6
S6
C5
S5
C4
S4
C3
S3
C2
S2
C1
A3
A2
A1
A0
SDO (IBIAS)*
SDI (ICMP)*
SCK (IPA)*
CSB (IMA)*
ISOMD
WDT
DRIVE
VREG
SWTEN
VREF1
VREF2
GPIO5
GPIO4
V–
V–**
GPIO3
GPIO2
GPIO1
C0
S1
TJMAX = 150°C, θJA = 55°C/W
*THE FUNCTION OF THESE PINS DEPENDS ON THE CONNECTION OF ISOMD
ISOMD TIED TO V–: CSB, SCK, SDI, SDO
ISOMD TIED TO VREG: IMA, IPA, ICMP, IBIAS
**THIS PIN MUST BE CONNECTED TO V–

LTC6804-1/LTC6804-2
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orDer inForMaTion
elecTrical characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ADC DC Specifications
Measurement Resolution l0.1 mV/bit
ADC Offset Voltage (Note 2) l0.1 mV
ADC Gain Error (Note 2)
l
0.01
0.02 % %
Total Measurement Error (TME) in
Normal Mode C(n) to C(n – 1), GPIO(n) to V–= 0 ±0.2 mV
C(n) to C(n – 1) = 2.0 ±0.1 ±0.8 mV
C(n) to C(n – 1), GPIO(n) to V–= 2.0 l±1.4 mV
C(n) to C(n – 1) = 3.3 ±0.2 ±1.2 mV
C(n) to C(n – 1), GPIO(n) to V–= 3.3 l±2.2 mV
C(n) to C(n – 1) = 4.2 ±0.3 ±1.6 mV
C(n) to C(n – 1), GPIO(n) to V–= 4.2 l±2.8 mV
C(n) to C(n – 1), GPIO(n) to V–= 5.0 ±1 mV
Sum of Cells, V(CO) = V–l±0.2 ±0.75 %
Internal Temperature, T = Maximum
Specified Temperature ±5 °C
VREG Pin l±0.1 ±0.25 %
VREF2 Pin l±0.02 ±0.1 %
Digital Supply Voltage VREGD l±0.1 ±1 %
The ldenotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C. The test conditions are V+= 39.6V, VREG = 5.0V unless otherwise noted.
TUBE TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6804IG-1#PBF LTC6804IG-1#TRPBF LTC6804G-1 48-Lead Plastic SSOP –40°C to 85°C
LTC6804HG-1#PBF LTC6804HG-1#TRPBF LTC6804G-1 48-Lead Plastic SSOP –40°C to 125°C
LTC6804IG-2#PBF LTC6804IG-2#TRPBF LTC6804G-2 48-Lead Plastic SSOP –40°C to 85°C
LTC6804HG-2#PBF LTC6804HG-2#TRPBF LTC6804G-2 48-Lead Plastic SSOP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Parts ending with PBF are RoHS and WEEE compliant.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
http://www.linear.com/product/LTC6804-1#orderinfo

LTC6804-1/LTC6804-2
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elecTrical characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Total Measurement Error (TME) in
Filtered Mode C(n) to C(n – 1), GPIO(n) to V–= 0 ±0.1 mV
C(n) to C(n – 1) = 2.0 ±0.1 ±0.8 mV
C(n) to C(n – 1), GPIO(n) to V–= 2.0 l±1.4 mV
C(n) to C(n – 1) = 3.3 ±0.2 ±1.2 mV
C(n) to C(n – 1), GPIO(n) to V–= 3.3 l±2.2 mV
C(n) to C(n – 1) = 4.2 ±0.3 ±1.6 mV
C(n) to C(n – 1), GPIO(n) to V–= 4.2 l±2.8 mV
C(n) to C(n – 1), GPIO(n) to V–= 5.0 ±1 mV
Sum of Cells, V(CO) = V–l±0.2 ±0.75 %
Internal Temperature, T = Maximum
Specified Temperature ±5 °C
VREG Pin l±0.1 ±0.25 %
VREF2 Pin l±0.02 ±0.1 %
Digital Supply Voltage VREGD l±0.1 ±1 %
Total Measurement Error (TME) in
Fast Mode C(n) to C(n – 1), GPIO(n) to V–= 0 ±2 mV
C(n) to C(n – 1), GPIO(n) to V–= 2.0 l±4 mV
C(n) to C(n – 1), GPIO(n) to V–= 3.3 l±4.7 mV
C(n) to C(n – 1), GPIO(n) to V–= 4.2 l±8.3 mV
C(n) to C(n – 1), GPIO(n) to V–= 5.0 ±10 mV
Sum of Cells, V(CO) = V–l±0.3 ±1 %
Internal Temperature, T = Maximum
Specified Temperature ±5 °C
VREG Pin l±0.3 ±1 %
VREF2 Pin l±0.1 ±0.25 %
Digital Supply Voltage VREGD l±0.2 ±2 %
Input Range C(n), n = 1 to 12 lC(n – 1) C(n –1) + 5 V
C0 l0
GPIO(n), n = 1 to 5 l0 5 V
ILInput Leakage Current When Inputs
Are Not Being Measured C(n), n = 0 to 12 l10 ±250 nA
GPIO(n), n = 1 to 5 l10 ±250 nA
Input Current When Inputs Are
Being Measured C(n), n = 0 to 12 ±2 µA
GPIO(n), n = 1 to 5 ±2 µA
Input Current During Open Wire
Detection
l70 100 130 µA
The ldenotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C. The test conditions are V+= 39.6V, VREG = 5.0V unless otherwise noted.

LTC6804-1/LTC6804-2
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elecTrical characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Voltage Reference Specifications
VREF1 1st Reference Voltage VREF1 Pin, No Load l3.1 3.2 3.3 V
1st Reference Voltage TC VREF1 Pin, No Load 3 ppm/°C
1st Reference Voltage Hysteresis VREF1 Pin, No Load 20 ppm
1st Reference Long Term Drift VREF1 Pin, No Load 20 ppm/√kHr
VREF2 2nd Reference Voltage VREF2 Pin, No Load l2.990 3 3.010 V
VREF2 Pin, 5k Load to V–l2.988 3 3.012 V
2nd Reference Voltage TC VREF2 Pin, No Load 10 ppm/°C
2nd Reference Voltage Hysteresis VREF2 Pin, No Load 100 ppm
2nd Reference Long Term Drift VREF2 Pin, No Load 60 ppm/√kHr
General DC Specifications
IVP V+Supply Current
(See Figure 1: LTC6804 Operation
State Diagram)
State: Core = SLEEP
, isoSPI = IDLE VREG = 0V 3.8 6 µA
VREG = 0V l3.8 10 µA
VREG = 5V 1.6 3 µA
VREG = 5V l1.6 5 µA
State: Core = STANDBY 18 32 50 µA
l10 32 60 µA
State: Core = REFUP or MEASURE 0.4 0.55 0.7 mA
l0.375 0.55 0.725 mA
IREG(CORE) VREG Supply Current
(See Figure 1: LTC6804 Operation
State diagram)
State: Core = SLEEP, isoSPI = IDLE VREG = 5V 2.2 4 µA
VREG = 5V l2.2 6 µA
State: Core = STANDBY 10 35 60 µA
l6 35 65 µA
State: Core = REFUP 0.2 0.45 0.7 mA
l0.15 0.45 0.75 mA
State: Core = MEASURE 10.8 11.5 12.2 mA
l10.7 11.5 12.3 mA
IREG(isoSPI) Additional VREG Supply Current if
isoSPI in READY/ACTIVE States
Note: ACTIVE State Current
Assumes tCLK = 1µs, (Note3)
LTC6804-2: ISOMD = 1,
RB1 + RB2 = 2k READY l3.9 4.8 5.8 mA
ACTIVE l5.1 6.1 7.3 mA
LTC6804-1: ISOMD = 0,
RB1 + RB2 = 2k READY l3.7 4.6 5.6 mA
ACTIVE l5.7 6.8 8.1 mA
LTC6804-1: ISOMD = 1,
RB1 + RB2 = 2k READY l6.5 7.8 9.5 mA
ACTIVE l10.2 11.3 13.3 mA
LTC6804-2: ISOMD = 1,
RB1 + RB2 = 20k READY l1.3 2.1 3 mA
ACTIVE l1.6 2.5 3.5 mA
LTC6804-1: ISOMD = 0,
RB1 + RB2 = 20k READY l1.1 1.9 2.8 mA
ACTIVE l1.5 2.3 3.3 mA
LTC6804-1: ISOMD = 1,
RB1 + RB2 = 20k READY l2.1 3.3 4.9 mA
ACTIVE l2.7 4.1 5.8 mA
The ldenotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C. The test conditions are V+= 39.6V, VREG = 5.0V unless otherwise noted.

LTC6804-1/LTC6804-2
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elecTrical characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V+Supply Voltage TME Specifications Met (Note 6) l11 40 55 V
VREG VREG Supply Voltage TME Supply Rejection < 1mV/V l4.5 5 5.5 V
DRIVE output voltage Sourcing 1µA
l
5.4
5.2 5.6 5.6 5.8 6.0 V V
Sourcing 500µA l5.1 5.6 6.1 V
VREGD Digital Supply Voltage l2.7 3.0 3.6 V
Discharge Switch ON Resistance VCELL = 3.6V l10 25 Ω
Thermal Shutdown Temperature 150 °C
VOL(WDT) Watchdog Timer Pin Low WDT Pin Sinking 4mA l0.4 V
VOL(GPIO) General Purpose I/O Pin Low GPIO Pin Sinking 4mA (Used as Digital Output) l0.4 V
ADC Timing Specifications
tCYCLE
(Figure3) Measurement + Calibration Cycle Time When Starting from the
REFUP State in Normal Mode
Measure 12 Cells l2120 2335 2480 µs
Measure 2 Cells l365 405 430 µs
Measure 12 Cells and 2 GPIO Inputs l2845 3133 3325 µs
Measurement + Calibration Cycle
Time When Starting from the
REFUP State in Filtered Mode
Measure 12 Cells l183 201.3 213.5 ms
Measure 2 Cells l30.54 33.6 35.64 ms
Measure 12 Cells and 2 GPIO Inputs l244 268.4 284.7 ms
Measurement + Calibration Cycle
Time When Starting from the
REFUP State in Fast Mode
Measure 12 Cells l1010 1113 1185 µs
Measure 2 Cells l180 201 215 µs
Measure 12 Cells and 2 GPIO Inputs l1420 1564 1660 µs
tSKEW1
(Figure 6) Skew Time. The Time Difference between C12 and GPIO2
Measurements, Command =
ADCVAX
Fast Mode l189 208 221 µs
Normal Mode l493 543 576 µs
tSKEW2
(Figure 3) Skew Time. The Time
Difference between C12 and C0
Measurements, Command = ADCV
Fast Mode l211 233 248 µs
Normal Mode l609 670 711 µs
tWAKE Regulator Start-Up Time VREG Generated from Drive Pin (Figure 28) l100 300 µs
tSLEEP Watchdog or Software Discharge
Timer SWTEN Pin = 0 or DCTO[3:0] = 0000 l1.8 2 2.2 sec
SWTEN Pin = 1 and DCTO[3:0] ≠ 0000 0.5 120 min
tREFUP
(Figure1,
Figures 3 to 7)
Reference Wake-Up Time State: Core = STANDBY l2.7 3.5 4.4 ms
State: Core = REFUP l0 ms
fSADC Clock Frequency l3.0 3.3 3.5 MHz
SPI Interface DC Specifications
VIH(SPI) SPI Pin Digital Input Voltage High Pins CSB, SCK, SDI l2.3 V
VIL(SPI) SPI Pin Digital Input Voltage Low Pins CSB, SCK, SDI l0.8 V
VIH(CFG) Configuration Pin Digital
Input Voltage High Pins ISOMD, SWTEN, GPIO1 to GPIO5, A0 to A3 l2.7 V
VIL(CFG) Configuration Pin Digital
Input Voltage Low Pins ISOMD, SWTEN, GPIO1 to GPIO5, A0 to A3 l1.2 V
The ldenotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C. The test conditions are V+= 39.6V, VREG = 5.0V unless otherwise noted.

LTC6804-1/LTC6804-2
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elecTrical characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ILEAK(DIG) Digital Input Current Pins CSB, SCK, SDI, ISOMD, SWTEN,
A0 to A3
l±1 µA
VOL(SDO) Digital Output Low Pin SDO Sinking 1mA l0.3 V
isoSPI DC Specifications (See Figure 16)
VBIAS Voltage on IBIAS Pin READY/ACTIVE State
IDLE State
l1.9 2.0
02.1 V V
IBIsolated Interface Bias Current RBIAS = 2k to 20k l0.1 1.0 mA
AIB Isolated Interface Current Gain VA≤ 1.6V IB= 1mA
IB= 0.1mA
l
l
18
18 20 20 22 24.5 mA/mA mA/mA
VATransmitter Pulse Amplitude VA= |VIP – VIM|l1.6 V
VICMP Threshold-Setting Voltage on ICMP
Pin VTCMP = ATCMP •VICMP l0.2 1.5 V
ILEAK(ICMP) Input Leakage Current on ICMP Pin VICMP = 0V to VREG l±1 µA
ILEAK(IP/IM) Leakage Current on IP and IM Pins IDLE State, VIP or VIM = 0V to VREG l±1 µA
ATCMP Receiver Comparator Threshold
Voltage Gain VCM = VREG/2 to VREG – 0.2V, VICMP = 0.2V to 1.5V l0.4 0.5 0.6 V/V
VCM Receiver Common Mode Bias IP/IM Not Driving (VREG – VICMP/3 – 167mV) V
RIN Receiver Input Resistance Single-Ended to IPA, IMA, IPB, IMB l27 35 43 kΩ
isoSPI Idle/Wakeup Specifications (See Figure 21)
VWAKE Differential Wake-Up Voltage tDWELL = 240ns l200 mV
tDWELL Dwell Time at VWAKE Before Wake
Detection VWAKE = 200mV l240 ns
tREADY Startup Time After Wake Detection l10 µs
tIDLE Idle Timeout Duration l4.3 5.5 6.7 ms
isoSPI Pulse Timing Specifications (See Figure 19)
t1/2PW(CS) Chip-Select Half-Pulse Width l120 150 180 ns
tINV(CS) Chip-Select Pulse Inversion Delay l200 ns
t1/2PW(D) Data Half-Pulse Width l40 50 60 ns
tINV(D) Data Pulse Inversion Delay l70 ns
SPI Timing Requirements (See Figure 15 and Figure 20)
tCLK SCK Period (Note 4) l1 µs
t1SDI Setup Time before SCK Rising
Edge
l25 ns
t2SDI Hold Time after SCK Rising
Edge
l25 ns
t3SCK Low tCLK = t3+ t4≥ 1µs l200 ns
t4SCK High tCLK = t3+ t4≥ 1µs l200 ns
t5CSB Rising Edge to CSB Falling
Edge
l0.65 µs
t6SCK Rising Edge to CSB Rising
Edge (Note 4) l0.8 µs
t7CSB Falling Edge to SCK Rising
Edge (Note 4) l1 µs
The ldenotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C. The test conditions are V+= 39.6V, VREG = 5.0V unless otherwise noted.

LTC6804-1/LTC6804-2
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elecTrical characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
isoSPI Timing Specifications (See Figure 19)
t8SCK Falling Edge to SDO Valid (Note 5) l60 ns
t9SCK Rising Edge to Short ±1
Transmit
l50 ns
t10 CSB Transition to Long ±1 Transmit l60 ns
t11 CSB Rising Edge to SDO Rising (Note 5) l200 ns
tRTN Data Return Delay l430 525 ns
tDSY(CS) Chip-Select Daisy-Chain Delay l150 200 ns
tDSY(D) Data Daisy-Chain Delay l300 360 ns
tLAG Data Daisy-Chain Lag (vs Chip-
Select)
l0 35 70 ns
t6(GOV) Data to Chip-Select Pulse Governor l0.8 1.05 µs
The ldenotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C. The test conditions are V+= 39.6V, VREG = 5.0V unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The ADC specifications are guaranteed by the Total Measurement
Error specification.
Note 3: The ACTIVE state current is calculated from DC measurements.
The ACTIVE state current is the additional average supply current into
VREG when there is continuous 1MHz communications on the isoSPI ports
with 50% data 1’s and 50% data 0’s. Slower clock rates reduce the supply
current. See Applications Information section for additional details.
Note 4: These timing specifications are dependent on the delay through
the cable, and include allowances for 50ns of delay each direction. 50ns
corresponds to 10m of CAT-5 cable (which has a velocity of propagation of
66% the speed of light). Use of longer cables would require derating these
specs by the amount of additional delay.
Note 5: These specifications do not include rise or fall time of SDO. While
fall time (typically 5ns due to the internal pull-down transistor) is not a
concern, rising-edge transition time tRISE is dependent on the pull-up
resistance and load capacitance on the SDO pin. The time constant must
be chosen such that SDO meets the setup time requirements of the MCU.
Note 6: V+needs to be greater than or equal to the highest C(n) voltage for
accurate measurements. See the graph Top Cell Measurement Error vs V+.

LTC6804-1/LTC6804-2
10
680412fc
For more information www.linear.com/LTC6804-1
Measurement Error vs Input,
Normal Mode
Measurement Error vs Input,
Filtered Mode
Measurement Error vs Input,
Fast Mode
Measurement Error
vs Temperature
Measurement Error Due to IR
Reflow
Measurement Error Long-
Term Drift
Typical perForMance characTerisTics
Measurement Noise vs Input,
Normal Mode
Measurement Noise vs Input,
Filtered Mode
Measurement Noise vs Input,
Fast Mode
TA= 25°C, unless otherwise noted.
TEMPERATURE (°C)
–50
MEASUREMENT ERROR (mV)
1.5
25
680412 G01
0
–1.0
–25 0 50
–1.5
–2.0
2.0
1.0
0.5
–0.5
75 100 125
CELL VOLTAGE = 3.3V
5 TYPICAL UNITS
CHANGE IN GAIN ERROR (ppm)
–125
NUMBER OF PARTS
20
25
30
25 50 75–50 –25 0
680412 G02
15
10
–100 –75
5
0
35 260°C, 1 CYCLE
TIME (HOURS)
0
MEASUREMENT ERROR (ppm)
30
5
25
15
20
10
0
680412 G03
30001000 2000 2500500 1500
CELL VOLTAGE = 3.3V
8 TYPICAL PARTS
INPUT (V)
0
MEASUREMENT ERROR (mV)
–0.5
0
0.5
35
680412 G04
–1.0
–1.5
–2.0 1 2 4
1.0
1.5
2.0 10 ADC MEASUREMENTS
AVERAGED AT EACH INPUT
INPUT (V)
0
MEASUREMENT ERROR (mV)
–0.5
0
0.5
35
680412 G05
–1.0
–1.5
–2.0 1 2 4
1.0
1.5
2.0
INPUT (V)
0
MEASUREMENT ERROR (mV)
2
6
10
4
680412 G06
–2
–6
0
4
8
–4
–8
–10 1235
10 ADC MEASUREMENTS
AVERAGED AT EACH INPUT
INPUT (V)
0
PEAK NOISE (mV)
0.6
0.8
1.0
4
680412 G07
0.4
0.2
0.5
0.7
0.9
0.3
0.1
01235
INPUT (V)
0
PEAK NOISE (mV)
0.6
0.8
1.0
4
680412 G08
0.4
0.2
0.5
0.7
0.9
0.3
0.1
01235
INPUT (V)
0
PEAK NOISE (mV)
6
8
10
4
680412 G09
4
2
5
7
9
3
1
0123

LTC6804-1/LTC6804-2
11
680412fc
For more information www.linear.com/LTC6804-1
Typical perForMance characTerisTics
Measurement Gain Error
Hysteresis, Hot
Measurement Gain Error
Hysteresis, Cold Noise Filter Response
Measurement Error vs VREG
Measurement Error V+PSRR
vs Frequency
Measurement Error VREG PSRR
vs Frequency
TA= 25°C, unless otherwise noted.
CHANGE IN GAIN ERROR (ppm)
–50
NUMBER OF PARTS
15
20
25 TA= 85°C TO 25°C
–20 0 30
680412 G10
10
5
0–40 –30 –10 10 20
CHANGE IN GAIN ERROR (ppm)
–40
0
NUMBER OF PARTS
5
10
15
20
–20 0 20 40
680412 G11
25
30 TA= –45°C TO 25°C
–30 –10 10 30
INPUT FREQUENCY (Hz)
10
NOISE REJECTION (dB)
0
–50
–10
–30
–20
–40
–70
–60
680412 G12
1M1k 100k100 10k
FILTERED
2kHz
3kHz
ADC MODE:
NORMAL
15kHz
FAST
VREG (V)
4.5
MEASUREMENT ERROR (mV)
0
0.5
1.0
5.3 5.4
680412 G13
–0.5
–1.0
–2.0 4.7 4.9 5.1
4.6 5.5
4.8 5.0 5.2
–1.5
2.0
1.5
VIN = 2V
VIN = 3.3V
VIN = 4.2V
FREQUENCY (Hz)
100
PSRR (dB)
–60
–50
–40
1M
680412 G14
–70
–80
–65
–55
–45
–75
–85
–90 1k 10k 100k 10M
V+DC = 39.6V
V+AC = 5VP-P
1 BIT CHANGE < –90dB
VREG GENERATED FROM
DRIVE PIN, FIGURE 28
FREQUENCY (Hz)
100
–20
–10
0
1M
68412 G15
–30
–40
1k 10k 100k 10M
–50
–60
–70
PSRR (dB)
VREG(DC) = 5V
VREG(AC) = 500mVP-P
1 BIT CHANGE < –70dB
Cell Measurement Error
vs Input RC Values
GPIO Measurement Error
vs Input RC Values Top Cell Measurement Error vs V+
INPUT RESISTOR, R (Ω)
1
CELL MEASUREMENT ERROR (mV)
0
5
10
10000
680412 G16
–5
–10
–20 10 100 1000
–15
20 NORMAL MODE CONVERSIONS
DIFFERENTIAL RC FILTER ON EVERY C PIN.
EXPECT CELL-TO-CELL AND
PART-TO-PART VARIATIONS
IN ERROR IF R > 100Ω AND/OR C > 10nF
15
C = 0
C = 10nF
C = 100nF
C = 1µF
INPUT RESISTANCE, R (Ω)
1
MEASUREMENT ERROR (mV)
2
6
10
10000
680412 G17
–2
–6
0
4
8
–4
–8
–10 10 100 1000 100000
C = 0
C = 100nF
C = 1µF
C = 10µF
TIME BETWEEN MEASUREMENTS > 3RC
V+(V)
36
–1.0
CELL 12 MEASUREMENT ERROR (mV)
–0.8
–0.4
–0.2
0
1.0
0.4
38 40
680412 G18
–0.6
0.6
0.8
0.2
42 44
C12-C11 = 3.3V
C12 = 39.6V

LTC6804-1/LTC6804-2
12
680412fc
For more information www.linear.com/LTC6804-1
Typical perForMance characTerisTics
Cell Measurement Error
vs Common Mode Voltage
Cell Measurement CMRR
vs Frequency Measurement Error vs V+
Sleep Supply Current vs V+Standby Supply Current vs V+REFUP Supply Current vs V+
TA= 25°C, unless otherwise noted.
C11 VOLTAGE (V)
0
–1.0
CELL 12 MEASUREMENT ERROR (mV)
–0.8
–0.4
–0.2
0
1.0
0.4
10 20
680412 G19
–0.6
0.6
0.8
0.2
30
C12-C11 = 3.3V
V+= 39.6V
FREQUENCY (Hz)
100
–90
REJECTION (dB)
–80
–60
–50
–40
10k 1M 10M
0
680412 G20
–70
1k 100k
–30
–20
–10
VCM(IN) = 5VP-P
NORMAL MODE CONVERSIONS
V+(V)
5
MEASUREMENT ERROR (mV)
1.5
20
680412 G21
0
–1.0
10 15 25
–1.5
–2.0
2.0
1.0
0.5
–0.5
30 35 40
MEASUREMENT ERROR OF
CELL 1 WITH 3.3V INPUT.
VREG GENERATED FROM
DRIVE PIN, FIGURE 28
V+(V)
5 15
2
SLEEP SUPPLY CURRENT (µA)
4
7
25 45 55
680412 G22
3
6
5
35 65 75
125°C
85°C
25°C
–45°C
SLEEP SUPPLY CURRENT =
V+CURRENT + VREG CURRENT
V+(V)
155
40
STANDBY SUPPLY CURRENT (µA)
50
80
25 45 55
680412 G23
70
60
35 65 75
125°C
85°C
25°C
–45°C
STANDBY SUPPLY CURRENT =
V+CURRENT + VREG CURRENT
V+(V)
155
850
REFUP SUPPLY CURRENT (µA)
1000
25 45 55
680412 G24
950
900
35 65 75
125°C
85°C
25°C
–45°C
REFUP SUPPLY CURRENT =
V+CURRENT + VREG CURRENT
Measure Mode Supply Current
vs V+Measurement Time vs Temperature
Internal Die Temperature
Measurement Error vs Temperature
V+(V)
5
MEASURE MODE SUPPLY CURRENT (mA)
12.00
12.25
12.50
35 55
680412 G25
11.75
11.50
15 25 45 65 75
11.25
11.00
125°C
85°C
25°C
–45°C
MEASURE MODE SUPPLY CURRENT =
V+CURRENT + VREG CURRENT
TEMPERATURE (°C)
–50
MEASUREMENT TIME (µs)
2420
25
680412 G26
2360
2320
–25 0 50
2300
2280
2440
2400
2380
2340
75 100 125
VREG = 5V
VREG = 4.5V
VREG = 5.5V
12 CELL NORMAL MODE TIME
SHOWN. ALL ADC MEASURE
TIMES SCALE PROPORTIONALLY
TEMPERATURE (°C)
–50
–10
TEMPERATURE MEASUREMENT ERROR (DEG)
–8
–4
–2
0
10
4
050 75 100
680412 G27
–6
6
8
2
–25 25 125
5 TYPICAL UNITS

LTC6804-1/LTC6804-2
13
680412fc
For more information www.linear.com/LTC6804-1
Typical perForMance characTerisTics
VREF2 vs Temperature VREF2 Load Regulation VREF2 V+Line Regulation
VREF2 VREG Line Regulation
VREF2 Hysteresis, Hot
VREF2 Power-Up
VREF2 Hysteresis, Cold
VREF2 Long-Term Drift
VREF2 Change Due to IR Reflow
TA= 25°C, unless otherwise noted.
TEMPERATURE (°C)
–50
VREF2 (V)
3.001
3.002
3.003
25 75
680412 G28
3.000
2.999
–25 0 50 100 125
2.998
2.997
V+= 39.6V
5 TYPICAL PARTS
IOUT (mA)
0.01
CHANGE IN VREF2 (ppm)
–600
–400
680412 G29
–800
–1000 0.1 110
0
–200
125°C
85°C
25°C
–45°C
V+= 39.6V
VREG = 5V
V+(V)
5
CHANGE IN VREF2 (ppm)
150
35
580412 G30
0
–100
15 25 45
–150
–200
200
100
50
–50
55 65 75
125°C
85°C
25°C
–45°C
VREG GENERATED FROM
DRIVE PIN, FIGURE 28
VREG (V)
4.5
–150
CHANGE IN VREF2 (ppm)
–100
–50
0
50
100
150 RL= 5k
4.75 5 5.25 5.5
680412 G31
125°C
85°C
25°C
–45°C
VREF2 (V)CSB
1.5
2.5
3.5
680412 G32
0.5
5
1.0
2.0
3.0
0
0
–5 1ms/DIV
VREF2
CSB
RL= 5k
CL= 1µF
TIME (HOURS)
0
CHANGE IN VREF2 (ppm)
0
680412 G33
–50
–100 1000 2000
500 1500 2500
50
100
–25
–75
25
75
3000
8 TYPICAL PARTS
CHANGE IN REF2 (ppm)
–125
NUMBER OF PARTS
15
20
25 TA= 85°C TO 25°C
75
680412 G34
10
5
0–75 –25 25 125 175
CHANGE IN REF2 (ppm)
–250
NUMBER OF PARTS
8
12
680412 G35
4
0–200 –150 –100 –50 0 50 100
16
6
10
2
14
TA= –45°C TO 25°C
CHANGE IN REF2 (ppm)
0
NUMBER OF PARTS
10
20
30 260°C, 1 CYCLE
5
15
25
–500 –300 –100 100
680412 G36
300–700

LTC6804-1/LTC6804-2
14
680412fc
For more information www.linear.com/LTC6804-1
Typical perForMance characTerisTics
Drive and VREG Pin Power-Up VREF1 Power-Up VREF1 vs Temperature
Internal Die Temperature
Increase vs Discharge Current
isoSPI Current (READY)
vs Temperature
isoSPI Current (READY/ACTIVE)
vs isoSPI Clock Frequency
Discharge Switch On-Resistance
vs Cell Voltage Drive Pin Load Regulation Drive Pin Line Regulation
TA= 25°C, unless otherwise noted.
CELL VOLTAGE (V)
0
DISCHARGE SWITCH ON-RESISTANCE (Ω)
5
15
20
25
50
35
12
680412 G37
10
40
45
30
34 5
125°C
85°C
25°C
–45°C
ON-RESISTANCE OF INTERNAL
DISCHARGE SWITCH MEASURED
WITH 100Ω. EXTERNAL DISCHARGE
RESISTOR BETWEEN S(n) and C(n)
ILOAD (mA)
0.01
CHANGE IN DRIVE PIN VOLTAGE (mV)
–60
–40
1
680412 G38
–80
–100 0.1
0
–20
125°C
85°C
25°C
–45°C
V+= 39.6V
V+(V)
5 15
–15
CHANGE IN DRIVE PIN VOLTAGE (mV)
–5
10
25 45 55
680412 G39
–10
5
0
35 65 75
125°C
85°C
25°C
–45°C
4
5
6
680412 G40
3
2
100µs/DIV
1
0
–1
VDRIVE AND VREG (V)
VDRIVE VREG
VREG: CL= 1µF
VREG GENERATED FROM
DRIVE PIN, FIGURE 28
VREF1 (V)CSB
1.5
2.5
3.5
680412 G41
0.5
5
–5
1.0
2.0
3.0
CSB
0
1ms/DIV
VREF1
CL= 1µF
TEMPERATURE (°C)
–50
3.145
VREF1 (V)
3.146
3.148
3.149
3.150
3.155
3.152
050 75 100
680412 G42
3.147
3.153
3.154
3.151
–25 25 125
5 TYPICAL
INTERNAL DISCHARGE CURRENT (mA PER CELL)
0
0
INCREASE IN DIE TEMPERATURE (°C)
5
15
20
25
50
35
20 40
680412 G43
10
40
45
30
60 80
12 CELLS DISCHARGING
1 CELL
DISCHARGING
6 CELLS DISCHARGING
isoSPI CLOCK FREQUENCY (kHz)
0
10
12
14
800
680412 G45
8
6
200 400 600 1000
4
2
0
isoSPI CURRENT (mA)
WRITE
READ
LTC6804-1
LTC6804-2
ISOMD = VREG
IB= 1mA
TEMPERATURE (°C)
–50 –25
4
isoSPI CURRENT (mA)
6
9
050 75
680412 G44
5
8
7
25 100 125
IB= 1mA
LT6804-1
ISOMD = VREG
LT6804-2
ISOMD = VREG
LT6804-1, ISOMD = 0

LTC6804-1/LTC6804-2
15
680412fc
For more information www.linear.com/LTC6804-1
Typical perForMance characTerisTics
isoSPI Driver Current Gain
(Port A/PortB) vs Temperature
isoSPI Driver Common Mode
Voltage (Port A/Port B) vs Pulse
Amplitude
isoSPI Comparator Threshold
Gain (Port A/Port B) vs Common
Mode
isoSPI Comparator Threshold
Gain (Port A/Port B) vs ICMP
Voltage
Typical Wake-Up Pulse Amplitude
(Port A) vs Dwell Time
IBIAS Voltage vs Temperature IBIAS Voltage Load Regulation
isoSPI Driver Current Gain
(Port A/PortB) vs Bias Current
TA= 25°C, unless otherwise noted.
TEMPERATURE (°C)
–50
1.98
IBIAS PIN VOLTAGE (V)
1.99
2.00
2.01
2.02
–25 0 25 50
680412 G46
75 100 125
IB= 1mA
3 PARTS
BIAS CURRENT (µA)
0
IBIAS PIN VOLTAGE (V)
2.000
2.005
800
408912 G47
1.995
1.990 200 400 600 1000
2.010
BIAS CURRENT (µA)
0
CURRENT GAIN (mA/mA)
21
22
23
800
680412 G48
20
19
18 200 400 600 1000
VA= 0.5V
VA= 1.0V
VA= 1.6V
TEMPERATURE (°C)
–50 –25
18
CURRENT GAIN (mA/mA)
20
23
050 75
680412 G49
19
22
21
25 100 125
IB= 100µA
IB= 1mA
PULSE AMPLITUDE (V)
0
2.5
DRIVER COMMON MODE (V)
3.0
3.5
4.0
4.5
5.0
5.5
0.5 1.0 1.5 2.0
IB= 100µA
IB= 1mA
680412 G50
COMMON MODE VOLTAGE (V)
2.5
0.44
COMPARATOR THRESHOLD GAIN (V/V)
0.46
0.48
0.50
0.52
0.56
3.0 3.5 4.0 4.5
680412 G51
5.0 5.5
0.54
VICMP = 1V
VICMP = 0.2V
ICMP VOLTAGE (V)
0
0.44
COMPARATOR THRESHOLD GAIN (V/V)
0.46
0.48
0.50
0.52
0.4 0.8 1.2 1.6
680412 G52
0.54
0.56
0.2 0.6 1.0 1.4
3 PARTS
WAKE-UP DWELL TIME, tDWELL (ns)
0
WAKE-UP PULSE AMPLITUDE, VWAKE (mV)
150
200
600
680412 G53
100
50 150 300 450
300
250 GUARANTEED
WAKE-UP REGION

LTC6804-1/LTC6804-2
16
680412fc
For more information www.linear.com/LTC6804-1
Typical perForMance characTerisTics
TA= 25°C, unless otherwise noted.
Write Command to a Daisy-Chained
Device (ISOMD = 0)
Data Read-Back from a Daisy-Chained
Device (ISOMD = 0)
Write Command to a Daisy-Chained
Device (ISOMD = 1)
Data Read-Back from a Daisy-Chained
Device (ISOMD = 1)
CSB
5V/DIV
SDI
5V/DIV
SCK
5V/DIV
SDO
5V/DIV
IPB-IMB
2V/DIV
(PORT B) 1µs/DIV 680412 G54
ISOMD = V–
BEGINNING OF A COMMAND
PORT A
IPB-IMB
1V/DIV
(PORT B)
IPA-IMA
1V/DIV
(PORT A)
1µs/DIV 680412 G55
ISOMD = VREG
BEGINNING OF A COMMAND
CSB
5V/DIV
SDI
5V/DIV
SCK
5V/DIV
SDO
5V/DIV
IPB-IMB
2V/DIV
(PORT B)
PORT A
1µs/DIV 680412 G56
ISOMD = V–
END OF A READ COMMAND
IPB-IMB
1V/DIV
(PORT B)
IPA-IMA
1V/DIV
(PORT A)
1µs/DIV 680412 G57
ISOMD = VREG
END OF A READ COMMAND

LTC6804-1/LTC6804-2
17
680412fc
For more information www.linear.com/LTC6804-1
pin FuncTions
C0 to C12: Cell Inputs.
S1 to S12: Balance Inputs/Outputs. 12 N-MOSFETs are
connectedbetweenS(n) andC(n–1)for dischargingcells.
V+:Positive Supply Pin.
V–:Negative Supply Pins. The V–pins must be shorted
together, external to the IC.
VREF2:Buffered 2nd reference voltage for driving multiple
10k thermistors. Bypass with an external 1µF capacitor.
VREF1:ADC Reference Voltage. Bypass with an external
1µF capacitor. No DC loads allowed.
GPIO[1:5]: General Purpose I/O. Can be used as digital
inputs or digital outputs, or as analog inputs with a mea-
surement range from V–to 5V. GPIO [3:5] can be used
as an I2C or SPI port.
SWTEN: Software Timer Enable. Connect this pin to VREG
to enable the software timer.
DRIVE: Connect the base of an NPN to this pin. Connect
the collector to V+and the emitter to VREG.
VREG:5V Regulator Input. Bypass with an external 1µF
capacitor.
ISOMD: Serial Interface Mode. Connecting ISOMD to
VREG configures Pins 41 to 44 of the LTC6804 for 2-wire
isolated interface (isoSPI) mode. Connecting ISOMD to
V–configures the LTC6804 for 4-wire SPI mode.
WDT: Watchdog Timer Output Pin. This is an open drain
NMOS digital output. It can be left unconnected or con-
nected with a 1M resistor to VREG. If the LTC6804 does not
receive a wake-up signal (see Figure 21) within 2 seconds,
the watchdog timer circuit will reset the LTC6804 and the
WDT pin will go high impedance.
Serial Port Pins
LTC6804-1
(DAISY-CHAINABLE)
LTC6804-2
(ADDRESSABLE)
ISOMD = VREG ISOMD = V–ISOMD = VREG ISOMD = V–
PORT B
(Pins 45
to 48)
IPB IPB A3 A3
IMB IMB A2 A2
ICMP ICMP A1 A1
IBIAS IBIAS A0 A0
PORT A
(Pins 41
to 44)
(NC) SDO IBIAS SDO
(NC) SDI ICMP SDI
IPA SCK IPA SCK
IMA CSB IMA CSB
CSB, SCK, SDI, SDO:4-Wire Serial Peripheral Interface
(SPI). Active low chip select (CSB), serial clock (SCK),
and serial data in (SDI) are digital inputs. Serial data out
(SDO) is an open drain NMOS output pin. SDO requires
a 5k pull-up resistor.
A0 to A3: Address Pins. These digital inputs are connected
to VREG or V–to set the chip address for addressable se-
rial commands.
IPA, IMA:Isolated 2-Wire Serial Interface Port A. IPA
(plus) and IMA (minus) are a differential input/output pair.
IPB, IMB:Isolated 2-Wire Serial Interface Port B. IPB
(plus) and IMB (minus) are a differential input/output pair.
IBIAS:Isolated Interface Current Bias. Tie IBIAS to
V–through a resistor divider to set the interface output
current level. When the isoSPI interface is enabled, the
IBIAS pin voltage is 2V. The IPA/IMA or IPB/IMB output
current drive is set to 20 times the current, IB, sourced
from the IBIAS pin.
ICMP: Isolated Interface Comparator Voltage Threshold
Set. Tie this pin to the resistor divider between IBIAS
and V–to set the voltage threshold of the isoSPI receiver
comparators. The comparator thresholds are set to 1/2
the voltage on the ICMP pin.

LTC6804-1/LTC6804-2
18
680412fc
For more information www.linear.com/LTC6804-1
block DiagraM
C12
C11
C10
C9
C8
C7
C0
C6
C5
C4
C3
C2
C1
–
+
680412 BD1
IPB
P
IMB
ICMP
IBIAS
SDO/(NC)
SDI/(NC)
SCK/(IPA)
CSB/(IMA)
ISOMD
WDT
DRIVE
VREG
SWTEN
VREF1
VREF2
GPIO5
GPIO4
V–
V–*
GPIO3
GPIO2
GPIO1
C0
S1
V+
C12
S12
C11
M
S11
C10
S10
C9
S9
C8
S8
C7
S7
C6
S6
C5
S5
C4
S4
C3
S3
C2
S2
C1
LOGIC
AND
MEMORY
DIGITAL
FILTERS
SERIAL I/O
PORT B
6-CELL
MUX
VREGD
SOC
VREG
P
M
AUX
MUX
12 BALANCE FETs
S(n)
C(n – 1)
P
M
6-CELL
MUX
POR
VREGD VREG
SERIAL I/O
PORT A
SOFTWARE
TIMER
DIE
TEMPERATURE
2ND
REFERENCE
1ST
REFERENCE
REGULATORS
ADC2
–
+
ADC1
16
16
V+
LDO1 VREGD
POR
V+
LDO2
DRIVE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
LTC6804-1

LTC6804-1/LTC6804-2
19
680412fc
For more information www.linear.com/LTC6804-1
block DiagraM
SDO/(IBIAS)
C12
C11
C10
C9
C8
C7
C0
C6
C5
C4
C3
C2
C1
–
+
680412 BD2
A4
P
A3
A2
A1
SDI/(ICMP)
SCK/(IPA)
CSB/(IMA)
ISOMD
WDT
DRIVE
SWTEN
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
C0
S1
C12
S12
C11
M
S11
C10
S10
C9
S9
C8
S8
C7
S7
C6
S6
C5
S5
C4
S4
C3
S3
C2
S2
C1
LOGIC
AND
MEMORY
DIGITAL
FILTERS
SERIAL I/O
ADDRESS
6-CELL
MUX
VREGD
SOC
VREG
P
M
AUX
MUX
P
M
6-CELL
MUX
POR
VREGD VREG
SERIAL I/O
PORT A
SOFTWARE
TIMER
DIE
TEMPERATURE
2ND
REFERENCE
1ST
REFERENCE
REGULATORS
ADC2
–
+
ADC1
V+
LDO1 VREGD
POR
V+
LDO2
DRIVE
VREG
VREF1
VREF2
V–
V–*
V+
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
16
16
12 BALANCE FETs
S(n)
C(n – 1)
LTC6804-2

LTC6804-1/LTC6804-2
20
680412fc
For more information www.linear.com/LTC6804-1
operaTion
STATE DIAGRAM
The operation of the LTC6804 is divided into two separate
sections: the core circuit and the isoSPI circuit. Both sec-
tions have an independent set of operating states, as well
as a shutdown timeout.
LTC6804 CORE STATE DESCRIPTIONS
SLEEP State
ThereferenceandADCsarepowereddown.Thewatchdog
timer (see Watchdog and Software Discharge Timer) has
timed out. The software discharge timer is either disabled
ortimed out. The supply currents arereducedtominimum
levels. The isoSPI ports will be in the IDLE state.
If a WAKEUP signal is received (see Waking Up the Serial
Interface), the LTC6804 will enter the STANDBY state.
STANDBY State
The reference and the ADCs are off. The watchdog timer
and/orthesoftwaredischargetimerisrunning.TheDRIVE
pinpowerstheVREG pinto5Vthroughanexternaltransistor.
(Alternatively,VREG canbepoweredbyanexternalsupply).
When a valid ADC command is received or the REFON bit is
set to 1 in the Configuration Register Group, the IC pauses
for tREFUP to allow for the reference to power up and then
enters either the REFUP or MEASURE state. If there is no
WAKEUP signal for a duration tSLEEP (when both the watch-
dogandsoftwaredischargetimerhaveexpired)theLTC6804
Figure 1. LTC6804 Operation State Diagram
returns to the SLEEP state. If the software discharge timer
is disabled, only the watchdog timer is relevant.
REFUP State
To reach this state the REFON bit in the Configuration Reg-
ister Group must be set to 1 (using the WRCFG command,
see Table 36). The ADCs are off. The reference is powered
up so that the LTC6804 can initiate ADC conversions more
quickly than from the STANDBY state.
When a valid ADC command is received, the IC goes to the
MEASURE state to begin the conversion. Otherwise, the
LTC6804willreturntotheSTANDBYstatewhentheREFON
bit is set to 0, either manually (using WRCFG command)
or automatically when the watchdog timer expires. (The
LTC6804 will then move straight into the SLEEP state if
both timers are expired).
MEASURE State
The LTC6804 performs ADC conversions in this state. The
reference and ADCs are powered up.
After ADC conversions are complete the LTC6804 will
transition to either the REFUP or STANDBY states, de-
pending on the REFON bit. Additional ADC conversions
can be initiated more quickly by setting REFON =1 to take
advantage of the REFUP state.
Note: Non-ADC commands do not cause a Core state tran-
sition. Only an ADC conversion or diagnostic commands
will place the Core in the MEASURE state.
680412 F01
isoSPI PORTCORE LTC6804
CONVERSION DONE
(REFON = 1)
WAKEUP
SIGNAL
(tWAKE)
ADC COMMAND
(tREFUP)
ADC
COMMAND
REFON = 1
(tREFUP)
WAKEUP SIGNAL
(CORE = STANDBY)
(tREADY)
WAKEUP SIGNAL
(CORE = SLEEP)
(tWAKE)
TRANSMIT/RECEIVE
NOTE: STATE TRANSITION
DELAYS DENOTED BY (tX)
NO ACTIVITY ON
isoSPI PORT
IDLE TIMEOUT
(tIDLE)
CONVERSION
DONE (REFON = 0)
REFON = 0
WD TIMEOUT
OR SWT TIMEOUT
(tSLEEP)
MEASUREREFUP
STANDBY
SLEEP
ACTIVE
READY
IDLE