Linear Technology DC1369A Quick setup guide

1
dc1369af
DEMO MANUAL DC1369A
Description
LTC2262-14/-12, LTC2261-14/-12,
LTC2260-14/-12, LTC2259-14/-12, LTC2258-14/-12, LTC2257-14/-12,
LTC2256-14/-12, 14/12-Bit, 25Msps to 150Msps ADCs
Demonstration circuit 1369A supports a family of
14/12-bit 25Msps to 150Msps ADCs. Each assembly
features one of the following devices: LTC2262-14 or
LTC2262-12, LTC2261-14, LTC2261-12, LTC2260-14,
LTC2260-12, LTC2259-14, LTC2259-12, LTC2258-14,
LTC2258-12, LTC2257-14, LTC2257-12, LTC2256-14,
LTC2256-12, high speed, high dynamic range ADCs.
Demonstration circuit 1369A supports the LTC2261 family
DDR LVDS output mode. This family of ADCs is also sup-
ported by demonstrationcircuit1370A, which iscompatible
with CMOS and DDR CMOS output modes.
performance summary
Several versions of the 1369A demo board supporting the
LTC2261 14/12-bit series of A/D converters are listed in
Table 1. Depending on the required resolution and sample
rate, the DC1369A is supplied with the appropriate ADC.
The circuitry on the analog inputs is optimized for analog
input frequencies from 5MHz to 170MHz. Refer to the
data sheet for proper input networks for different input
frequencies.
Design files for this circuit board are available at
http://www.linear.com/demo
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope
and QuikEval are trademarks of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
(TA= 25°C)
Table 1
PARAMETER CONDITION VALUE
Supply Voltage – DC1369A Depending on sampling rate and the A/D converter
provided, this supply must provide up to 250mA
Optimized for 3.6V
3.5V ↔6.0V Min/Max
Analog Input Range Depending on SENSE Pin Voltage 1VP-P to 2VP-P
Logic Input Voltages Minimum Logic High 1.3V
Maximum Logic Low 0.6V
Logic Output Voltages (Differential) Nominal Logic Levels (100Ω Load, 3.5mA Mode) 350mV/1.25V Common Mode
Minimum Logic Levels (100Ω Load, 3.5mA Mode) 247mV/1.25V Common Mode
Sampling Frequency (Convert Clock Frequency) See Table 1
Convert Clock Level Single-Ended Encode Mode (ENC – Tied to GND) 0V to 3.6V
Convert Clock Level Differential Encode Mode (ENC – Not Tied to GND) 0.2V to 3.6V
Resolution See Table 1
Input Frequency Range See Table 1
SFDR See Applicable Data Sheet
SNR See Applicable Data Sheet

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dc1369af
DEMO MANUAL DC1369A
Demonstration circuit 1369A is easy to set up to evaluate
the performance of the LTC2262 family of A/D converters.
Refer to Figure 1 for proper measurementequipment setup
and follow the procedure below:
Setup
If a DC890 QuikEval™ II Data Acquisition and Collection
System was supplied with the DC1369A demonstration
circuit, follow the DC890 Quick Start Guide to install the
required software and for connecting the DC890 to the
DC1369A and to a PC.
DC1369A Demonstration Circuit Board Jumpers
The DC1369A demonstration circuit board should have
the following jumper settings as default positions (as per
Figure 1):
JP2: PAR/SER: Selects Parallel or Serial programming
mode. (Default – Serial)
JP3: Duty Cycle Stabilizer: Enables/Disable Duty Cycle
Stabilizer. (Default – Enable)
JP4: SHDN: Enables and disables the LTC2262
(Default – Enable)
Applying Power and Signals to the DC1369A
Demonstration Circuit
If a DC890 is used to acquire data from the DC1369A,
the DC890 must first be connected to a powered USB
port or provided an external 6V to 9V before applying
3.6V to 6.0V across the pins marked V+and GND on the
DC1369A. DC1369A requires 3.6V for proper operation.
Regulators on the board produce the voltages required for
the ADC. The DC1369A demonstration circuit requires up
to 250mA depending on the sampling rate and the A/D
converter supplied.
The DC890 data collection board is powered by the USB
cable and does not require an external power supply unless
it must be connected to the PC through an unpowered hub,
in which case it must be supplied an external 6V to 9V on
turrets G7(+) and G1(–) or the adjacent 2.1mm power jack.
Analog Input Network
For optimal distortion and noise performance the RC
network on the analog inputs may need to be optimized
for different analog input frequencies. For input frequen-
cies above 170MHz, refer to the LTC2262 data sheet for a
proper input network. Other input networks may be more
appropriate for input frequencies less that 5MHz.
Quick start proceDure
Table 2. DC1369A Variants
DC1369A VARIANTS ADC PART NUMBER RESOLUTION MAXIMUM SAMPLE RATE INPUT FREQUENCY
1369A-A LTC2261-14 14-Bit 125Msps 5MHz to 170MHz
1369A-B LTC2260-14 14-Bit 105Msps 5MHz to 170MHz
1369A-C LTC2259-14 14-Bit 80Msps 5MHz to 170MHz
1369A-D LTC2258-14 14-Bit 65Msps 5MHz to 170MHz
1369A-E LTC2257-14 14-Bit 40Msps 5MHz to 170MHz
1369A-F LTC2256-14 14-Bit 25Msps 5MHz to 170MHz
1369A-G LTC2261-12 12-Bit 125Msps 5MHz to 170MHz
1369A-H LTC2260-12 12-Bit 105Msps 5MHz to 170MHz
1369A-I LTC2259-12 12-Bit 80Msps 5MHz to 170MHz
1369A-J LTC2258-12 12-Bit 65Msps 5MHz to 170MHz
1369A-K LTC2257-12 12-Bit 40Msps 5MHz to 170MHz
1369A-L LTC2256-12 12-Bit 25Msps 5MHz to 170MHz
1369A-M LTC2262-14 14-Bit 150Msps 5MHz to 170MHz
1369A-N LTC2262-12 12-Bit 150Msps 5MHz to 170MHz

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dc1369af
DEMO MANUAL DC1369A
Figure 1. DC1369A Setup
Quick start proceDure
DC1369A F01
Analog Input
3.5V to 6V
+
Single-Ended
Encode Clock
Parallel/Serial
Programming Mode
Duty Cycle Stabilizer
SHDN
Parallel Data Output
to DC890
Jumpers Are Shown in
Default Positions

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dc1369af
DEMO MANUAL DC1369A
Quick start proceDure
In almost all cases, filters will be required on both analog
input and encode clock to provide data sheet SNR. In the
case of the DC1369A a bandpass filter used for the clock
should be used prior to the DC1075A.
The filters should be located close to the inputs to avoid
reflections from impedance discontinuities at the driven
end of a long transmission line. Most filters do not present
50Ω outside the passband. In some cases, 3dB to 10dB
pads may be required to obtain low distortion.
If your generator cannot deliver full-scale signals without
distortion, you may benefit from a medium power amplifier
based on a Gallium Arsenide Gain block prior to the final
filter. This is particularly true at higher frequencies where
IC based operational amplifiers may be unable to deliver
the combination of low noise figure and High IP3 point
required. A high order filter can be used prior to this final
amplifier, and a relatively lower Q filter used between the
amplifier and the demo circuit.
Encode Clock
NOTE: Apply an encode clock to the SMA connector on
the DC1369A demonstration circuit board marked J7.
As a default the DC1369A is populated to have a single-
ended input.
For the best noise performance, the encode input must
be driven with a very low jitter, square wave source. The
amplitude should be large, up to 3VP-P or 13dBm. When
using a sinusoidal signal generator a squaring circuit can
be used. Linear Technology also provides demo board
DC1075A that divides a high frequency sine wave by four,
producing a low jitter square wave for best results with
the LTC2262 family.
Using bandpass filters on the clock and the analog input
will improve the noise performance by reducing the
wideband noise power of the signals. In the case of the
DC1369A a bandpass filter used for the clock should be
used prior to the DC1075A. Data sheet FFT plots are taken
with 10 pole LC filters made by TTE (Los Angeles, CA) to
suppress signal generator harmonics, non harmonically
related spursand broadband noise.Low phase noiseAgilent
8644B generators are used with TTE bandpass filters for
both the clock input and the analog input.
Apply the analog input signal of interest to the SMA con-
nectors on the DC1369A demonstration circuit board
marked J5 AIN+. These inputs are capacitive coupled to
Balun transformers ETC1-1-13.
An internally generated conversion clock output is avail-
able on J1 which could be collected via a logic analyzer, or
other data collection system if populated with a SAMTEC
MEC8-150 type connector or collected by the DC890 Qui-
kEval II Data Acquisition Board using PScope™ software.

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dc1369af
DEMO MANUAL DC1369A
Quick start proceDure
Manual Configuration settings:
Bits: 14 (or 12 for 12-bit parts)
Alignment: 14
FPGA Ld: DDR LVDS
Channs: 2
Bipolar: Checked
Positive-Edge Clk: Checked
If everything is hooked up properly, powered and a suit-
able convert clock is present, clicking the Collect button
should result in time and frequency plots displayed in
the PScope window. Additional information and help for
PScope is available in the DC890 Quick Start Guide and in
the online help available within the PScope program itself.
Figure 2. ADC Configuration
Software
The DC890 is controlled by the PScope System Software
provided or downloaded from the Linear Technology
website at http://www.linear.com/software/. If a DC890
was provided, follow the DC890 Quick Start Guide and
the instructions below.
To start the data collection software if PScope.exe is in-
stalled (by default) in \Program Files\LTC\PScope\, double
click the PScope Icon or bring up the run window under
the start menu and browse to the PScope directory and
select PScope.
If the DC1369Ademonstration circuitis properly connected
to the DC890, PScope should automatically detect the
DC1369A, and configure itself accordingly. If necessary
the procedure below explains how to manually configure
PScope.
Under the Configure menu, go to “ADC Configuration....”
Check the Config Manually box and use the following
configuration options (see Figure 2):

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dc1369af
DEMO MANUAL DC1369A
Quick start proceDure
Serial Programming
PScope has the ability to program the DC1369A board
serially through the DC890. There are several options
available in the LTC2262 family that are only available
through serially programming. PScope allows all of these
features to be tested.
These options are available by first clicking on the Set
Demo Bd Options icon on the PScope toolbar (Figure 3).
This will bring up the menu shown in Figure 4.
Figure 4. Demo Board Configuration Options
Figure 3. PScope Toolbar
This menu allows any of the options available for the
LTC2262 family to be programmed serially. The LTC2262
family has the following options:
Power Control: Selects between normal operation, nap,
and sleep modes
• Normal(Default):EntireADCispowered,andactive
• Nap: ADC core powers down while references stay
active
• Shutdown:TheentireADCispowereddown
Clock Inversion: Selects the polarity of the CLKOUT signal
• Normal(Default):NormalCLKOUTpolarity
• Inverted:CLKOUTpolarityisinverted
Clock Delay: Selects the phase delay of the CLKOUT
signal
• None(Default):NoCLKOUTdelay
• 45deg:CLKOUTdelayedby45degrees
• 90deg:CLKOUTdelayedby90degrees
• 135deg:CLKOUTdelayedby135degrees
Clock Duty Cycle: Enable or Disables Duty Cycle Stabilizer
• StabilizerOff(Default):Dutycyclestabilizerdisabled
• StabilizerOn:Dutycyclestabilizerenabled
Output Current: Selects the LVDS output drive current
• 1.75mA(Default):LVDSoutputdrivercurrent
• 2.1mA:LVDSoutputdrivercurrent
• 2.5mA:LVDSoutputdrivercurrent
• 3.0mA:LVDSoutputdrivercurrent
• 3.5mA:LVDSoutputdrivercurrent
• 4.0mA:LVDSoutputdrivercurrent
• 4.5mA:LVDSoutputdrivercurrent

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DEMO MANUAL DC1369A
Quick start proceDure
Internal Termination: Enables LVDS Internal Termination
• Off(Default):Disablesinternaltermination
• On:Enablesinternaltermination
Outputs: Enables Digital Outputs
• Enabled(Default):Enablesdigitaloutputs
• Disabled:Disablesdigitaloutputs
Output Mode: Selects Digital Output Mode
• FullRate:FullrateCMOSoutputmode(Thismodeis
not supported by the DC1369A, please use the DC1370)
• DoubleLVDS(Default):DoubledatarateLVDSoutput
mode
• DoubleCMOS:DoubledatarateCMOSoutputmode
(This mode is not supported by the DC1369A, please
use the DC1370)
Test Pattern: Selects Digital Output Test Patterns
• Off(Default):ADCdatapresentedatoutput
• AllOut=1:Alldigitaloutputsare1
• AllOut=0:Alldigitaloutputsare0
• Checkerboard:OF,andD13-D0Alternatebetween101
0101 1010 0101 and 010 1010 0101 1010 on alternat-
ing samples.
• Alternating:Digitaloutputsalternatebetweenall1’sand
all0’sonalternatingsamples.
Alternate Bit: Alternate Bit Polarity (ABP) Mode
• Off(Default):Disablesalternatebitpolarity
• On:Enablesalternatebitpolarity(BeforeenablingABP,
be sure the part is in offset binary mode)
Randomizer: Enables Data Output Randomizer
• Off(Default):Disablesdataoutputrandomizer
• On:Enablesdataoutputrandomizer
Two’s Complement:EnablesTwo’sComplementMode
• Off(Default):Selectsoffsetbinarymode
• On:Selectstwo’scomplementmode
Once the desired settings are selected hit OK and PScope
will automatically update the register of the device on the
DC1369A demo board.

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dc1369af
DEMO MANUAL DC1369A
parts List
ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
1 1 C1 RES, 0402 150Ω 1% 1/16W VISHAY CRCW0402150RFKED
2 9 C2, C3, C6, C7, C38, C39, C59-C61 CAP, 0402 0.01uF 10% 16V X7R AVX 0402YC103KAT
3 2 C10, C9 CAP, 0402 8.2pF 5% 50V COG AVX 04025A8R2JAT2A
4 6 C12, C15, C18, C19, C21, C37 CAP, 0402 0.1uF 10% 10V X5R TDK C1005X5R1A104K
5 3 C13, C17, C23 CAP, 0402 1uF 10% 10V X5R TDK C1005X5R1A105K
6 2 C14, C22 CAP, 0603 1uF 10% 16V X7R TDK C1608X7R1C105K
7 1 C20 CAP, 0402 1uF 10% 10V X5R MURATA GRM155R61A105KE15D
8 1 C24 CAP, 0603 4.7uF 20% 6.3V X5R TDK C1608X5R0J475MT
9 12 C26-C36, C56 CAP, 0603 0.1uF 10% 50V X7R TDK C1608X7R1H104K
10 1 C51 CAP, 0402 4.7pF +/-0.25pF 50V NPO AVX 04025A4R7CAT2A
11 2 C53, C52 CAP, 0402 100pf 5% 50V COG TDK C1005C0G1H101J
12 2 C54, C55 CAP, 1206 22uF 10% 6.3V X5R AVX 12066D226KAT2A
13 7 R9, R10, R48, R54, R57, C57, C58 RES, 0402 0Ω JUMPER VISHAY CRCW04020000Z0ED
14 1 D1 DIODE, SCHOTTKY SOT-23 AVAGO HSMS-2822
15 3 JP2, JP3, JP4 HEADER, 3-PIN, 2mm SAMTEC TMM-103-02-L-S
16 3 J5, J7, J9 CONN, BNC, SMA 50Ω EDGE-LANCH E.F.JOHNSON, 142-0701-851
17 1 J8 HEADER, 2×7 2mm MOLEX 87331-1420
18 1 L1 IND, 0603 56uH 5% MURATA LQP18MN56NG02D
19 3 L2, L3, L4 FERRITE BEAD, 1206 MURATA BLM31PG330SN1L
20 1 L5 IND, 0603 BEAD ?
21 1 L6 IND, 0603 OPTION OPTION
22 1 P1 EDGE FINGERS ON PCB PART OF THE PCB
23 2 RN2, RN1 RES ARRAY, 33Ω VISHAY CRA04SS08333R0JTD
24 2 R1, R2 RES, 0402 301Ω 1% 1/16W VISHAY CRCW0402301RFKED
25 3 R4, R5, R56 RES, 0402 OPTION OPTION
26 1 R6 RES, 0402 10kΩ 5% 1/16W VISHAY CRCW040210K0JNED
27 1 R7 RES, 0402 10kΩ 1% 1/16W VISHAY CRCW040210K0FKED
28 1 R8 RES, 0402 6.81kΩ 1% 1/16W YAGEO RC0402FR-076K81L
29 4 R14, R33, R34, R35 RES, 0402 1kΩ 5% 1/16W VISHAY CRCW04021K00JNTDE3
30 1 R16 RES, 0402 100Ω 5% 1/16W VISHAY CRCW0402100RJNED
31 8 R17-R23, R30 RES, 0201 100Ω 5% 1/16W VISHAY CRCW0201100RFNTD
32 1 R24 RES, 0402 100kΩ 5% 1/16W VISHAY CRCW0402100KJNED
33 3 R25, R26, R29 RES, 0603 4.99kΩ 1% 1/16W AAC CR16-4991FM
34 3 R36, R44, R45 RES, 0402 86.6Ω 1% 1/16W VISHAY CRCW040286R6FKED
35 2 R40, R39 RES, 0402 24.9Ω 1% 1/16W VISHAY CRCW040224R9FKED
36 0 R46, R49, R52, R53, R55 RES, 0402 OPTION VISHAY CRCW0402101J ?
37 1 R47 RES, 0402 20Ω 1% 1/16W VISHAY CRCW040220R0FKED
38 1 R50 IND, 36nH COILCRAFT 0402CS-36NXJB
39 0 R51 RES, 0402 301Ω 1% 1/16W OPTION VISHAY CRCW0402301RFKED OPTION
40 5 TP1, TP2, TP3, TP4, TP5 TURRETS MILLMAX 2501-2-00-80-00-00-07-0
41 1 T1 XFMR, 1:1 MACOM MABA-007159-000000
42 1 T2 XFMR, 1:1 CT M/A-C0M MABAES0060/COILCRAFT WBC1-1LB

9
dc1369af
DEMO MANUAL DC1369A
parts List
ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
43 1 T3 XFMR, 1:4 CT COILCRAFT WBC4-1WLB
44 1 U1 IC, EEPROM MICROCHIP TECH. 24LC025-I/ST
45 1 U3 IC, FIN1108 FAIRCHILD FIN1108
46 1 U4 IC, LDO Micropower Regulators LINEAR TECH. LT1763CDE-1.8
47 1 U5 IC, 8-BIT I/0 EXPANDER PHILIPS SEMI PCF8574TS/3
48 1 U6 IC, LDO Micropower Regulators LINEAR TECH. LT1763CDE
49 1 U7 IC, EEPROM MICROCHIP TECH. 24LC32A-I/ST
50 3 XJP2, XJP3, XJP4 SHUNT, 2mm SAMTEC 2SN-BK-G
51 4 STANDOFF, SNAP ON KEYSTONE_8831
See page 2 of the Schematic Diagram for U2.

10
dc1369af
DEMO MANUAL DC1369A
5 5
4 4
3 3
2 2
1 1
D D C C B B A A
GND
FAST DAACS BOARD ID CIRCUITRY
OXA0
OX40
OXA2
 
3.1 Change 05/22/12 Clarence M.
SCL
VCC_IN
SDA VSS
VCC_IN
PAR/SER
ENABLE
ENABLE
-D8/D9 -D6/D7 +D2/D3 -D2/D3 +D0/D1 +CLK -CLK +D12/D13 -D12/D13 +D10/D11 -D10/D11 +D8/D9 +D6/D7 -D0/D0
SDI
SCL SDA
SCK SDI
VSS
CS
SCK
SDI
SD0
SD0 SCK
SD0
-D4/D5 +D4/D5
CS
CS
SDIPAR/SER
CS
VCC_IN
VSS SCL
VSS
SDA SCL
VCC_IN
SCL
SDA
SDA
SCL SDA
VOUT
VDD
VDD
VDD
OVDD
VOUT
VDD
OVDD
VDD
VOUT
VOUT
VOUT
VIN
VDD
VDD VDD
VOUT
VDD
Customer Notice:
Linear Technology has made a best effort to
design a circuit that meets customer-supplied specifications; however, it remains the customers responsibility to verify proper
and reliable operation in the actual application, Component
substitution and printed circuit board layout may significantly affect circuit performance or reliability. Contact Linear
Applications Engineering for assistance.
This circuit is proprietary to Linear Technology and supplied for use with Linear Technology parts.
Customer Notice:
Linear Technology has made a best effort to
design a circuit that meets customer-supplied specifications; however, it remains the customers responsibility to verify proper
and reliable operation in the actual application, Component
substitution and printed circuit board layout may significantly affect circuit performance or reliability. Contact Linear
Applications Engineering for assistance.
This circuit is proprietary to Linear Technology and supplied for use with Linear Technology parts.
Customer Notice:
Linear Technology has made a best effort to
design a circuit that meets customer-supplied specifications; however, it remains the customers responsibility to verify proper
and reliable operation in the actual application, Component
substitution and printed circuit board layout may significantly affect circuit performance or reliability. Contact Linear
Applications Engineering for assistance.
This circuit is proprietary to Linear Technology and supplied for use with Linear Technology parts.
REVISION HISTORY
DESCRIPTION DATE APPROVEDECO REV
PROTO
308/11/08
REVISION HISTORY
DESCRIPTION DATE APPROVEDECO REV
PROTO
308/11/08
REVISION HISTORY
DESCRIPTION DATE APPROVEDECO REV
PROTO
308/11/08
SIZE
SCALE:
CAGE CODE
DWG NO
REV
SHEET OF
FILENAME:
TITLE
CONTRACT NO.
APPROVALS
DATE
DRAWN CHECKED APPROVED ENGINEER DESIGNER
TECHNOLOGY
1630 McCarthy Blvd. Milpitas, CA 95035 Phone: [phone] Fax: [phone]
3.1
DC1369A
05/22/12 05:59:39
12
SCH, LTC2261CUJ, HIGH SPEED LOW POWER
1369A-3.DSN
NONE
MI 10/31/07
125MSPS ADC FAMILY, LVDS
SIZE
SCALE:
CAGE CODE
DWG NO
REV
SHEET OF
FILENAME:
TITLE
CONTRACT NO.
APPROVALS
DATE
DRAWN CHECKED APPROVED ENGINEER DESIGNER
TECHNOLOGY
1630 McCarthy Blvd. Milpitas, CA 95035 Phone: [phone] Fax: [phone]
3.1
DC1369A
05/22/12 05:59:39
12
SCH, LTC2261CUJ, HIGH SPEED LOW POWER
1369A-3.DSN
NONE
MI 10/31/07
125MSPS ADC FAMILY, LVDS
SIZE
SCALE:
CAGE CODE
DWG NO
REV
SHEET OF
FILENAME:
TITLE
CONTRACT NO.
APPROVALS
DATE
DRAWN CHECKED APPROVED ENGINEER DESIGNER
TECHNOLOGY
1630 McCarthy Blvd. Milpitas, CA 95035 Phone: [phone] Fax: [phone]
3.1
DC1369A
05/22/12 05:59:39
12
SCH, LTC2261CUJ, HIGH SPEED LOW POWER
1369A-3.DSN
NONE
MI 10/31/07
125MSPS ADC FAMILY, LVDS
C53 100pF C53 100pF
R34 1K R34 1K
U7 24LC32A-I/STU7 24LC32A-I/ST
A0
1
A1
2
A2
3
A3
4SDA 5
SCL 6
WP 7
VCC 8
C15 0.1uF C15 0.1uF
R40 1% 24.9 R40 1% 24.9
C33 0.1uF C33 0.1uF
C13 1uF C13 1uF
C38 0.01uF C38 0.01uF
L1 56uH L1 56uH
C7 0.01uF C7 0.01uF
1 2
C60 0.01uF C60 0.01uF
1 2
C52 100pF C52 100pF
T1
MABA-007159-000000
T1
MABA-007159-000000
C59 0.01uF C59 0.01uF
1 2
R21 100 R21 100
U1 24LC025-I/STU1 24LC025-I/ST
A0
1
A1
2
A2
3
A3
4SDA 5
SCL 6
WP 7
VCC 8
R24 100K R24 100K
R16 100 R16 100
R33 1K R33 1K
C12 0.1uF C12 0.1uF
C17 1uF C17 1uF
C27 0.1uFC27 0.1uF
R35 1K R35 1K
R45 86.6 1%R45 86.6 1%
L4 BEAD L4 BEAD
C58  C58 
1 2
R4 OPTR4 OPT
R20
100
R20
100
TP5
GND
TP5
GND
R50 36nHR50 36nH
C3 0.01uF C3 0.01uF
1 2
C24 4.7uF C24 4.7uF
R25 4.99K
1%
R25 4.99K
1%
T3
WBC4-1WL
T3
WBC4-1WL
JP3
DUTY CYCLE STAB. EN DIS
JP3
DUTY CYCLE STAB. EN DIS
1 3 2
C35 0.1uF C35 0.1uF
R1 301 1% R1 301 1%
C36 0.1uF C36 0.1uF
RN2 33RN2 33
1 2 3 4
8 7 6 5
R39 1% 24.9 R39 1% 24.9
U2
*
U2
*
D10_11+ 32
AIN+
1
AIN-
2
GND
3
REFH
4
REFH
5
REFL
6
REFL
7
PAR/SER
8
VDD
9
VDD
10
ENC+
11
ENC-
12
CS
13
SCK
14
SDI
15
SDO
16
D0_1-
17
D0_1+
18
D2_3-
19
D2_3+
20
D4_5- 21
D4_5+ 22
D6_7- 23
D6_7+ 24 OGND 25
OVDD 26
CLKOUT- 27
CLKOUT+ 28
D8_9- 29
D8_9+ 30
D10_11- 31
D12_13- 33
D12_13+ 34
OF+ 36
OF- 35
VCM 37
VREF 38
SENSE 39
VDD 40
GND
41
R55 OPTR55 OPT
R44 86.6 1% R44 86.6 1%
R48 0R48 0
R10 0R10 0
L2 BEAD L2 BEAD
TP2
V+
3.5V - 6V
TP2
V+
3.5V - 6V
R2 301 1% R2 301 1%
TP4TP4
R23 100 R23 100
J9
ENC-
J9
ENC-
U5
PCF8574TS/3
U5
PCF8574TS/3
P0 10 P1 11 P2 12 P3 14
SDA
4
P4 16 P5 17 P6 19 P7 20
GND
15
SCL
2
INT
1
VDD 5
A0
6
A1
7
A2
9
NC
8NC 3
NC 13 NC 18
U6 LT1763CDEU6 LT1763CDE
GND 7
SHDN
8
SENSE 5
BYP 6
NC
9
IN
10 OUT 2
NC
4
IN
11 OUT 3
NC
12
NC
1
R6 10K R6 10K
C30 0.1uF C30 0.1uF L6 OPT L6 OPT
C1 OPT C1 OPT
1 2
C14 1uF C14 1uF
R51 OPT R51 OPT
L5
BEAD
L5
BEAD
JP2
PAR SER
PAR/SER
JP2
PAR SER
PAR/SER
1 3 2
D1
HSMS-2822
D1
HSMS-2822
1 2
3
R22 100 R22 100
J8J8
5V 2
SCK/SCL 4
CS 6
GND
8
EEVCC 10
EEGND 12
NC 14
VUNREG 1
GND
3
MISO 5
MOSI/SDA 7
EESDA 9
EESCL 11
GND
13
R56 OPT R56 OPT
C32 0.1uF C32 0.1uF
C19 0.1uF C19 0.1uF
R49
OPT
R49
OPT
R17 100 R17 100
C22 1uF C22 1uF
C31 0.1uF C31 0.1uF
R26 4.99K 1%R26 4.99K 1%
R14 1K R14 1K
R52
OPT
R52
OPT
R54 0R54 0
RN1 33RN1 33
1 2 3 4
8 7 6 5
U4 LT1763CDE-1.8U4 LT1763CDE-1.8
GND 7
SHDN
8
SENSE 5
BYP 6
NC
9
IN
10 OUT 2
NC
4
IN
11 OUT 3
NC
12
NC
1
C57  C57 
1 2
C26 0.1uF C26 0.1uF
T2
MABAES0060
T2
MABAES0060
R8 6.81K 1%R8 6.81K 1%
R36 86.6 1% R36 86.6 1%
C39 0.01uF C39 0.01uF
C54 22uF C54 22uF
TP1
EXT REF
TP1
EXT REF
C51
4.7pF
C51
4.7pF
C56 0.1uFC56 0.1uF
J7
ENC+
J7
ENC+
C34 0.1uF C34 0.1uF C21
0.1uF C21 0.1uF
C61
0.01uF
C61
0.01uF
1 2
C28 0.1uF C28 0.1uF
R46 OPTR46 OPT
C37 0.1uF C37 0.1uF
R18
100
R18
100
R47 0R47 0
J5
AIN+
J5
AIN+
TP3
GND
TP3
GND
C10 8.2pF C10 8.2pF
C2 0.01uFC2 0.01uF
C9 8.2pF C9 8.2pF
C6
0.01uF
C6
0.01uF
1 2
C55 22uF C55 22uF
P1 EDGE-CON-100P1 EDGE-CON-100
2 4 6 8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98
100
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99
R30
100
R30
100
JP4 SHDN
EN DIS
JP4 SHDN
EN DIS
1 3 2
C18 0.1uF C18 0.1uF
R53 OPTR53 OPT
C29 0.1uF C29 0.1uF
R29 4.99K 1%R29 4.99K 1%
L3 BEADL3 BEAD
C20 1uF C20 1uF
R19 100 R19 100
R7 10K 1%R7 10K 1%
R57 0 R57 0
C23 1uF C23 1uF
R9 0R9 0
U3 FIN1108 U3 FIN1108
OUT6- 32
VE1
1
VE2
2
EN12
3
IN1-
4
IN1+
5
IN2+
6
IN2-
7
IN3-
8
IN3+
9
IN4+
10
IN4-
11
VC1 12
EN
13
IN5-
14
IN5+
15
IN6+
16
IN6-
17
IN7-
18
IN7+
19
IN8+
20
IN8-
21
EN34
22
VE3
23
VBB
24
VC2 25
VC3 26
EN56
27
OUT8- 28
OUT8+ 29 OUT7+ 30
OUT7- 31
OUT6+ 33 OUT5+ 34
VE4
36
OUT5- 35
VE5
37
OUT4- 38
OUR4+ 39
OUT3+ 40
OUT3- 41 OUT2- 42
OUT2+ 43 OUT1+ 44
OUT1- 45
EN78
46
VC5 48
VC4 47
R5 OPTR5 OPT
schematic Diagram