Linear Technology DC1974 Series Quick setup guide

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dc1974f
DEMO MANUAL DC1974
DESCRIPTION
LTC2124, LTC2123, LTC2122
14-Bit, 310Msps to 170Msps Dual
ADCs with JESD204B Outputs
Demonstration circuit 1974 supports the LT C
®
2124 14-bit
dual ADC family with JESD204B compliant CML outputs.
It was specially designed for applications that require
single-ended AC coupled inputs. The DC1974 supports
the LTC2124, LTC2123 and LTC2122 with sample rates
from 310Msps to 170Msps.
The specific ADC characteristics are listed in the DC1974
Variants section. The circuitry on the analog inputs is opti-
mized for analog input frequencies from 5MHz to 400MHz.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
Refer to the data sheet for proper input networks for dif-
ferent input frequencies.
Design files for this circuit board are available at
http://www.linear.com/demo/DC1974
DC1974 VARIANTS ADC PART NUMBER
RESOLUTION
(Bit)
MAXIMUM SAMPLE RATE
(Msps)
INPUT FREQUENCY
(MHz)
1974A-A LTC2124 14 310 5 to 400
1974A-B LTC2123 14 250 5 to 400
1974A-C LTC2122 14 170 5 to 400
PARAMETER CONDITION MIN TYP MAX UNIT
ADC Supply Voltage This Supply Must Provide Up to 700mA 4 6 V
Analog Input Range 1.35 1.5 VPP
Sampling Frequency (Device Clock Frequency) Depending on ADC (1X CLK Mode) 10 310 MHz
Device Clock Level (Single-Ended at J3) Minimum Logic Levels (DEVCLK+ Tied to GND) 0 V
Maximum Logic Levels (DEVCLK+ Tied to GND) 3.6 V
Device Clock Level (Differential Signal Across J3 and J4) Minimum Logic Levels (DEVCLK+ Not Tied to GND,
1.2V Common Mode)
0.2 V
Digital Inputs (ADC_SYS_REF_N, ADC_SYS_REF_P,
SYNC_N, SYNC_P)
Differential Input Voltage 0.2 1.8 V
Common Mode Input Range 1.1 1.2 1.5 V
PERFORMANCE SUMMARY
Specifications are at TA= 25°C
DC1974 VARIANTS

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DEMO MANUAL DC1974
QUICK START PROCEDURE
Figure 1. DC1974 Setup
Demonstration circuit 1974 is easy to set up to evaluate the
performance of the LTC2124 A/D converter family. Refer
to Figure 1 for proper measurement equipment setup and
follow the procedure below:
SETUP
The DC1974 evaluation system uses standard, off the shelf
FPGA evaluation boards for data capture and communi-
cation with the host computer. Follow the instructions in
Appendix A for the Xilinx KC705 based system. Verilog
code may be downloaded from the respective ADC landing
page. www.linear.com/LTC2123
CHANNEL 1
SINGLE-ENDED
ANALOG INPUT
OPTIONAL FPGA
REFERENCE
CLOCK INPUT
OPTIONAL FPGA
REFERENCE
SIGNAL INPUT
OPTIONAL SYS_REF
INPUT FOR ADC
(SUB CLASS 1 ONLY)
SINGLE-ENDED DEVICE
CLOCK INPUT
OPTIONAL SYS_REF
INPUT FOR FPGA
(SUB CLASS 1 ONLY)
JUMPERS SHOWN IN THEIR
DEFAULT POSITIONS
4V TO 6V
dc1974 F01
THE DC1974 CONNECTS TO
KC705 VIA AN FMC CONNECTOR
CHANNEL 2
SINGLE-ENDED
ANALOG INPUT

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DEMO MANUAL DC1974
HARDWARE SETUP
SMAs
J1: AINA – Analog input for channel A – Apply a signal to
J1 from a 50Ω driver. Filters are required for data sheet
performance.
J2: AINB – Analog input for channel B – Apply a signal to
J2 from a 50Ω driver. Filters are required for data sheet
performance.
J3: DEVCLK––Encode clock input for single-ended
clocks–By default the DC1974 is defined to accept a
single-ended clock signal on J3. It can be modified to ac-
cept a differential clock signal through J3 and J4. Some
component changes are required, see the encode clock
section for more information.
J4: DEVCLK+ – Encode clock input for differential sig-
nals – By default the DC1974 is defined to accept a
single-ended clock signal on J3. It can be modified to
accept a differential clock signal through J3 and J4. Some
component changes are required, see the encode clock
section for more information.
J5 and J6: ADC_SYS_REF – JESD204B Subclass 1 only –
When testing the ADC in subclass 1 operation a SYS_REF
input is required to synchronize the ADC and FPGA. Apply
a SYS_REF signal to this input from a SYS_REF driver
board. This input drives the SYS_REF of the ADC.
J11 and J12: FPGA_SYS_REF – JESD204B Subclass 1
only – When testing the ADC in subclass 1 operation a
SYS_REF input is required to synchronize the ADC and
FPGA.ApplyaSYS_REFsignal tothisinputfrom aSYS_REF
driver board. This input drives the SYS_REF of the FPGA.
J7 and J8: FPGA_GBT_REF – This is an optional reference
port for the FPGA. It is used for testing purposes only. In
the default configuration these SMAs are not used.
J9 and J10: FPGA_CLK – This is an optional clock input
port for the FPGA. It is used for testing purposes only. In
the default configuration these SMAs are not used.
TURRETS
V+: Positive supply voltage for the ADC and digital
logic–This voltage feeds a regulator that supplies the
proper voltages for the ADC and buffers. The voltage range
for this turret is 4V to 6V. The supply should be able to
deliver 700mA of current.
SENSE: Optional reference voltage – This pin is connected
directly to the SENSE pin of the ADC. Connecting SENSE
to VDD selects the internal reference and a ±0.66V input
range. The same input voltage range can be achieved
by applying an external 1.25V reference to SENSE. If no
external voltage is supplied this pin will be pulled up to
VDD through a 1k pull-up resistor.
1.8V OUT: Optional 1.8V turret – This pin is connected
directly to the VDD pin of the ADC. It requires a supply that
can deliver up to 500mA. Driving this pin will shutdown the
on board regulator. It can also be a test point to measure
the voltage at the output of the regulators.
GND: Ground Connection – This demo board only has a
single ground plane. This turret should be tied to the GND
terminal of the power supply being used.
JUMPERS:
JP1 EEPROM:EEPROMwriteprotect.Forfactory use only.
Should be left in the enable (PROG) position.
JP2 SYNC: This jumper is provided to manually force the
SYNC~ signal of the ADC to a known value. By default,
the resistors connecting this jumper are removed. If R20
and R21 are installed the SYNC jumper can be used to
force SYNC~ high or low depending on the position of the
jumper. Position 0 is for low and 1 is for high.

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DEMO MANUAL DC1974
If a Kintex 7 FPGA board is used to acquire data from
the DC1974, the Kintex 7 FPGA board must FIRST be
poweredBEFOREapplying4V to 6Vacross the pins marked
“V+” and “GND” on the DC1974. For more information
about the Kintex 7 board, please see the demo manual at
www.xilinx.com. TheDC1974requiresat least4Vforproper
operation. Regulators on the board produce the voltages
required for the ADC and the required logic devices. The
DC1974 requires up to 700mA. The DC1974 should not be
removed or connected to the Kintex 7 FPGA board while
power is applied.
The DC2159 should also be connected to the Kintex 7
board and the supplied mini USB cable should be con-
nected to the DC2159. The Kintex 7 board should be
powered on BEFOREthe mini USB connector is connected
to theDC2159. See Figure 5 in Appendix A.
APPLYING POWER AND SIGNALS TO THE DC1974 DEMONSTRATION CIRCUIT
Apply the analog input signal of interest to the SMA con-
nector on the DC1974 board marked J1 or J2. In the default
setup, the DC1974 has a single SMA input that is meant
to be driven with a 50Ω source. The DC1974 is populated
with an input network that has 50Ω characteristic imped-
ance over a wide frequency range. This can be modified
to produce different frequency responses as needed. Al-
though the input of the DC1974 is single-ended, there is a
transformer on the board that translates the single-ended
signal to a differential signal to drive the ADC.
ANALOG INPUT NETWORK
In almost all cases, off board filters with good return loss
will be required on the analog input of the DC1974 to
produce data sheet SNR.
The off board filter should be located close to the input
of the demo board to avoid reflections from impedance
discontinuitiesatthedrivenend of a long transmission line.
Most filters do not present 50Ω outside the passband. In
some cases, 3dB to 10dB pads may be required to make
the filter look more like 50Ω to obtain low distortion.
Applyanencodeclockto the SMA connector on the DC1974
marked J3. By default, the DC1974 is configured to have
a single-ended clock input. Although the clock input of
the DC1974 is single-ended, there is a transformer on
the board that translates the single-ended signal to a dif-
ferential signal to drive the ADC.
For the best noise performance, the encode input must
be driven with a very low jitter signal generator source.
The amplitude should be as large as possible up to 2VPP
or 10dBm.
The DC1974 is designed to accept single-ended signals
by default. To modify the DC1974 to accept a differential
signal, remove C33, R44, R45 and R46. Populate R49,
R43, R48 and R47 with 0Ω resistors. Drive the demo
board with a differential signal on J3 and J4. These SMAs
are positioned 0.5" apart to accommodate LT C differential
clock boards.
ENCODE CLOCK

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DEMO MANUAL DC1974
The DC1974 is controlled by the PScope
™
System Soft-
ware provided or downloaded from the Linear Technology
website at http://www.linear.com/software/. If a Kintex 7
FPGA board and DC2159 were provided, follow the demo
manual of these boards for proper setup.
The Kintex 7 FPGA board will act as the data collection
board and the DC2159 is used to connect the FPGA to
the computer. These boards both are designed to work
seamlessly with PScope, Linear Technology’s data col-
lection software.
To start the data collection software and if “PScope.exe”
is installed (by default) at \Program Files\LT C \PScope\,
double click the PScope icon or bring up the run window
under the start menu and browse to the PScope directory
and select PScope.
If the DC1974 is properly connected to the Kintex 7 FPGA
boardandthe DC2159, PScope shouldautomaticallydetect
the DC1974 and configure itself accordingly. If necessary
the procedure below explains how to manually configure
PScope.
Under the “Configure” menu, go to “ADC Configuration...”
Check the “Config Manually” box and use the following
configuration options, shown in Figure 2:
Manual Configuration settings:
Bits: 14
Alignment: 16
Channs: 2
Bipolar: Unchecked
Positive-Edge Clk: Unchecked
If everything is hooked up properly, powered and a suit-
able encode clock is present, clicking the “Collect” button
should result in time and frequency plots displayed in
the PScope window. Additional information and help for
PScope is available in the KC705 guide and in the online
help available within the PScope program itself.
NOTE: If a PRBS error occurs hit connect again. This
is a bug in the first version of the software.
SERIAL PROGRAMMING
PScope has the ability to program the DC1974 board
serially through the DC2159. There are several options
available for the LTC2124 family that are only available
through serial programming. PScope allows all of these
features to be tested.
These options are available by first clicking on the “Set
Demo Bd Options” icon on the PScope toolbar (Figure 3).
This will bring up the menu shown in Figure 4.
SOFTWARE
Figure 2: ADC Configuration
Figure 3: PScope Toolbar

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DEMO MANUAL DC1974
This menu allows any of the options available for the
LTC2124 to be programmed serially. The LTC2124 family
has the following options:
Sleep Mode – Selects between normal operation and
sleep mode.
nOff (Default) – Entire ADC is powered and active.
nOn – The entire ADC is powered down.
Nap Mode – Selects between normal operation and
napmode.
n Off (Default) – Entire ADC is powered and active.
n On – The entire ADC is put into nap mode.
Channel B Power Down – Selects between normal opera-
tion and powering down channel B.
nOff (Default) – Normal operation.
nOn – Channel B is powered down.
Channel A Power Down – Selects between normal opera-
tion and powering down channel B.
nOff (Default) – Normal operation.
nOn – Channel A is powered down.
2x Clock – Selects between a sample rate equal to the
device clock, or device clock twice the sample rate.
nOff (Default) – DEVCLK is equal to the sample rate.
nOn – DEVCLK is twice the sample rate.
Overflow – Enables or disables the overflow bit in the
output data.
nDisabled (Default) – Over flow bit is disabled.
nEnabled – Overflow bit is enabled.
Duty Cycle Stabilizer – Enables or disables Duty Cycle
Stabilizer.
nStabilizeroff (Default)–Duty CycleStabilizerDisabled.
nStabilizer on – Duty Cycle Stabilizer Enabled.
Device ID – Sets the device ID defined in JESD204B 8.3.
Default is 00000000, but can be set to whatever the user
chooses.
Bank ID – Sets the bank ID defined in JESD204B 8.3. De-
fault is 0000, but can be set to whatever the user chooses.
Frames per MultiFrame – Selects number of frames in
each multiframe as defined in JESD204B 5.3.3.5. The user
selects the number of desired frames per multiframe and
PScope configures the ADC accordingly. Valid values for
number of frames per multiframe are 9 to 32.
Figure 4: Demo Bd Configuration Options
SOFTWARE

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DEMO MANUAL DC1974
Lane Alignment Sequence – Enables or disables the lane
alignment sequence.
nEnabled (Default) – Lane alignment sequence is
enabled.
nDisabled - Lane alignment sequence is disabled.
Lane Alignment Monitor – Enables or disables the lane
monitor sequence.
nEnabled(Default)–Lanealignment monitorsequence
is enabled.
nDisabled – Lane alignment monitor sequence is
disabled.
Frame Alignment Monitor –Enablesor disablesthe Frame
monitor sequence
nEnabled (Default) – Frame alignment monitor se-
quence is enabled.
nDisabled – Frame alignment monitor sequence is
disabled.
Reset Dividers (Subclass 1 or 2 Only) – Enables or dis-
ables SYSREF reset of dividers.
nEnabled(Default)–Subclass1–EnablestheSYSREF
reset of dividers. Subclass 2 – Enables SYNC~ reset
of dividers.
nDisabled – Subclass 1 – Disables the SYSREF reset
of dividers. Subclass 2 – Disables SYNC~ reset of
dividers.
Scrambling – Enables or disables the scrambling of the
output data.
nDisabled (Default) – Scrambling is disabled.
nEnabled – Scrambling is enabled.
Alert Mode De-arm Length (Subclass 1 Only) – Selects
the de-arming length in multiframe periods to trigger the
alert in subclass 1. Valid values are 1 to 8.
Alert Mode (Subclass 1 Only) – Enables or disables the
alert mode.
nDisabled (Default) – Alert mode is disabled.
nEnabled – Alert mode is enabled.
TX Sync – Enables or disables Transmitter induced syn-
chronization.
nDisabled (Default) – Transmitter induced synchro-
nization isdisabled.
nEnabled - Transmitter induced synchronization
isenabled.
Test Pattern – Selects the data presented at the output
of the ADC
Normal ADC Data (Default) – The data that is sampled
by the input of the ADC
K28.5 Pattern – A repeating SYNC comma.
K28.7 Pattern – 1111100000.
D21.5 Pattern – 1010101010.
PRBS15 Pattern – A Pseudorandom bit sequence pat-
tern described by 1 + x14 + x15.
Lane Alignment Sequence – The lane alignment se-
quence is transmitted according to tables 3a to 3h from
the datasheet.
Test Samples Sequence – The test samples are repeat-
edly transmitted according to tables 4a to 4b from the
datasheet.
Modified RPAT Pattern – A modified RPAT pattern as
described in IEEE Std. 802.3-2008 Annex 48A.
CML Output Magnitude – Magnitude of the CML out-
putsignals.
Value selections are:
10mA (250mV) Default
12mA (300mV)
14mA (350mV)
16mA (400mV)
Once the desired settings are selected hit OK and PScope
will automatically update the register of the device on the
DC1974 demo board.
SOFTWARE

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DEMO MANUAL DC1974
XILINX KC705 BASED EVALUATION SYSTEM
ThedemonstrationsystemfortheLTC2124familyconsists
of the DC1974, a Xilinx KC705 FPGA evaluation board, a
DC2159 USB communication board and a host PC running
the PScope software.
Complete systems that ship from Linear Technology will
have the KC705 board configured to automatically load
the default subclass 0 FPGA image from the onboard
configuration EEPROM. The procedure for bringing up
the system is as follows:
1) If the boards were obtained separately, assemble them
as shown in Figure 5 (FMC connectors are fragile, make
sure they are properly aligned before seating.)
2) Connect power supply to the KC705 board and turn on
thepowerswitch.If the assembled system was obtained
from Linear Technology, the subclass 0 image will load
automatically from the onboard configuration memory.
3) Boards not obtained from Linear Technology will need
to be configured as described in the Alternate FPGA
Configuration section below.
4) Apply power, encode clock and analog input signals to
the DC1974 board.
5) VerifythatPScopesoftwareis installed. Connect DC2159
to the host PC with a USB-mini cable. Driver installation
will start automatically and PScope will recognize the
DC1974 when installation finishes.
NOTE: Power must be applied to the KC705 board when
the USB cable is connected or the driver installation will
not complete properly.
ALTERNATE FPGA CONFIGURATION
KC705 boards not obtained from Linear Technology will
need to be configured via JTAG. FPGA images are located
in the PScope installation directory in the FPGA_images
folder. Connect a USB micro cable to the JTAG USB con-
nector on the KC705 board and use a Xilinx tool such as
Impact to load the Subclass 0, 2 lane bitfile. Once the
FPGA is configured, remove the USB cable and exit the
software. (The onboard JTAG adapter and the DC2159
USB communication board use the same USB controller
and they may interfere with one another.)
APPENDIX A

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DEMO MANUAL DC1974
5. CONNECT
DC2159
TO PC
1. ASSEMBLE BOARDS
4. POWER-UP
DC1974, TURN ON
CLOCK AND
ANALOG INPUTS
3. CONFIGURE
FPGA VIA JTAG
(IF NECESSARY),
THEN REMOVE
USB CABLE
2. POWER-UP
KC705
dc1974 F05
Figure 5. KC705 Based Demonstration System
APPENDIX A

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DEMO MANUAL DC1974
PARTS LIST
ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART #
Required Circuit Components
1 2 C1, C2 CAP., X5R, 1µF, 10V, 10%, 0402 AVX, 0402ZD105KAT2A
2 1 C3 CAP., TANT, 100µF, 10V, 10%, 6032 AVX, TAJW107K010RNJ
3 1 C4 CAP., X7R, 47µF,10V, 10%, 1210 MURATA, GRM32ER71A476KE15L
4 4 C5, C11, C25, C26 CAP., X5R, 2.2µF, 10V, 20%, 0603 AVX, 0603ZD225MAT2A
5 7 C6, C33-C35, C50-C52 CAP., X7R, 0.01µF, 16V, 10%, 0402 AVX, 0402YC103KAT2A
6 1 C7 CAP., X5R, 10µF, 6.3V, 20%, 0805 AVX, 08056D106MAT2A
7 22 C10, C12-C24, C27-C32, C41, C53 CAP., X5R, 0.1µF, 10V, 10%, 0402 AVX, 0402ZD104KAT2A
8 4 C37, C38, C39, C40 CAP., C0G, 47pF, 16V, 10%, 0402 AVX, 0402YA470KAT2A
9 8 C42-C49 CAP., X7R, 1000pF, 50V, 10%, 0402 AVX, 04025C102KAT2A
10 4 E1, E2, E3, E4 TESTPOINT, TURRET, 0.094" MILL-MAX, 2501-2-00-80-00-00-07-0
11 2 JP1, JP2 HEADER, HD1X3-079 SULLINS, NRPN031PAEN-RC
12 10 J1-J6, J9-J12 CONN., SMA 50Ω, EDGE-LAUNCH EF JOHNSON, 142-0701-851
13 0 J7, J8 (OPT) CONN., SMA 50Ω, EDGE-LAUNCH EF JOHNSON, 142-0701-851
14 1 J13 CONN., BGA 40X10 SAMTEC, SEAM-40-02.0-S-10-2-A-K-TR
15 1 L1 RES., CHIP, 0Ω, 1206 VISHAY, CRCW12060000Z0EA
16 1 L2 IND., FERRITE BEAD, 33Ω, 1206 MURATA, BLM31PG330SN1L
17 0 L3 RES., 1206 OPT
18 2 R1,R59 RES., CHIP, 3.01k, 1/16W, 1%, 0402 VISHAY, CRCW04023K01FKED
19 1 R2 RES., CHIP, 10k, 1/16W, 1%, 0402 VISHAY, CRCW040210K0FKED
20 1 R4 RES., CHIP, 182k, 1/16W, 1%, 0402 VISHAY, CRCW0402182KFKED
21 4 R5, R24, R25, R58 RES., CHIP, 1k, 1/16W, 1%, 0402 NIC, NRC04F1001TRF
22 10 R6-R11, R32-R35 RES., CHIP, 24.9Ω, 1/16W, 1%, 0402 VISHAY, CRCW040224R9FKED
23 11 R12, R13, R15, R16, R18, R39,
R40, R44, R45, R46, R57
RES., CHIP, 0Ω, 1/16W, 0402 NIC, NRC04Z0TRF
24 5 R14, R17, R41, R56, R61 RES., CHIP, 100Ω, 1/16W, 1%, 0402 NIC, NRC04F1000TRF
25 0 R19-R23, R42, R43, R48-R53,
R54, R55, R60
RES., 0402 OPT
26 2 R26, R29 RES., CHIP, 20Ω, 1/16W, 1%, 0402 NIC, NRC04F20R0TRF
27 2 R27, R28 RES., CHIP, 49.9Ω, 1/16W, 1%, 0402 VISHAY, CRCW040249R9FKED
28 2 R30, R31 RES., CHIP, 300Ω, 1/16W, 1%, 0402 NIC, NRC04F3000TRF
29 3 R36, R37,R38 RES., CHIP, 4.99k, 1/16W, 1%, 0402 VISHAY, CRCW04024K99FKED
30 5 R47, R62,R63,R64,R65 RES., CHIP, 4.99Ω, 1/16W, 1%, 0402 NIC, NRC04F4R99TRF
31 2 R66, R67 RES., CHIP, 100Ω, 1/20W, 1%, 0201 NIC, NRC02F1000TRF
32 3 T1, T2, T3 XFMR., MABA-007159-000000 M/A-COM, MABA-007159-000000
33 1 U2 I.C., LT3080EDD#PBF, DFN 3X3 LINEAR TECH., LT3080EDD#PBF
34 1 U3 I.C., LT1763CDE-3.3#PBF, DFN12DE-4X3 LINEAR TECH., LT1763CDE-3.3#PBF
35 1 U6 I.C. EEPROM 32KBIT 400KHz, TSSOP8 MICROCHIP, 24LC32A-I/ST

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DEMO MANUAL DC1974
ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART #
36 1 U7 I.C., NC7WZ14P6X, SC70-6 FAIRCHILD SEMI., NC7WZ14P6X
37 1 U9 I.C., LTC6957IDD-2#PBF, DFN12DD-3X3 LINEAR TECH., LTC6957IDD-2#PBF
38 1 SHUNTS FOR JP1 & JP2 SHUNT, 0.079" CENTER SAMTEC, 2SN-BK-G
39 0 MH1, MH2 SCREW, M3 THREAD, #4-40x5/8" KEYSTONE, 29316 (DO NOT INSTALL)
40 0 MH1, MH2 STAND-OFF, ALUM., M3 THREAD, 5.0 HEX,
#4-40X1"
KEYSTONE, 24438 (DO NOT INSTALL)
41 2 STENCILS STENCILS (TOP & BOTTOM) STENCIL DC1974A-3
DC1974A-A Required Circuit Components
1 1 DC1974A GENERAL BOM
2 1 U1 I.C., 14-BIT, 310Msps, QFN48UK-7X7 LINEAR TECH., LTC2124IUK#PBF
DC1974A-B Required Circuit Components
1 1 DC1974A GENERAL BOM
2 1 U1 I.C., 14-BIT, 250Msps, QFN48UK-7X7 LINEAR TECH., LTC2123IUK#PBF
DC1974A-C Required Circuit Components
1 1 DC1974A GENERAL BOM
2 1 U1 I.C., 14-BIT, 170Msps, QFN48UK-7X7 LINEAR TECH., LTC2122IUK#PBF
PARTS LIST

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DEMO MANUAL DC1974
SCHEMATIC DIAGRAM
5
5
4
4
3
3
2
2
1
1
D D C C B B A A
ASSY
LTC2123IUK-14
U1
LTC2122IUK-14
*250
170
Msps
-A LTC2124IUK-14 310
GND
V+
4V - 6V
ALL CAPACITORS ARE IN MICROFARADS, 0402.
NOTES: UNLESS OTHERWISE SPECIFIED 2. INSTALL SHUNTS AS SHOWN. 1. ALL RESISTORS ARE IN OHMS, 0402. -Bit
14 14 14
-B -C
C42 - C49
1000pF
SYNC
0 1
CML* CONNECTIONS ARE 50 OHMS
3. R18 IS OPTIONAL AT THE FINAL VERSION.
SENSE
AINB- AINB+ AINA- AINA+
VCM
CLK- CLK+
V+ +3.3V
V+
VDD
VDD
VDD
VDD
VDDVDD
VDD
OVDD
OVDD
VDD
OVDD
OVDD
VDD
VDD
VDD
+3.3V
VDD
+3.3V +3.3V
CMLB1_N CMLB1_P SYNC_N SYNC_P CMLB2_N CMLB2_P CMLA2_P CMLA1_N CMLA1_P CMLA2_N OF+ OF- CS SCK SDI SDO
FPGA_CLK_P FPGA_CLK_N
REVISION HISTORY DESCRIPTION DATEAPPROVEDECO REV
CLARENCE M.PRODUCTION3 07-31-14
__
REVISION HISTORY DESCRIPTION DATEAPPROVEDECO REV
CLARENCE M.PRODUCTION3 07-31-14
__
REVISION HISTORY DESCRIPTION DATEAPPROVEDECO REV
CLARENCE M.PRODUCTION3 07-31-14
__
SIZE DATE:
IC NO. REV.
SHEET OF
TITLE:
APPROVALS
PCB DES.
APP ENG.
TECHNOLOGY Fax: [phone]
Milpitas, CA 95035 Phone: [phone] McCarthy Blvd. LTC Confidential-For Customer Use Only
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SCHEMATIC
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
SCALE = NONE
www.linear.com
3
DEMO CIRCUIT 1974A
Thursday, July 31, 2014
12
N/A LTC212XIUK FAMILY
KIM T.
CLARENCE M.
DUAL 14-BIT HIGH SPEED ADC
WITH JESD204B SERIAL OUTPUTS
SIZE DATE:
IC NO. REV.
SHEET OF
TITLE:
APPROVALS
PCB DES.
APP ENG.
TECHNOLOGY Fax: [phone]
Milpitas, CA 95035 Phone: [phone] McCarthy Blvd. LTC Confidential-For Customer Use Only
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SCHEMATIC
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
SCALE = NONE
www.linear.com
3
DEMO CIRCUIT 1974A
Thursday, July 31, 2014
12
N/A LTC212XIUK FAMILY
KIM T.
CLARENCE M.
DUAL 14-BIT HIGH SPEED ADC
WITH JESD204B SERIAL OUTPUTS
SIZE DATE:
IC NO. REV.
SHEET OF
TITLE:
APPROVALS
PCB DES.
APP ENG.
TECHNOLOGY Fax: [phone]
Milpitas, CA 95035 Phone: [phone] McCarthy Blvd. LTC Confidential-For Customer Use Only
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SCHEMATIC
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
SCALE = NONE
www.linear.com
3
DEMO CIRCUIT 1974A
Thursday, July 31, 2014
12
N/A LTC212XIUK FAMILY
KIM T.
CLARENCE M.
DUAL 14-BIT HIGH SPEED ADC
WITH JESD204B SERIAL OUTPUTS
J9
FPGA_CLK_N
SMA
J9
FPGA_CLK_N
SMA
J5
ADC_SYS_REF_N
SMA
J5
ADC_SYS_REF_N
SMA
R46
0
R46
0
R22 OPT R22 OPT
R12
0
R12
0
R1 3.01k R1 3.01k
L1
0 Ohm RES
1206
L1
0 Ohm RES
1206
C50
0.01uF
C50
0.01uF
E3
SENSE
E3
SENSE
C5 2.2uF 0603 C5 2.2uF 0603
E4
1.8V OUT
E4
1.8V OUT
R48 OPT R48 OPT
R67 100 0201 R67 100 0201
R29 20 R29 20
J10
FPGA_CLK_P
SMA
J10
FPGA_CLK_P
SMA
J6
ADC_SYS_REF_P
SMA
J6
ADC_SYS_REF_P
SMA
R25
1k
R25
1k
R44
0
R44
0
R39
0
R39
0
R40
0
R40
0
R41 100 R41 100
T3
MABA-007159-000000
T3
MABA-007159-000000
5 4 3
1
2
R47 4.99 R47 4.99
R13
0
R13
0
R66 100 0201 R66 100 0201
R20 OPT R20 OPT
R10 45.3 R10 45.3
C11 2.2uF 0603 C11 2.2uF 0603
R14 100 R14 100
R27 49.9 R27 49.9
R54 OPT R54 OPT
T1
MABA-007159-000000
T1
MABA-007159-000000
5 4 3
1
2
R64
4.99
R64
4.99
R50 OPT R50 OPT
E1E1
C14 0.1uF C14 0.1uF
R28 49.9 R28 49.9
C24 0.1uF C24 0.1uF R7
45.3 R7 45.3
C34
0.01uF
C34
0.01uF
R49 OPT R49 OPT
C7 10uF 0805 C7 10uF 0805
C26 2.2uF 0603 C26 2.2uF 0603
U1 *
QFN48UK-7X7
U1 *
QFN48UK-7X7
VDD
1
GND
2
AINA+
3
AINA-
4
SENSE
5
VREF
6
VCM
7
GND
8
AINB-
9
AINB+
10
GND
11
VDD
12
VDD
13
GND
14
DEVCLK-
15
DEVCLK+
16
GND
17
SYSREF_P
18
SYSREF_N
19
GND
20
SYNC_P
21
SYNC_N
22
VDD
23
VDD
24
OVDD
25
OVDD
26
CMLB2_N
27
CMLB2_P
28
CMLB1_N
29
CMLB1_P
30
CMLA1_N
31
CMLA1_P
32
CMLA2_N
33
CMLA2_P
34
OVDD
35
OVDD
36
VDD
37
VDD
38
DNC
39
DNC
40
OFN-
41
OFN+
42
SDO
43
SDI
44
SCK
45
CS
46
GND
47
VDD
48
GND
49
L2
33 Ohm FB
1206
L2
33 Ohm FB
1206
T2
MABA-007159-000000
T2
MABA-007159-000000
5 4 3
1
2
C6 0.01uF C6 0.01uF
C35
0.01uF
C35
0.01uF
C4 47uF 1210 C4 47uF 1210
C51
0.01uF
C51
0.01uF
U3 LT1763CDE-3.3 U3 LT1763CDE-3.3
OUT
2
OUT
3
EP
13
SHDN
8
NC
9
GND
7
IN
10
IN
11
SENSE
5
NC
4
NC
1
NC
12
BYP
6
C32 0.1uF C32 0.1uF
R16
0
R16
0
R30
300
R30
300
J2
AINB
SMA
J2
AINB
SMA
C15 0.1uF C15 0.1uF
C53
0.1uF
C53
0.1uF
R56 100 R56 100
C17 0.1uF C17 0.1uF
L3
OPT
1206
L3
OPT
1206
C19 0.1uF C19 0.1uF
C13 0.1uF C13 0.1uF
C25 2.2uF
0603
C25 2.2uF
0603
C16 0.1uF C16 0.1uF
R18 0
[3]
R18 0
[3]
C18 0.1uF C18 0.1uF
R21 OPT R21 OPT
R60 OPT R60 OPT
C27
0.1uF
C27
0.1uF
R2 10k R2 10k
C33
0.01uF
C33
0.01uF
J1
AINA
SMA
J1
AINA
SMA
R63 4.99 R63 4.99
U9
LTC6957IDD-2
U9
LTC6957IDD-2
GND
5
IN-
4
IN+
3
V+
2
FILTA
1
OUT1-
10
OUT2-
9
OUT2+
8
SD2
7
FILTB
6
OUT1+
11
SD1
12
EP
13
R45
0
R45
0
C23
0.1uF
C23
0.1uF
+
C3 100uF 10V 6032
+
C3 100uF 10V 6032
R6 45.3 R6 45.3
C52
0.01uF
C52
0.01uF
R24
1k
R24
1k
R4 182K R4 182K
GNDVCC
U7 NC7WZ14P6X
GNDVCC
U7 NC7WZ14P6X
16
4 3 5 2
J4
DEVCLK+
SMA
J4
DEVCLK+
SMA
C10 0.1uF C10 0.1uF
R11 45.3 R11 45.3
C31 0.1uF C31 0.1uF
JP2JP2
1 3 2
C30
0.1uF
C30
0.1uF
R15
0
R15
0
C2 1uF C2 1uF
C21 0.1uF C21 0.1uF
R5 1k R5 1k
R42 OPT R42 OPT R26
20 R26 20
C28
0.1uF
C28
0.1uF
R23 OPT R23 OPT
R62 4.99 R62 4.99
E2E2
R9
24.9
R9
24.9
R8
24.9
R8
24.9
R43 OPT R43 OPT
R17 100 R17 100
R19 OPT R19 OPT
C20 0.1uF C20 0.1uF
C1 1uF C1 1uF
C12 0.1uF C12 0.1uF
R65 4.99 R65 4.99
R61 100 R61 100
R55 OPT R55 OPT
R52 OPT R52 OPT
R31
300
R31
300
C22
0.1uF
C22
0.1uF
R53 OPT R53 OPT
LT3080EDD U2 LT3080EDD U2
OUT
1
OUT
2
OUT
3
SET
4
VCTRL
5
NC
6
IN
7
IN
8
EP
9
J3
DEVCLK-
SMA
J3
DEVCLK-
SMA
C29 0.1uF C29 0.1uF
R51 OPT R51 OPT

13
dc1974f
DEMO MANUAL DC1974
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
SCHEMATIC DIAGRAM
5
5
4
4
3
3
2
2
1
1
D D C C B B A A
EEPROM
WP
PROG
CS_FMC
SCL SDA
SCK_FMC SDI_FMC SDO_FMC
3P3VAUX
VDD
+3.3V CS
SDO SDI SCK
CMLA2_P CMLA2_N CMLB1_N CMLB1_P CMLB2_N CMLB2_P
CMLA1_P CMLA1_N
SYNC_P SYNC_N OF+ OF-
FPGA_CLK_P FPGA_CLK_N
SIZE DATE:
IC NO. REV.
SHEET OF
TITLE:
APPROVALS
PCB DES.
APP ENG.
TECHNOLOGY Fax: [phone]
Milpitas, CA 95035 Phone: [phone] McCarthy Blvd. LTC Confidential-For Customer Use Only
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SCHEMATIC
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
SCALE = NONE
www.linear.com
3
DEMO CIRCUIT 1974A
Thursday, July 31, 2014
22
N/A LTC212XIUK FAMILY
KIM T.
CLARENCE M.
DUAL 14-BIT HIGH SPEED ADC
WITH JESD204B SERIAL OUTPUTS
SIZE DATE:
IC NO. REV.
SHEET OF
TITLE:
APPROVALS
PCB DES.
APP ENG.
TECHNOLOGY Fax: [phone]
Milpitas, CA 95035 Phone: [phone] McCarthy Blvd. LTC Confidential-For Customer Use Only
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SCHEMATIC
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
SCALE = NONE
www.linear.com
3
DEMO CIRCUIT 1974A
Thursday, July 31, 2014
22
N/A LTC212XIUK FAMILY
KIM T.
CLARENCE M.
DUAL 14-BIT HIGH SPEED ADC
WITH JESD204B SERIAL OUTPUTS
SIZE DATE:
IC NO. REV.
SHEET OF
TITLE:
APPROVALS
PCB DES.
APP ENG.
TECHNOLOGY Fax: [phone]
Milpitas, CA 95035 Phone: [phone] McCarthy Blvd. LTC Confidential-For Customer Use Only
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SCHEMATIC
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
SCALE = NONE
www.linear.com
3
DEMO CIRCUIT 1974A
Thursday, July 31, 2014
22
N/A LTC212XIUK FAMILY
KIM T.
CLARENCE M.
DUAL 14-BIT HIGH SPEED ADC
WITH JESD204B SERIAL OUTPUTS
R32
24.9
R32
24.9
J12
FPGA_SYS_REF_N
SMA
J12
FPGA_SYS_REF_N
SMA
J13J
SEAM-10X40PIN
J13J
SEAM-10X40PIN
GND
J1
CLK1_C2M_P
J2
CLK1_C2M_N
J3
GND
J4
GND
J5
HA03_P
J6
HA03_N
J7
GND
J8
HA07_P
J9
HA07_N
J10
GND
J11
HA11_P
J12
HA11_N
J13
GND
J14
HA14_P
J15
HA14_N
J16
GND
J17
HA18_P
J18
HA18_N
J19
GND
J20
HA22_P
J21
HA22_N
J22
GND
J23
HB01_P
J24
HB01_N
J25
GND
J26
PB07_P
J27
HB07_N
J28
GND
J29
HB11_P
J30
HB11_N
J31
GND
J32
HB15_P
J33
HB15_N
J34
GND
J35
HB18_P
J36
HB18_N
J37
GND
J38
VIO_B_M2C
J39
GND
J40
R33 24.9 R33 24.9
R37
4.99K
R37
4.99K
J13E
SEAM-10X40PIN
J13E
SEAM-10X40PIN
GND
E1
HA01_P_CC
E2
HA01_N_CC
E3
GND
E4
GND
E5
HA05_P
E6
HA05_N
E7
GND
E8
HA09_P
E9
HA09_N
E10
GND
E11
HA13_P
E12
HA13_N
E13
GND
E14
HA16_P
E15
HA16_N
E16
GND
E17
HA20_P
E18
HA20_N
E19
GND
E20
HB03_P
E21
HB03_N
E22
GND
E23
HB05_P
E24
HB05_N
E25
GND
E26
HB09_P
E27
HB09_N
E28
GND
E29
HB13_P
E30
HB13_N
E31
GND
E32
HB21_P
E33
HB21_N
E34
GND
E35
HB20_P
E36
HB20_N
E37
GND
E38
VADJ
E39
GND
E40
SCKSCK
J13A SEAM-10X40PIN J13A SEAM-10X40PIN
GND
A1
DP1_M2C_P
A2
DP1_M2C_N
A3
GND
A4
GND
A5
DP2_M2C_P
A6
DP2_M2C_N
A7
GND
A8
GND
A9
DP3_M2C_P
A10
DP3_M2C_N
A11
GND
A12
GND
A13
DP4_M2C_P
A14
DP4_M2C_N
A15
GND
A16
GND
A17
DP5_M2C_P
A18
DP5_M2C_N
A19
GND
A20
GND
A21
DP1_C2M_P
A22
DP1_C2M_N
A23
GND
A24
GND
A25
DP2_C2M_P
A26
DP2_C2M_N
A27
GND
A28
GND
A29
DP3_C2M_P
A30
DP3_C2M_N
A31
GND
A32
GND
A33
DP4_C2M_P
A34
DP4_C2M_N
A35
GND
A36
GND
A37
DP5_C2M_P
A38
DP5_C2M_N
A39
GND
A40
C40 47pF C40 47pF
J7
FPGA_GBT_REF_P
SMA
OPT
J7
FPGA_GBT_REF_P
SMA
OPT
C39 47pF C39 47pF
J13K
SEAM-10X40PIN
J13K
SEAM-10X40PIN
VREF_B_M2C
K1
GND
K2
GND
K3
CLK1_M2C_P
K4
CLK1_M2C_N
K5
GND
K6
HA02_P
K7
HA02_N
K8
GND
K9
HA06_P
K10
HA06_N
K11
GND
K12
HA10_P
K13
HA10_N
K14
GND
K15
HA17_P_CC
K16
HA17_N_CC
K17
GND
K18
HA21_P
K19
HA21_N
K20
GND
K21
HA23_P
K22
HA23_N
K23
GND
K24
HB00_P_CC
K25
HB00_N_CC
K26
GND
K27
HB06_P_CC
K28
HB06_N_CC
K29
GND
K30
HB10_P
K31
HB10_N
K32
GND
K33
HB14_P
K34
HB14_N
K35
GND
K36
HB17_P_CC
K37
HB17_N_CC
K38
GND
K39
VIO_B_M2C
K40
R36 4.99K R36 4.99K
SDOSDO
J13F
SEAM-10X40PIN
J13F
SEAM-10X40PIN
PG_M2C
F1
GND
F2
GND
F3
HA00_P_CC
F4
HA00_N_CC
F5
GND
F6
HA04_P
F7
HA04_N
F8
GND
F9
HA08_P
F10
HA08_N
F11
GND
F12
HA12_P
F13
HA12_N
F14
GND
F15
HA15_P
F16
HA15_N
F17
GND
F18
HA19_P
F19
HA19_N
F20
GND
F21
HB02_P
F22
HB02_N
F23
GND
F24
HB04_P
F25
HB04_N
F26
GND
F27
HB08_P
F28
HB08_N
F29
GND
F30
HB12_P
F31
HB12_N
F32
GND
F33
HB16_P
F34
HB16_N
F35
GND
F36
HB19_P
F37
HB19_N
F38
GND
F39
VADJ
F40
J8
FPGA_GBT_REF_N
SMA
OPT
J8
FPGA_GBT_REF_N
SMA
OPT
JP1JP1
1 3 2
GNDGND
R58 1k R58 1k
J13B
SEAM-10X40PIN
J13B
SEAM-10X40PIN
RES1
B1
GND
B2
GND
B3
DP9_M2C_P
B4
DP9_M2C_N
B5
GND
B6
GND
B7
DP8_M2C_P
B8
DP8_M2C_N
B9
GND
B10
GND
B11
DP7_M2C_P
B12
DP7_M2C_N
B13
GND
B14
GND
B15
DP6_M2C_P
B16
DP6_M2C_N
B17
GND
B18
GND
B19
GBTCLK1_M2C_P
B20
GBTCLK1_M2C_N
B21
GND
B22
GND
B23
DP9_C2M_P
B24
DP9_C2M_N
B25
GND
B26
GND
B27
DP8_C2M_P
B28
DP8_C2M_N
B29
GND
B30
GND
B31
DP7_C2M_P
B32
DP7_C2M_N
B33
GND
B34
GND
B35
DP6_C2M_P
B36
DP6_C2M_N
B37
GND
B38
GND
B39
RES0
B40
C37 47pF C37 47pF
J13G SEAM-10X40PIN J13G SEAM-10X40PIN
GND
G1
CLK0_C2M_P
G2
CLK0_C2M_N
G3
GND
G4
GND
G5
LA00_P_CC
G6
LA00_N_CC
G7
GND
G8
LA03_P
G9
LA03_N
G10
GND
G11
LA08_P
G12
LA08_N
G13
GND
G14
LA12_P
G15
LA12_N
G16
GND
G17
LA16_P
G18
LA16_N
G19
GND
G20
LA20_P
G21
LA20_N
G22
GND
G23
LA22_P
G24
LA22_N
G25
GND
G26
LA25_P
G27
LA25_N
G28
GND
G29
LA29_P
G30
LA29_N
G31
GND
G32
LA31_P
G33
LA31_N
G34
GND
G35
LA33_P
G36
LA33_N
G37
GND
G38
VADJ
G39
GND
G40
R57 0 R57 0
SDISDI
J13C
SEAM-10X40PIN
J13C
SEAM-10X40PIN
GND
C1
DP0_C2M_P
C2
DP0_C2M_N
C3
GND
C4
GND
C5
DP0_M2C_P
C6
DP0_M2C_N
C7
GND
C8
GND
C9
LA06_P
C10
LA06_N
C11
GND
C12
GND
C13
LA10_P
C14
LA10_N
C15
GND
C16
GND
C17
LA14_P
C18
LA14_N
C19
GND
C20
GND
C21
LA18_P_CC
C22
LA18_N_CC
C23
GND
C24
GND
C25
LA27_P
C26
LA27_N
C27
GND
C28
GND
C29
SCL
C30
SDA
C31
GND
C32
GND
C33
GA0
C34
12P0V
C35
GND
C36
12P0V
C37
GND
C38
3P3V
C39
GND
C40
R35 24.9 R35 24.9
R59 3.01k R59 3.01k
R34 24.9 R34 24.9
CSCS
J13H
SEAM-10X40PIN
J13H
SEAM-10X40PIN
VREF_A_M2C
H1
PRSNT_M2C_N
H2
GND
H3
CLK0_M2C_P
H4
CLK0_M2C_N
H5
GND
H6
LA02_P
H7
LA02_N
H8
GND
H9
LA04_P
H10
LA04_N
H11
GND
H12
LA07_P
H13
LA07_N
H14
GND
H15
LA11_P
H16
LA11_N
H17
GND
H18
LA15_P
H19
LA15_N
H20
GND
H21
LA19_P
H22
LA19_N
H23
GND
H24
LA21_P
H25
LA21_N
H26
GND
H27
LA24_P
H28
LA24_N
H29
GND
H30
LA28_P
H31
LA28_N
H32
GND
H33
LA30_P
H34
LA30_N
H35
GND
H36
LA32_P
H37
LA32_N
H38
GND
H39
VADJ
H40
C41 0.1uF C41 0.1uF
R38
4.99K
R38
4.99K
J13D SEAM-10X40PIN J13D SEAM-10X40PIN
PG_C2M
D1
GND
D2
GND
D3
GBTCLK0_M2C_P
D4
GBTCLK0_M2C_N
D5
GND
D6
GND
D7
LA01_P_CC
D8
LA01_N_CC
D9
GND
D10
LA05_P
D11
LA05_N
D12
GND
D13
LA09_P
D14
LA09_N
D15
GND
D16
LA13_P
D17
LA13_N
D18
GND
D19
LA17_P_CC
D20
LA17_N_CC
D21
GND
D22
LA23_P
D23
LA23_N
D24
GND
D25
LA26_P
D26
LA26_N
D27
GND
D28
TCK
D29
TDI
D30
TDO
D31
3P3VAUX
D32
TMS
D33
TRST_N
D34
GA1
D35
3P3V
D36
GND
D37
3P3V
D38
GND
D39
3P3V
D40
C38 47pF C38 47pF
EEPROM
ARRAY
U6 24LC32A
EEPROM
ARRAY
U6 24LC32A
SDA
5
VCC
8
A0
1
A1
2
A2
3
GND
4
WP
7
SCL
6
J11
FPGA_SYS_REF_P
SMA
J11
FPGA_SYS_REF_P
SMA

14
dc1974f
DEMO MANUAL DC1974
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
[phone] ●FAX: [phone] ●www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2014
LT 1114 • PRINTED IN USA
DEMONSTRATION BOARD IMPORTANT NOTICE
Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions:
This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT
OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete
in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety
measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union
directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.
If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date
of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU
OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS
FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR
ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims
arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all
appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or
agency certified (FCC, UL, CE, etc.).
No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance,
customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive.
Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and
observe good laboratory practice standards. Common sense is encouraged.
This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application
engineer.
Mailing Address:
Linear Technology
1630 McCarthy Blvd.
Milpitas, CA 95035
Copyright © 2004, Linear Technology Corporation