DESCRIPTION
There is a demonstration board available for the
LTC1067/LTC1067-50. Demonstration board 150A
has the LTC1067 part installed and the board 150B
has the LTC1067-50 installed. The schematic for
the board is shown in Figure 15 and the assembly
drawing is shown in Figure 16. To obtain a demon-
stration board, call your local representative or Lin-
ear Technology’s marketing department. The
demonstration board has all integrated circuits,
connectors and decoupling capacitors installed.
The board is ready to be configured with the ap-
propriate resistors and jumper connections. There
are two sets of power supply connections. One is
for the LTC1067/LTC1067-50 and the other is for
the buffering op amp on the board. Having separate
connections gives the board the most flexibility. The
two sets of supplies can be connected together if a
common supply is desired. When configuring the
board for split supply operation, a jumper wire must
be installed in the JPAGND position. This connects
theAGND pin of the device to the ground plane of
the board. The JPVNEG jumper must be left open.
The power supply is then connected to V+, V –and
GND turrets (all of the GND turrets on the board
are the same). For single supply operation, insert a
wire in the JPVNEG jumper and leave the JPAGND
jumper open. This connects the V –pin to the
board’s ground plane. The JPAGND jumper must
be left open so that the on-chip resistor network
can set theAGND potential at the midpoint of the
supply. Connect the power supply to V+ and any
GND turret.
The V –turret can be left open or shorted to the
adjacent GND turret. If the buffering op amp is run
on the same single voltage supply, the VOA+ turret
and the V+ turrets must be connected together and
the VOA –turret must be shorted to the adjacent
GND turret.
The J1 BNC connector is the clock input. There is a
200W series resistor connected between the con-
nector and the CLK pin of the part. This resistor,
coupled with the CLK pin’s input capacitance, slows
down the rise and fall times of the clock signal and
decreases high frequency coupling. The clock in-
put is not terminated to 50W or 75W. An external
terminator should be used. Jumpers JP51 and
JP61 are connected in parallel with R51 and R61
respectively. Jumper JP51 connects the LPApin of
the part with the SApin. This can be used for oper-
ating modes 1 or 2.Alternatively, a 0W resistor in
the R51 position fulfills the same requirement. The
JP61
jumper connects the SA pin of the part to
the AGND pin.
This would be used for operating
Mode 3. Here, a 0W resistor in the R61 position
also works. Jumpers JP52 and JP62 perform the
same functions on the B side of the part. The buff-
ering amplifier can be configured for inverting or
noninverting operation. For inverting applications,
connect jumper JP2 positions 1 and 2.Additionally,
connect jumper JP4 for split supply applications or
JP8 for a single supply. For a noninverting applica-
tion, connect jumper JP2 positions 2 and 3.
Several other jumpers should be connected as fol-
lows:
JP1: Install a jumper wire from position 1 to position
2, leave the other positions open.
JP5: Install a jumper wire if split supply, leave open
if single supply.
JP6: Leave open.
JP7: Install a jumper wire.
JP9: Install a jumper wire if single supply, leave
open if split supply.
