Linear Technology DC2191A Quick setup guide

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DEMO MANUAL DC2191A
DESCRIPTION
RF Transmitter Using LTC2000
16-Bit, 2.5Gsps to 2.7Gsps DAC
Demonstration circuit 2191A supports the LT C
®
2000, a
high speed, high dynamic range DAC driving the LT5579
upconverting mixer.
The circuitry on the DAC IF output is optimized for analog
frequenciesfromDCto500MHz.Thecircuitry on the LO input
is optimized for frequencies from 1000MHz to 4300MHz.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
PERFORMANCE SUMMARY
The circuitry on the RF output is optimized for frequencies
from 2200MHz to 2600MHz.
Design files for this circuit board are available at
http://www.linear.com/demo/DC2191
Specifications are at TA= 25°C
PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply Voltage – DC2191 This supply must provide up to 1100mA 4.8 5.0 5.2 V
Sampling Frequency (Sample Clock Frequency)* 300 2500 or 2700 MHz
Sample Clock Level (Single-Ended) Use a 50Ω Source 0 15 dBm
LVDS Inputs Differential Input Voltage Range
Common Mode Voltage Range
±0.2
0.4
±0.6
1.8
V
V
LO Input Frequency Range 750 4300 MHz
*DC2191A-A Features the LTC2000-16, 16-Bit, 2.5Gsps DAC

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DEMO MANUAL DC2191A
QUICK START PROCEDURE
DC2191 is easy to set up to evaluate the performance of the
LTC2000 + LT5579. Refer to Figure 1 for proper measure-
ment equipment set-up and follow the procedure below.
SOFTWARE
The software for the DC2191, LTDACGen is available at
www.linear.com/LTDACGEN free of charge. It simplifies
the creation of complex waveforms and loading them into
the FPGA to test the DC2191. For more information about
how to use the LTDACGen software, refer to the help files
that come with the software.
APPLYING POWER AND SIGNALS TO THE DC2191
DEMONSTRATION CIRCUIT
If a Stratix IV demo board is used to supply data to the
DC2191, the two boards should first be bolted together and
a proper connection should be made. If Linear Technology
provided the Stratix IV board the proper bit file is already
installed in flash memory and will begin to operate when
the board is powered on. If an unprogrammed FPGA board
is used, refer to the Stratix IV GX Development Board
Reference Manual on how to program it.
Power should be applied to the system in this order:
1. Connect the Altera board to the provided power supply.
2. Connect the USB cable to J7.
3. Apply a clock to J4.
4. Connect an LO source to J6.
5. Turn on the voltage to the Altera board.
6. Connect the 5V from a bench supply to the +5V turret
on the DC2191.
7. Open the LTDACGen software and hit connect.
LTDACGen should report back that it is connected to the
FPGA. See Figure 2:

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DEMO MANUAL DC2191A
QUICK START PROCEDURE
Figure 1. DC2191 Setup (zoom for details)
SINGLE-ENDED
SAMPLE CLOCK INPUT
CONNECT USB TO PC
RUNNING LTDACGen SOFTWARE
JUMPERS SHOWN IN THEIR DEFAULT POSITIONS
THE DC2191 CONNECTS TO THE ALTERA STRATIX IV
GX FPGA DEVELOPMENT BOARD VIA HSMC CONNECTORS
5V
RF OUTPUT
LO INPUT
+

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DEMO MANUAL DC2191A
QUICK START PROCEDURE
Figure 2. LTDACGen Connected to FPGA

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DEMO MANUAL DC2191A
QUICK START PROCEDURE
Figure 3. Default Frequency

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DEMO MANUAL DC2191A
QUICK START PROCEDURE
ANALOG OUTPUT NETWORK
The analog output network of the DC2191 has been de-
signed to maximize the performance of the LTC2000. The
LTC2000 drives a chebyshev lowpass filter with a corner
at 500MHz.
SAMPLE CLOCK
The sample clock to the DC2191 demonstration circuit
board is marked J4. As a default it is a single-ended 50Ω
input port. There is an onboard balun that does a single-
ended to differential translation.
For the best noise performance, the sample input must
be driven with a very low jitter signal generator source.
The amplitude should be as large as possible up to ±1.8V
or 9dBm.
RESULTS
After everything is set up and the software is con-
nected to the DAC demo system, a sine wave can be
added to the output waveform. The default frequency is
399.932861328MHz (Figure 3). By clicking Update FPGA,
the data is sent to the FPGA and is then used to program
the DAC. A spectrum analyzer can then be used to view
the results at J5.
HARDWARE SETUP
SMAs
J2 & J3: Differential Trigger Input. Apply a signal to J2 from
a50Ω driver. Absorptive filters are required for data sheet
performance. UseJ2andJ3ifthe triggerisadifferentialsignal.
J4: Sample Clock Input. Apply a clock signal to this SMA
connector from a 50Ω driver. A 0dBm clock source should
be sufficient, but for best phase noise and jitter perfor-
mance, use the highest possible amplitude and slew rate.
J5: RF Output Signal. This is the upconverted output of
the DAC if the output impedance is 50Ω. Connect to a
spectrum analyzer.
J6: LO Input Signal. This is the local oscillator input to
the upconverting mixer. Nominal power level is 0dBm.
J8: SYNC. This SMA is to provide access to the sync pin
of the LT8614. It is not used in normal use.
Turrets
+5V: Positive Input Voltage for the DAC, Mixer, and Digital
Circuits. This voltage feeds a series of regulators that supply
the proper voltages for the DAC. The voltage range for this
turret is 4.8V to 5.2V. Note: For close-in phase noise plots,
driving this voltage is not ideal. There is a known 20kHz noise
hump in the spectrum that is generated by the regulators. For
the best phase noise performance, back drive the onboard
regulators with the provided turrets from a low noise supply.
GND: Ground Connection. This demo board has only a
single ground plane. This turret should be tied to the GND
terminal of the power supply being used.
SVDD3V0: Optional 3.0V Input. This pin is connected
directly to the SVDD pin of the DAC. It requires a supply
that can deliver up to 100mA. Driving this pin will shut
down the onboard regulator.
AVDD3V3: Optional 3.3V Input. This pin is connected
directly to the AVDD33 pin of the DAC. It requires a supply
that can deliver up to 450mA. Driving this pin will shut
down the onboard regulator.
DVDD3V3: Optional 3.3V Input. This pin is connected
directly to the DVDD33 pin of the DAC. It requires a sup-
ply that can deliver up to 50mA. Driving this pin will shut
down the onboard regulator.
AVDD1V8: Optional 1.8V Input. This pin is connected
directly to the AVDD18 pin of the DAC. It requires a supply
that can deliver up to 1A. Driving this pin will shut down
the onboard regulator.
DVDD1V8: Optional 1.8V Input. This pin is connected
directly to the DVDD18 pin of the DAC. It requires a supply
that can deliver up to 500mA. Driving this pin will shut
down the onboard regulator.

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DEMO MANUAL DC2191A
VP1: This is a test point that is at the output of the on-
board switching regulator. It is meant for test purposes.
It can also be driven to 2.5V to shut down the output of
the switching regulator.
TSTP & TSTN: These pins are tied directly to the TSTP
and TSTN pins of the DAC. They can be used to measure
the internal temperature and timing of the LVDS inputs.
FSADJ: This is an optional pin that is tied directly to the
FSADJ pin of the DAC. It can be used to set the full-scale
output current of the DAC. In normal operation this pin
is tied to GND through 500Ω to set a current of 40mA at
the output.
REFIO: This pin is tied directly to the REFIO pin of the
DAC and is used to set the reference voltage for the DAC.
Normally it is internally set to 1.25V but can be overdriven
with an external voltage from 1.1V to 1.4V.
Jumpers
The DC2191 demonstration circuit should have the fol-
lowing jumper settings as default positions.
JP1: PD. In the RUN position this pin results in normal
operation of the DAC. In the SHDN position the DAC is
powered down. (Default: RUN or up)
JP2: SPI and JTAG. This jumper selects how the FPGA is
programmed. In the SPI position the FPGA is programmed
from the onboard FTDI chip and the LTDACGen software.In
the JTAG position the J9 is used with a JTAG programmer
to program the FPGA. (Default: SPI or down)
Connectors
J1: DC590. This is an optional header that can be used
to program the DAC with the DC590. (Default: removed)
J9: JTAG. This is an optional header that can be used to
program the FPGA through a JTAG programmer. (Default:
removed)
J7: USB. Connect a USB cable from J7 to a computer with
the LTDACGen software installed.
J10 & J11: HSMC Connectors. These connectors are
designed to connect to the Altera Stratix IV development
board. All of the communication between the FPGA and
the DAC is routed through these connectors.

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DEMO MANUAL DC2191A
PARTS LIST
ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
Required Circuit Components
1 13 C1, C25, C26, C29, C31, C32, C33, C34,
C35, C36, C37, C71, C72
CAP., X7R, 0.1µF, 16V 10% 0402 AVX, 0402YC104KAT2A
2 4 C2, C3, C8, C19, C78, C94 CAP., NPO, 0.01µF, 25V, 5%, 0603 TDK, C1608C0G1H103J
3 9 C4, C6, C9, C11, C14, C18, C67, C68,
C69, C76, C77, C81
CAP., X7R, 1µF, 16V 10% 0603 AVX, 0603YC105KAT2A
4 5 C5, C7, C10, C12, C15 CAP., TANT., 47µF, 16V, 10%, 7343 AVX, TAJD476K016RNJ
5 6 C13, C16, C27, C28, C73, C74 CAP., X5R, 4.7µF, 16V, 20%, 1206 TDK, C3216X5R1C475M
6 3 C17, C40, C82 CAP., X5R, 10µF, 10V, 20%, 0603 AVX, 0603ZD106MA2T
7 1 C20 CAP., C0G, 4.7pF, 50V ± 0.25pF, 0603 AVX, 06035A4R7CAT2A
8 2 C21, C24 CAP., X7R, 0.1µF, 16V, 10%, 0603 TDK, C1608X7R1C104K
9 1 C22 CAP., X7R, 1µF, 25V, 10%, 0603 TDK, C1608X7R1E105K
10 2 C23, C70 CAP., X7R, 47µF, 10V, 10%, 1210 MURATA, GRM32ER71A476KE15L
11 1 C30 CAP., X5R, 3.3µF, 16V, 10%, 0603 TDK, C1608X5R1C335K
12 2 C38, C39 CAP., COG, 27pF, 50V, 5%, 0402 TDK, C1005C0G1H270J
13 2 C89, C88 CAP., COG, 5.6pF, 50V, 5%, 0402 TDK, C1005C0G1H5R6J
14 2 C90, C93 CAP., COG, 22pF, 50V, 5%, 0402 TDK, C1005C0G1H220J
15 1 C83 CAP., COG, 2.7pF, 50V, 5%, 0402 TDK, C1005C0G1H2R7J
16 1 C85 CAP., COG, 1.2pF, 50V, 5%, 0402 TDK, C1005C0G1H1R2J
17 1 C79 CAP., COG, 10pF, 50V, 5%, 0402 TDK, C1005C0G1H100J
18 1 C80 CAP., COG, 100pF, 50V, 5%, 0402 TDK, C1005C0G1H101J
19 2 C41, C42 CAP., COG, 100pF, 25V, 5%, 0201 TDK, C0603C0G1E101J
20 1 C43 CAP., X5R, 0.01µF, 16V, 10%, 0402 MURATA, GRM155R61C103KA01D
21 1 C44 CAP., X7R, 47nF, 25V, 10%, 0402 MURATA, GRM155R71E473KA88D
22 9 C45, C48, C49, C53, C54, C58, C61, C62,
C64
CAP., X5R, 100µF, 6.3V, 20%, 1206 TDK, C3216X5R0J107M
23 10 C46, C50, C51, C52, C55, C56, C57, C59,
C60, C63
CAP., X7S, 2.2µF, 4V, 20%, 0306 MURATA, LLL185C70G225ME01L
24 1 C47 CAP., COG, 10pF, 25V, 5%, 0201 MURATA, GRM0335C1E100JA01D
25 0 C65, C84, C86, C91, C92 CAP., OPT, 0402 OPTION
26 1 C66 CAP., NP0, 1pF, 25V ±.25pF, 0402 AVX, 04023A1R0CAT2A
27 1 C75 CAP., X7R, 10µF, 50V, 10%, 1210 MURATA, GRM32ER71H106KA12L
28 1 D1 DIODE, TVS, 70V, SMA DIODES INC./ ZETEX, SMAT70A-13-F
29 1 D2 DIODE, TVS, 24V, SMA DIODES INC./ ZETEX, SMAJ24A-13-F
30 1 D3 LED,RED, WATERCLEAR, 0805 WURTH, 150080RS75000
31 10 E1, E2, E3, E5-E11 TEST POINT, TURRET, .061, PBF MILL-MAX, 2308-2-00-80-00-00-07-0
32 2 E4, E12 TEST POINT, TURRET, .094, PBF MILL-MAX, 2501-2-00-80-00-00-07-0
33 2 JP1, JP2 HEADER, 3 PIN, .079 SULLINS, NRPN031PAEN-RC
34 1 J1 HEADER, 2 × 7 DUAL ROW MOLEX 87831-1420
35 3 J2, J3, J8 CON.,SMA JACK, STRAIGHT, THRU-HOLE AMPHENOL CONNEX, 132134
36 1 J4 CON., SMA PCB TOP MOUNT AEP, 9650-1113-005
37 2 J5, J6 CON., SMA 50 OHM EDGE-LAUNCH EMERSON, 142-0701-851

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DEMO MANUAL DC2191A
PARTS LIST
ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
38 1 J7 CONNECTOR, USB TYPE B, RIGHT ANGLE PCB
MOUNT
FCI, 61729-0010BLF
39 1 J9 HEADER, 2 ×5, 0.100 SAMTEC, TSW-105-07-L-D
40 2 J10, J11 CONNECTOR, HSMC SAMTEC, ASP-122952-01
41 6 L1, L2, L3, L4, L6, L7 FERRITE BEAD, 33Ω at 100mhz, 1206 MURATA, BLM31PG330SN1L
42 1 L5 INDUCTOR, 2.2µH, 20% HIGH CURRENT, SMT VISHAY, IHLP2020BZER2R2M11
43 1 L8 INDUCTOR, CERAMIC CHIP, 1nH, 5%, 0402 COILCRAFT, 0402CS-1N0XJLU
44 1 L9 FERRITE BEAD, 30Ω at 100Mhz, 0805 TDK, MPZ2012S300A
45 1 L10 INDUCTOR, 6.8µH, 20% HIGH CURRENT, SMT VISHAY, IHLP2020BZER6R8M11
46 2 L18, L19 IND, 3.3nH, 5%, 0402 TOKO, LL1005-FHL3N3S
47 2 L16, L17 IND, 3.9nH, 5%, 0402 TOKO, LL1005-FHL3N9S
48 1 L13 IND, 1.8nH, 5%, 0402 TOKO, LL1005-FHL1N8S
49 1 L12 IND, 2.7nH, 5%, 0402 TOKO, LL1005-FHL2N7S
50 2 L20, L21 IND, 560nH, 5%, 0603 COILCRAFT, 0603HL-561XJR
51 2 L14, L15 RES., CHIP, 0Ω, JUMPER, 1/16W, 0402 VISHAY, CRCW04020000Z0ED
52 5 MP1-MP5 MACHINE SCREW, NYLON, #4-40 ×1/2 IN.,
SLOTTED
EAGLE PLASTIC DEVICES, 561-J440.5
53 2 MP6-MP7 HEX STANDOFF, NYLON, #4-40 ×1/2 IN.,
THREADED
KEYSTONE, 1902C
54 4 MP8-MP11 SPACER, NYLON, 5mm L ×3.2mm DIA. BIVAR, 9908-5MM
55 2 MP12-MP13 STANDOFF, NYLON, 3/4 IN. KEYSTONE, 8834
56 4 MP14-MP17 STANDOFF, NYLON, #4-40 ×1/4 IN. MICROPLASTICS, #14HTSP101
57 2 MP18, MP19 STANDOFF, NYLON 3/4" KEYSTONE, 8834
58 2 Q1, Q2 TRANSISTOR, N-CH. POWER MOSFET, SOIC 8L FAIRCHILD, FDS8870
59 6 R1, R2, R3, R13, R17, R30 RES., CHIP, 1k, 1/16W, 5%, 0402 VISHAY, CRCW04021K00JNED
60 1 R4 RES., CHIP, 4.7k, 1/16W, 5%, 0402 YAGEO, RC0402JR-074K7L
61 4 R5, R14, R15, R16 RES., CHIP, 10k, 1/16W, 5%, 0402 YAGEO, RC0402JR-0710KL
62 2 R6, R8 RES., CHIP, 2k, 1/16W, 5%, 0402 VISHAY, CRCW04022K00JNED
63 0 R7, R10, R36, R37, R38, R39 RES., CHIP, DNI, 0402 OPTION
64 1 R9 RES., CHIP, 39Ω, 1/16W, 1%, 0402 VISHAY, CRCW040239R0FKED
65 3 R11, R57, R58 RES., CHIP, 0Ω JUMPER, 1/16W, 0402 VISHAY, CRCW04020000Z0ED
66 1 R12 RES., CHIP, 12k, 1/16W, 5%, 0402 VISHAY, CRCW040212K0JNED
67 1 R18 RES., CHIP, 2.2k, 1/16W, 5%, 0402 VISHAY, CRCW04022K20JNED
68 2 R19, R20 RES., CHIP, 3.24k, 1/16W, 1%, 0402 VISHAY, CRCW04023K24FKED
69 1 R21 RES., CHIP, 1k, 1/16W, 1%, 0402 YAGEO, RC0402FR-071KL
70 1 R22 RES., CHIP, 7.15k, 1/16W, 1%, 0402 VISHAY, CRCW04027K15FKED
71 2 R26, R29 RES., CHIP, 49.9Ω, 1/6W, 1%, 0201 VISHAY, CRCW020149R9FNED
72 7 R31, R32, R33, R34, R35, R41, R42 RES., CHIP, 10Ω, 1/16W, 1%, 0402 VISHAY, CRCW040210R0FKED
73 1 R45 RES., CHIP, 499Ω, 1/16W, 1%, 0402 VISHAY, CRCW0402499RFKED
74 1 R49 RES., CHIP, 41.2k, 1/10W, 1%, 0603 VISHAY, CRCW060341K2FKEA
75 1 R50 RES., CHIP, 309k, 1/10W, 1%, 0603 VISHAY, CRCW0603309KFKEA
76 1 R51 RES., CHIP, 243k, 1/10W, 1%, 0603 VISHAY, CRCW0603243KFKEA

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DEMO MANUAL DC2191A
PARTS LIST
ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
77 1 R52 RES., CHIP, 50Ω, 1/8W, 5%, 0603 VISHAY, FC0603E50R0JST1
78 1 R53 RES., CHIP, 560Ω, 1/10W, 5%, 0603 VISHAY, CRCW0603560RJNEA
79 1 R54 RES., CHIP, 10k, 1/10W, 1%, 0603 VISHAY, CRCW060310K0FKEA
80 4 R55, R56, R59, R60 RES., CHIP, 20Ω, 1/16W, 1%, 0402 VISHAY, CRCW040220R0FKED
81 2 R61, R62 RES., CHIP, 11Ω, 1/16W, 1%, 0402 VISHAY, CRCW040211R0FKED
82 1 T1 TRANSFORMER, BALUN ANAREN, B0430J50100AHF
83 1 U2 IC, USB TO MULTIPURPOSE UART/FIFO, TQFP FTDI, FT2232HL
84 1 U3 IC, QUAD MUX/DEMUX, TSSOP-16 FAIRCHILD, FST3257MTCX
85 1 U4 IC, EEPROM 1KBIT 3MHz, 8TSSOP MICROCHIP, 93LC46C-I/ST
86 1 U5 IC, MICROPOWER REGULATOR, SO-8 LINEAR TECH., LT1763CS8-3#PBF
87 2 U6, U7 IC, MICROPOWER REGULATOR, SO-8 LINEAR TECH., LT1763CS8-3.3#PBF
88 1 U8 IC, BUCK REGULATOR, QFN LINEAR TECH., LT8614IUDC#PBF
89 1 U9 IC, VOLTAGE REFERENCE, MSOP LINEAR TECH., LTC6655CHMS8-
2.048#PBF
90 2 U10, U11 I.C., LOW DROPOUT REGULATOR, 3mm ×3mm, DFN LINEAR TECH., LT3080EDD#PBF
91 1 U12 I.C., 80V IDEAL DIODE, DFN-6L LINEAR TECH.,LTC4359HDCB#TRPBF
92 1 U13 IC, MIXER LINEAR TECH, LTC5579IUH
93 2 XJP1, XJP2 SHUNT, 2mm SAMTEC, 2SN-BK-G
94 1 Y1 CRYSTAL, 12.0MHz, SMT ABRACON, ABMM2-12.000MHZ-E2-T
DC2191A-A Required Circuit Components
1 1 GENERAL BOM DC2191A
2 1 U1 IC, 16-BIT 2.5Gsps DAC LINEAR TECH. LTC2000IY-16

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DEMO MANUAL DC2191A
Figure 4. DC2191 Demo Circuit Schematic (Sheet 2)
SCHEMATIC DIAGRAM
2 2
1 1
D
D
C
C
B
B
A
A
NOTES:
CK
LTC2000 HIGH SPEED DAC + LTC5579 MIXER
(T0 PAGE 4)
FSADJ
*
U1
SHDN
DEMO CIRCUIT 2191A
LTC2000IY-16
TSTN
TRIG P
(TO PAGE 4)
(T0 PAGE 4)
RF Output
DC590
PD
0.1dB Chebychev, BW = 500MHz
1. ALL RESISTORS ARE SIZE 0402, U.O.N.
ASSY
LO Input
ASSEMBLY TABLE
REFIO
-A
TSTP
LTC2000IY-14
TO PAGE 4

-B
U1*
RUN
TRIG N
(FROM PAGE 4)
2. REFER TO PAGE 4 FOR LTC2000 POWER CONNECTIONS.
-C
DIGITAL INPUTS [DA0..DA15] AND [DB0..DB15] FROM PAGE 4
LTC2000IY-11
SVDD3V0
SVDD3V0
SVDD3V0
AVDD3V3
DBP3
DBP7
DCKIP
DAP0
DAN5
DBN10
DAN14
CS_ALT
DAN9
DAN2
PD_ALT
DBP15
DCKIN
DBN7
DCKOP
DBN3
DBP14
DAP10
DAP14
DBN5
CS_FTDI
DAP9
DAP8
DAN13
DBP5
DAP3
DBP4
SDI_ALT
DBN15
DAN8
DBP10
DAN10
DAN3
DBP9
DAN1
DBP11
DBN6
DAP12
DBP13
DAN4
DAN11
DAP13
SDO_FTDI
DBN4
DBN9
SCK_ALT
DBN2
DAP6
DBN11
DAN15
DBP1
DAN12
DAP4
DAP2
TRIGGER_P
DBP8
DBP6
PD_ALT
DAP1
DBP12
DAP15
SCK_FTDI
DAN7
DBN13
DAN6
DBN0
DBN1
DAN0
DCKON
DBP0
DBN8
DBP2
SDO_ALT
DBN12
TRIGGER_N
DAP11
DAP7
DAP5
DBN14
SDI_FTDI
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
TECHNOLOGY
    

        







M. HAWKINS
C. MAYOTT
 
 
 




TECHNOLOGY
    

        







M. HAWKINS
C. MAYOTT
 
 
 




TECHNOLOGY
    

        







M. HAWKINS
C. MAYOTT
C85 1.2pF C85 1.2pF
C90 22pF C90 22pF
L18 3.3nH L18 3.3nH
1 2
E11E11
L14 0 L14 0
1 2
R62 11 R62 11
R4110 R4110
R31 10R31 10
C81 1.0uF C81 1.0uF
C40 10uF C40 10uF
C42
100pF
COG 0201
C42
100pF
COG 0201
U13 LT5579 U13 LT5579
IF+
3
IF-
4
GND
1
GND
2
GND
5
GND
6
GND
7
GND
12
GND
13
GND
14
GND
17
GND
18
GND
19
GND
20
GND 21
LO 22
GND 23 GND 24
GND
25
VCC 11
VCC 10
VCC 9
VCC 8
GND
16
RF 15
C91 DNI C91 DNI
C79 10pF C79 10pF
C41 100pF COG 0201 C41 100pF COG 0201
J6J6
1
J2J2
1
R60 20 R60 20
R37 OPTR37 OPT
J5J5
1
E10E10
C93 22pF C93 22pF
L13 1.8nH L13 1.8nH
1 2
J4J4
1
L16 3.9nH L16 3.9nH
1 2
JP1JP1
1 3 2
R61 11 R61 11
R33 10R33 10
C83 2.7pF C83 2.7pF
GND
GND IN
T1
ANAREN XINGER
GND
GND IN
T1
ANAREN XINGER
1 3 2
4 6 5
R32 10R32 10
E9E9
L21
560nH
L21
560nH
12
C89 5.6pF C89 5.6pF
R39 OPTR39 OPT
C94 0.01uF C94 0.01uF
C47 10pF 0201 COG C47 10pF 0201 COG
C66 1pF NP0 C66 1pF NP0
E8E8
C82 10uF C82 10uF
R38 OPTR38 OPT
L15 0 L15 0
1 2
R58 0 R58 0
L12 2.7nH L12 2.7nH
1 2
R29 49.9 0201 1% R29 49.9 0201 1%
J1J1
VUNREG 1
GND 3
MISO 5
MOSI/SDA 7
EESDA 9
EESCL 11
GND 13
VCCIO 2
SCK/SCL 4
CS 6
GND 8
EEVCC 10
EEGND 12
GPIO 14
C65 DNI 0402 C65 DNI 0402
L17 3.9nH L17 3.9nH
1 2
J3J3
1
C92 DNI C92 DNI
C88 5.6pF C88 5.6pF
R35 10R35 10
L8 1nHL8 1nH
1 2
C43 0.01uF 0402 X5R C43 0.01uF 0402 X5R
R36 OPTR36 OPT
R45 499R45 499
R57 0 R57 0
C78 0.01uF C78 0.01uF
C86 DNI C86 DNI
R34 10R34 10
L19 3.3nH L19 3.3nH
1 2
R26 49.9 0201 1% R26 49.9 0201 1%
L20
560nH
L20
560nH
1 2
R59 20 R59 20
DAP15 A8
DAN15 A7
DAP14 B8
DAN14 B7
DAP13 C8
DAN13 C7
DAP12 D8
DAN12 D7
DAP11 E8
DAN11 E7
DAP10 F8
DAN10 F7
DAP9 G8
DAN9 G7
DAP8 H8
DAN8 H7
DAP7 K8
DAN7 K7
DAP6 L8
DAN6 L7
DAP5 M8
DAN5 M7
DAP4 N8
DAN4 N7
DAP3 P8
DAN3 P7
DAP2 Q8
DAN2 Q7
DAP1 R8
DAN1 R7
DAP0 S8
DAN0 S7
DBP15
A10 DBN15
A9
DBP14
B10 DBN14
B9
DBP13
C10 DBN13
C9
DBP12
D10 DBN12
D9
DBP11
E10 DBN11
E9
DBP10
F10 DBN10
F9
DBP9
G10 DBN9
G9
DBP8
H10 DBN8
H9
DBP7
K10 DBN7
K9
DBP6
L10 DBN6
L9
DBP5
M10 DBN5
M9
DBP4
N10 DBN4
N9
DBP3
P10 DBN3
P9
DBP2
Q10 DBN2
Q9
DBP1
R10 DBN1
R9
DBP0
S10 DBN0
S9
DCKIP
J10
DCKIN
J9
CKP
A3
CKN
A2
IOUTP H1
IOUTN J1
SCK S5
SD0 S3
SDI S4
PD S1
CS S2
REFIO M1
FSADJ M2
DCKON J7
DCKOP J8
TSTP
R4
TSTN
R3
SVDD S6
R4210 R4210
C84 DNI C84 DNI
C80 100pF C80 100pF

12
dc2191afa
DEMO MANUAL DC2191A
Figure 5. DC2191 Demo Circuit Schematic (Sheet 3)
SCHEMATIC DIAGRAM
2 2
1 1
D
D
C
C
B
B
A
A
JTAG
USB
CS_IF
SDO_IF
SDI_IF SCK_IF
JTAG
SPI
DEMO CIRCUIT 2191A
LTC2000 HIGH SPEED DAC + LTC5579 MIXER

POWER
SYNC
DVDD3V3
GND
SVDD3V0
+5V
AVDD3V3
VP1
DVDD1V8
FAULT
2.2V
AVDD1V8
USBD-
TMS TDO
TCK
VBUS
USBD+
TMS TDO
VBUS
TDI
TDI
TCK
VP1
SVDD3V0
SVDD3V0
FTDI_1V8
FTDI_1V8
SVDD3V0
SVDD3V0
SVDD3V0
SVDD3V0
FTDI_1V8
SVDD3V0
SVDD3V0
SVDD3V0
SVDD3V0
SVDD3V0
DVDD3V3
AVDD3V3
SVDD3V0
+5V
DVDD1V8
AVDD1V8
SVDD3V0
+5V
+5V
SCK_FTDI SDO_FTDI
BC3
CLK
RDN
DATA
BC2
BC1
FIFO_DATA_IN2
BD1
BC6
BD4
TXEN WM FIFO_DATA_IN1
CS
FIFO_DATA_IN5
CS_FTDI
BC0
BD6
FIFO_DATA_IN7
BC4
SUSPEND#
RESET#
FIFO_DATA_IN3
FIFO_DATA_IN4
RXEN
SDI_FTDI
FIFO_DATA_IN6 FIFO_DATA_IN0
BD5
BD2 BD0
SIWUA_CTRL
BD7
BC7
BC5 AC7
SYSCLK
PWRENN
OEN_CTRL BD3
 
 
 




TECHNOLOGY
    

        







M. HAWKINS
C. MAYOTT
 
 
 




TECHNOLOGY
    

        







M. HAWKINS
C. MAYOTT
 
 
 




TECHNOLOGY
    

        







M. HAWKINS
C. MAYOTT
C37
0.1uF
C37
0.1uF
R20
3.24K
R20
3.24K
R30 1K
0402
R30 1K
0402
C69 1.0uF C69 1.0uF
U11
LT3080EDD
U11
LT3080EDD
VIN
7
VCTRL
5
VOUT 3
VIN
8VOUT 2
VOUT 1
PAD 9
SET
4
C30 3.3uF C30 3.3uF
C23 47uF 1210 C23 47uF 1210
E5E5
C3
0.01uF
C3
0.01uF
C6
1.0uF
C6
1.0uF
C21 0.1uF C21 0.1uF
L6
FERRITE BEAD, 33 OHMS
L6
FERRITE BEAD, 33 OHMS
C11
1.0uF
C11
1.0uF
C14
1.0uF
C14
1.0uF
R7 OPTR7 OPT
R2 1K R2 1K
C73 4.7uF 1206 C73 4.7uF 1206
R14 10K R14 10K
C25 0.1uF C25 0.1uF
C20 4.7pF C20 4.7pF L5 2.2uHL5 2.2uH
1 2
E7E7
C13 4.7uF C13 4.7uF
C22 1.0uFC22 1.0uF
C71
0.1uF
C71
0.1uF
C68 1.0uF C68 1.0uF
D2
SMAJ24A
D2
SMAJ24A
21
C18 1.0uF C18 1.0uF
L2
FERRITE BEAD, 33 OHMS
L2
FERRITE BEAD, 33 OHMS
L4
FERRITE BEAD, 33 OHMS
L4
FERRITE BEAD, 33 OHMS
C67 1.0uF C67 1.0uF
R52 50R52 50
L1
FERRITE BEAD, 33 OHMS
L1
FERRITE BEAD, 33 OHMS
J8J8
1
C76 1.0uF C76 1.0uF
E1E1
C26 0.1uF C26 0.1uF
L7
FERRITE BEAD, 33 OHMS
L7
FERRITE BEAD, 33 OHMS
C9
1.0uF
C9
1.0uF
E4E4
LTC4359HDCB U12 LTC4359HDCB U12
SHDN
5
IN 4
SOURCE 3
GATE 2
OUT 1
VSS
6
PAD
7
R3 1K R3 1K
R12 12KR12 12K
L10
6.8uH
L10
6.8uH
1 2
R10
OPT
R10
OPT
C31
0.1uF
C31
0.1uF
C29 0.1uF C29 0.1uF
R13 1KR13 1K
R49 41.2KR49 41.2K
U3
FST3257MTCX
U3
FST3257MTCX
1B1 2 1B2 3
1A
4
2A
72B1 5
2B2 6
3A
93B1 11
3B2 10 4B1 14 4B2 13
4A
12
S
1
GND
8VCC 16
OE 15
R18 2.2K R18 2.2K
R22 7.15K R22 7.15K
C35
0.1uF
C35
0.1uF
E12E12
C8
0.01uF
C8
0.01uF
R56 20R56 20
R16 10K R16 10K
C32
0.1uF
C32
0.1uF
R54 10K R54 10K
C24 0.1uFC24 0.1uF
C72
0.1uF
C72
0.1uF
E6E6
Q1 FDS8870 Q1 FDS8870
2 1 3
4
5 6 7 8
+
C10
47uF
+
C10
47uF
U9
LTC6655CHMS8-2.048
U9
LTC6655CHMS8-2.048
VIN
2
SHDN
1
GND
3
OUTF 7
GND 8
GND
4
OUTS 6
GND 5
E3E3
+
C12
47uF
+
C12
47uF
C39
27pF
NPO
C39
27pF
NPO
C44 47nF 0402 25V C44 47nF 0402 25V
U10
LT3080EDD
U10
LT3080EDD
VIN
7
VCTRL
5
VOUT 3
VIN
8VOUT 2
VOUT 1
PAD 9
SET
4
R50 309K R50 309K
JP2JP2
1 3 2
+
C15
47uF
+
C15
47uF
E2E2 R55 20R55 20
R51 243K R51 243K
U4
93LC46C-I/ST
U4
93LC46C-I/ST
ORG 6
NC 7
CLK
2
VSS 5
DI
3
CS
1
DO
4
VCC 8
L9
FERRITE BEAD
L9
FERRITE BEAD
U8 LT8614 U8 LT8614
VIN1
4
GND1
6
PG
19
SYNC/MODE
17
TR/SS
16
INTVCC
2
RT
15
GND1
7
FB 20
BIAS 1
SW 22 SW 21
BST 3
GND2 11
VIN2 13
EN/UV 14
GND2 10
GND
18
SW 9 SW 8
C74 4.7uF 1206 C74 4.7uF 1206
C75
10uF
1210
C75
10uF
1210
U2
FT2232HL
U2
FT2232HL
GND
1
GND
5
GND
11
GND
15
GND
25
GND
35
GND
47
GND
51
AGND
10
TEST
13
OSCO
3
OSCI
2
EEDATA
61 EECLK 62 EECS 63
RESET#
14
REF
6
DP
8DM 7
VREGOUT
49
VREGIN
50
VPHY 4
VPLL 9
VCORE 12
VCORE 37
VCORE 64
VCCIO 20
VCCIO 31
VCCIO 42
VCCIO 56
ADBUS0 16 ADBUS1 17 ADBUS2 18 ADBUS3 19 ADBUS4 21 ADBUS5 22 ADBUS6 23 ADBUS7 24 ACBUS0 26 ACBUS1 27 ACBUS2 28 ACBUS3 29 ACBUS4 30 ACBUS5 32 ACBUS6 33 ACBUS7 34 BDBUS0 38 BDBUS1 39 BDBUS2 40 BDBUS3 41 BDBUS4 43 BDBUS5 44 BDBUS6 45 BDBUS7 46 BCBUS0 48 BCBUS1 52 BCBUS2 53 BCBUS3 54 BCBUS4 55 BCBUS5 57 BCBUS6 58 BCBUS7 59
PWREN# 60
SUSPEND# 36
D3 RED D3 RED
21
C33
0.1uF
C33
0.1uF
R4 4.7K R4 4.7K
R19
3.24K
R19
3.24K
C1 0.1uFC1 0.1uF
R8 2K R8 2K
C17 10uF C17 10uF
R5 10K R5 10K
J9J9
1 3 5 6
4 2
7 9
8 10
C16 4.7uF C16 4.7uF
C27 4.7uF C27 4.7uF
C4
1.0uF
C4
1.0uF
U5
LT1763CS8-3
U5
LT1763CS8-3
OUT 1
SEN 2
GND
3
BYP 4
SHDN
5
GND
6
GND
7
IN
8
C77 1.0uF C77 1.0uF
+
C7
47uF
+
C7
47uF
C70 47uF 1210 C70 47uF 1210
Q2 FDS8870 Q2 FDS8870
2
1
3
4
5
6
7
8
C36
0.1uF
C36
0.1uF
R53 560 R53 560
Y1 12.0 MhzY1 12.0 Mhz
1 3
2
4
R17 1K R17 1K
C38 27pF NPO C38 27pF NPO
R6 2K R6 2K
R21 1.00K R21 1.00K
R15 10K R15 10K
C2
0.01uF
C2
0.01uF
J7J7
1 2 3 4 5 6
U6
LT1763CS8-3.3
U6
LT1763CS8-3.3
OUT 1
SEN 2
GND
3
BYP 4
SHDN
5
GND
6
GND
7
IN
8
R11 0 OHMS R11 0 OHMS
+
C5
47uF
+
C5
47uF
C19
0.01uF
C19
0.01uF
D1
SMAT70A
D1
SMAT70A
2 1
C34
0.1uF
C34
0.1uF
U7
LT1763CS8-3.3
U7
LT1763CS8-3.3
OUT 1
SEN 2
GND
3
BYP 4
SHDN
5
GND
6
GND
7
IN
8
R1 1K R1 1K
C28 4.7uF C28 4.7uF
R9 39R9 39
L3
FERRITE BEAD, 33 OHMS
L3
FERRITE BEAD, 33 OHMS

13
dc2191afa
DEMO MANUAL DC2191A
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Figure 6. DC2191 Demo Circuit Schematic (Sheet 4)
SCHEMATIC DIAGRAM
2 2
1 1
D
D
C
C
B
B
A
A
U1
LTC2000 POWER CONNECTIONS
LTC2000 POWER BYPASS CAPACITORS
HSMC CONNECTORS - MEZZANINE SIDE
NET CONNECTIONS FOR LTC2000 POWER PINS TO PCB POWER NETS
DEMO CIRCUIT 2191A
LTC2000 HIGH SPEED DAC + LTC5579 MIXER

AVDD33 AVDD18 DVDD18DVDD33
DVDD1V8AVDD1V8
AVDD3V3
DVDD3V3 AVDD3V3
DVDD1V8
SVDD3V0
AVDD1V8
DVDD3V3
RDN
BD5
BC2
DAN1
FIFO_DATA_IN4
DAP3
DAN7
DAP1
RXEN
RESET#
DBN5
PD_ALT
DBN9
BC5
BD4
DAN9
DBP15
DAN8
DCKIN
DAP14
DBP9
FIFO_DATA_IN3
CS_ALT
DBP13
WM
DBP1
DATA
DBP0
DBP5
FIFO_DATA_IN6
TXEN
SDO_ALT
DAP7
SUSPEND#
DBP12
DAN15
DAP2
BC3
BC4
DCKOP
DAP0
DBN11 DBN8
DAP11 DAP4
FIFO_DATA_IN7
DAP13
DAP10
DAN10
BD1
DCKIP
DBP6
DAP8
BD7
DAN4
AC7
DBN10
DBN12
FIFO_DATA_IN0
DBN1
DBP11
BC0
DAN13 DBN13
FIFO_DATA_IN1
CLK
TRIGGER_P
DAN3
DAN11
DBN0
SIWUA_CTRL
BD0
DBN6
SCK_ALT
FIFO_DATA_IN5
DAN14
DBP7
DBN3
CS DBN4
DAN0
DAP6
DBN14
FIFO_DATA_IN2
DAN12
BC6
BC7
DAN2
DAP12
DBP2
BD6
DAP9
DAN6
BC1
DAP15
DBP8
DBP4
DBP10
DBN15
DAP5
BD3
OEN_CTRL
DBP14
PWRENN
DBP3
DCKON
DBN7
SDI_ALT
TRIGGER_N
BD2
SYSCLK
DAN5
DBN2
 
 
 




TECHNOLOGY
    

        







M. HAWKINS
C. MAYOTT
 
 
 




TECHNOLOGY
    

        







M. HAWKINS
C. MAYOTT
 
 
 




TECHNOLOGY
    

        







M. HAWKINS
C. MAYOTT
C64 100uF C64 100uF
C48 100uF C48 100uF
C55 2.2uF C55 2.2uF
C56 2.2uF C56 2.2uF
C58 100uF C58 100uF
GND GNDGNDGND
BANK 2 

GNDGNDGNDGND
BANK 2 

D0 41
D1
42
D2 43
D3
44
3V3 45
12V
46
LVDS_TXP0 47
LVDS_RXP0
48
LVDS_TXN0 49
LVDS_RXN0
50
3V3 51
12V
52
LVDS_TXP1 53
LVDS_RXP1
54
LVDS_TXN1 55
LVDS_RXN1
56
3V3 57
12V
58
LVDS_TXP2 59
LVDS_RXP2
60
LVDS_TXN2 61
LVDS_RXN2
62
3V3 63
12V
64
LVDS_TXP3 65
LVDS_RXP3
66
LVDS_TXN3 67
LVDS_RXN3
68
3V3 69
12V
70
LVDS_TXP4 71
LVDS_RXP4
72
LVDS_TXN4 73
LVDS_RXN4
74
3V3 75
12V
76
LVDS_TXP5 77
LVDS_RXP5
78
LVDS_TXN5 79
LVDS_RXN5
80
3V3 81
12V
82
LVDS_TXP6 83
LVDS_RXP6
84
LVDS_TXN6 85
LVDS_RXN6
86
3V3 87
12V
88
LVDS_TXP7 89
LVDS_RXP7
90
LVDS_TXN7 91
LVDS_RXN7
92
3V3 93
12V
94
CLKOUT1P 95
CLKIN1P
96
CLKOUT1N 97
CLKIN1N
98
3V3 99
GND 165
GND
166
GND 167
GND
168
12V
100
C50 2.2uF C50 2.2uF
C57 2.2uF C57 2.2uF
GNDGNDGNDGND
BANK 3


GNDGNDGNDGND
BANK 3


LVDS_TXP8 101
GND 169
LVDS_RXP8
102
LVDS_TXN8 103
LVDS_RXN8
104
3V3 105
12V
106
LVDS_TXP9 107
LVDS_RXP9
108
LVDS_TXN9 109
LVDS_RXN9
110
3V3 111
12V
112
LVDS_TXP10 113
LVDS_RXP10
114
LVDS_TXN10 115
LVDS_RXN10
116
3V3 117
12V
118
LVDS_TXP11 119
LVDS_RXP11
120
LVDS_TXN11 121
LVDS_RXN11
122
3V3 123
12V
124
LVDS_TXP12 125
LVDS_RXP12
126
LVDS_TXN12 127
LVDS_RXN12
128
3V3 129
12V
130
LVDS_TXP13 131
LVDS_RXP13
132
LVDS_TXN13 133
LVDS_RXN13
134
3V3 135
12V
136
LVDS_TXP14 137
LVDS_RXP14
138
LVDS_TXN14 139
LVDS_RXN14
140
3V3 141
12V
142
LVDS_TXP15 143
LVDS_RXP15
144
LVDS_TXN15 145
LVDS_RXN15
146
3V3 147
12V
148
LVDS_TXP16 149
LVDS_RXP16
150
LVDS_TXN16 151
LVDS_RXN16
152
3V3 153
12V
154
CLKOUT2P 155
CLKIN2P
156
CLKOUT2N 157
CLKIN2N
158
3V3 159
12V
160
GND
170
GND 171
GND
172
C51 2.2uF C51 2.2uF
C52 2.2uF C52 2.2uF
C59 2.2uF C59 2.2uF
GNDGNDGNDGND
BANK 1


GNDGNDGNDGND
BANK 1


XCVR_TXP7 1
XCVR_RXP7
2
XCVR_TXN7 3
XCVR_RXN7
4
XCVR_TXP6 5
XCVR_RXP6
6
XCVR_TXN6 7
XCVR_RXN6
8
XCVR_TXP5 9
XCVR_RXP5
10
XCVR_TXN5 11
XCVR_RXN5
12
XCVR_TXP4 13
XCVR_RXP4
14
XCVR_TXN4 15
XCVR_RXN4
16
XCVR_TXP3 17
XCVR_RXP3
18
XCVR_TXN3 19
XCVR_RXN3
20
XCVR_TXP2 21
XCVR_RXP2
22
XCVR_TXN2 23
XCVR_RXN2
24
XCVR_TXP1 25
XCVR_RXP1
26
XCVR_TXN1 27
XCVR_RXN1
28
XCVR_TXP0 29
XCVR_RXPO
30
XCVR_TXN0 31
XCVR_RXN0
32
SDA 33
SCL
34
JTAG_TCK 35
JTAG_TMS
36
JTAG_TDO 37
JTAG_TDI
38
CLKOUT0 39
CLKIN0
40
GND 161
GND
162
GND 163
GND
164
C60 2.2uF C60 2.2uF
C45 100uF C45 100uF
GND
A1
GND
A4
GND
A6
GND
B1
GND
B2
GND
B3
GND
B4
GND
B6
GND
C6
GND
D6
GND
E6
GND
F1
GND
F2
GND
F3
GND
F4
GND
F5
GND
F6
GND
G1
GND
G2
GND
G3
GND
G4
GND
G5
GND
G6
GND
H2
GND
H3
GND
H4
GND
H5
GND
H6
GND K1
GND K2
GND K3
GND K4
GND K5
GND K6
GND L1
GND L2
GND L3
GND L4
GND L5
GND L6
GND M3
GND M6
GND N1
GND N2
GND N3
GND N6
GND P6
GND Q6
GND R1
GND R2
GND R5
GND R6
DVDD18 A5 DVDD18 B5
AVDD18 C1 AVDD18 C2 AVDD18 C3 AVDD18 C4
DVDD18 C5
AVDD18 D1 AVDD18 D2 AVDD18 D3
DVDD18 D4 DVDD18 D5
AVDD18 E1 AVDD18 E2
DVDD18 E3 DVDD18 E4 DVDD18 E5
AVDD33
M4
DVDD33
M5
DVDD33
N5
DVDD33
P5
DVDD33
Q5
AVDD33
N4
AVDD33
P1
AVDD33
P2
AVDD33
P3
AVDD33
P4
AVDD33
Q1
AVDD33
Q2
AVDD33
Q3
AVDD33
Q4
GND
J2 GND J3
GND J4
GND J5
GND J6
C61 100uF C61 100uF
C49 100uF C49 100uF
GNDGNDGNDGND
BANK 2 

GNDGNDGNDGND
BANK 2 

D0 41
D1
42
D2 43
D3
44
3V3 45
12V
46
LVDS_TXP0 47
LVDS_RXP0
48
LVDS_TXN0 49
LVDS_RXN0
50
3V3 51
12V
52
LVDS_TXP1 53
LVDS_RXP1
54
LVDS_TXN1 55
LVDS_RXN1
56
3V3 57
12V
58
LVDS_TXP2 59
LVDS_RXP2
60
LVDS_TXN2 61
LVDS_RXN2
62
3V3 63
12V
64
LVDS_TXP3 65
LVDS_RXP3
66
LVDS_TXN3 67
LVDS_RXN3
68
3V3 69
12V
70
LVDS_TXP4 71
LVDS_RXP4
72
LVDS_TXN4 73
LVDS_RXN4
74
3V3 75
12V
76
LVDS_TXP5 77
LVDS_RXP5
78
LVDS_TXN5 79
LVDS_RXN5
80
3V3 81
12V
82
LVDS_TXP6 83
LVDS_RXP6
84
LVDS_TXN6 85
LVDS_RXN6
86
3V3 87
12V
88
LVDS_TXP7 89
LVDS_RXP7
90
LVDS_TXN7 91
LVDS_RXN7
92
3V3 93
12V
94
CLKOUT1P 95
CLKIN1P
96
CLKOUT1N 97
CLKIN1N
98
3V3 99
GND 165
GND
166
GND 167
GND
168
12V
100
C53 100uF C53 100uF
C62 100uF C62 100uF C46 2.2uF C46 2.2uF
GNDGNDGNDGND
BANK 3


GNDGNDGNDGND
BANK 3


LVDS_TXP8 101
GND 169
LVDS_RXP8
102
LVDS_TXN8 103
LVDS_RXN8
104
3V3 105
12V
106
LVDS_TXP9 107
LVDS_RXP9
108
LVDS_TXN9 109
LVDS_RXN9
110
3V3 111
12V
112
LVDS_TXP10 113
LVDS_RXP10
114
LVDS_TXN10 115
LVDS_RXN10
116
3V3 117
12V
118
LVDS_TXP11 119
LVDS_RXP11
120
LVDS_TXN11 121
LVDS_RXN11
122
3V3 123
12V
124
LVDS_TXP12 125
LVDS_RXP12
126
LVDS_TXN12 127
LVDS_RXN12
128
3V3 129
12V
130
LVDS_TXP13 131
LVDS_RXP13
132
LVDS_TXN13 133
LVDS_RXN13
134
3V3 135
12V
136
LVDS_TXP14 137
LVDS_RXP14
138
LVDS_TXN14 139
LVDS_RXN14
140
3V3 141
12V
142
LVDS_TXP15 143
LVDS_RXP15
144
LVDS_TXN15 145
LVDS_RXN15
146
3V3 147
12V
148
LVDS_TXP16 149
LVDS_RXP16
150
LVDS_TXN16 151
LVDS_RXN16
152
3V3 153
12V
154
CLKOUT2P 155
CLKIN2P
156
CLKOUT2N 157
CLKIN2N
158
3V3 159
12V
160
GND
170
GND 171
GND
172
C63 2.2uF C63 2.2uF
GNDGNDGNDGND
BANK 1


GNDGNDGNDGND
BANK 1


XCVR_TXP7 1
XCVR_RXP7
2
XCVR_TXN7 3
XCVR_RXN7
4
XCVR_TXP6 5
XCVR_RXP6
6
XCVR_TXN6 7
XCVR_RXN6
8
XCVR_TXP5 9
XCVR_RXP5
10
XCVR_TXN5 11
XCVR_RXN5
12
XCVR_TXP4 13
XCVR_RXP4
14
XCVR_TXN4 15
XCVR_RXN4
16
XCVR_TXP3 17
XCVR_RXP3
18
XCVR_TXN3 19
XCVR_RXN3
20
XCVR_TXP2 21
XCVR_RXP2
22
XCVR_TXN2 23
XCVR_RXN2
24
XCVR_TXP1 25
XCVR_RXP1
26
XCVR_TXN1 27
XCVR_RXN1
28
XCVR_TXP0 29
XCVR_RXPO
30
XCVR_TXN0 31
XCVR_RXN0
32
SDA 33
SCL
34
JTAG_TCK 35
JTAG_TMS
36
JTAG_TDO 37
JTAG_TDI
38
CLKOUT0 39
CLKIN0
40
GND 161
GND
162
GND 163
GND
164
C54 100uF C54 100uF

14
dc2191afa
DEMO MANUAL DC2191A
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
[phone] ●FAX: [phone] ●www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2015
LT 0416 REV A • PRINTED IN USA
DEMONSTRATION BOARD IMPORTANT NOTICE
Linear Technology Corporation (LT C ) provides the enclosed product(s) under the following AS IS conditions:
This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT
OR EVALUATION PURPOSES ONLY and is not provided by LT C for commercial use. As such, the DEMO BOARD herein may not be complete
in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety
measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union
directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.
If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date
of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU
OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS
FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR
ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LT C from all claims
arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all
appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or
agency certified (FCC, UL, CE, etc.).
No License is granted under any patent right or other intellectual property whatsoever. LT C assumes no liability for applications assistance,
customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
LT C currently services a variety of customers for products around the world, and therefore this transaction is not exclusive.
Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and
observe good laboratory practice standards. Common sense is encouraged.
This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LT C applica-
tion engineer.
Mailing Address:
Linear Technology
1630 McCarthy Blvd.
Milpitas, CA 95035
Copyright © 2004, Linear Technology Corporation

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