Linear Technology DC1544 User manual

LT3957
1
DESCRIPTION
Demonstration circuit 1544 is a Boost, SEPIC, Flyback
and Inverting Converter ith 5A, 40V S itch featuring
the LT3957. The LT3957 can be configured as a boost,
flyback, SEPIC, and inverting converter, but the demon-
stration circuit is assembled as a boost. The input volt-
age range is 4.5V to 20V and the output voltage is 24V
ith 600mA over the entire input voltage range.
The LT3957 has an internal n-channel 5A, 40V po er
s itch for high voltage, po er, and efficiency. The dual
paddle package provides excellent heat dissipation for
the internal po er s itch. The LT3957 current-mode
dc/dc converter features adjustable s itching frequency,
soft-start, compensation, shutdo n and undervoltage
lockout ith hysteresis, and a feedback pin (FBX) that
can be used in both positive and negative applications. A
SYNC input can be used to synchronize the s itching at
a frequency higher than the IC is programmed.
The demonstration circuit features small 1210 case size
ceramic input and output capacitors. The internal n-
channel po er s itch provides efficiency as high as 95%
in typical boost applications ith 14.4W output.
The LT3957 datasheet gives a complete description of
the part, operation and applications information. The
datasheet must be read in conjunction ith this Quick
Start Guide for demonstration circuit 1544A. The LT3957
is assembled in a 36-lead plastic UHE package ith t o
thermally enhanced pads for SW and GND. Proper board
layout is essential for both proper operation and maxi-
mum thermal performance. See the datasheet section
‘Layout Considerations’.
Figure 1. DC1544A 12VIN Efficiency
Design files for this circuit board are a ailable. Call
the LTC factory.
L , LT are trademarks of Linear Technology Corporation.
PARAMETER CONDITIONS UNITS
Minimum Input Supply Voltage 4.5 V
Maximum Input Supply Voltage 20 V
Output Voltage Programmed V
IN
= 4.5V-20V, I
LOAD
≤ 600mA 24 V
S itching Frequency R
T
= 41.2k 300 kHz
Guaranteed Maximum Output current V
IN
= 4.5V-20V 600 mA
Input Undervoltage Lockout (falling) R1=200k, R2=95.3k 3.8 V
Input Turn-on Voltage (rising) R1=200k, R2=95.3k 4.2 v
Efficiency V
IN
= 12V, I
LOAD
= 600mA 95 %
DEMO CIRCUIT
1544
QUICK START GUIDE
LT3957
Boost, SEPIC, Fly ack and Inverting Converter with 5A,
40V Switch

LT3957
2
QUICK START PROCEDURE
Demonstration circuit 1544 is easy to set up to evaluate
the performance of the LT3957. Refer to Figure 2 for
proper measurement equipment setup and follo the
procedure belo :
NOTE. When measuring the input or output voltage ripple, care must be
taken to avoid a long ground lead on the oscilloscope probe. Measure the
input or output voltage ripple by touching the probe tip directly across the
Vin or Vout and GND terminals.
1. Place jumpers in the follo ing positions:
NO SYNC
2. With po er off, connect the input po er supply to
VIN and GND.
NOTE. Connect po er to GND, not SGND.
3. Connect a load of 600mA or less to VOUT and GND
terminals (not SGND).
4. Turn on the po er at the input.
NOTE. Make sure that the input voltage does not exceed 20V.
5. Check for the proper output voltage (24V).
NOTE. If there is no output, temporarily disconnect the load to make
sure that the load is not set too high.
6. Once the proper output voltage is established, adjust
the load and input ithin the operating ranges and
observe the output voltage regulation, ripple voltage,
efficiency and other parameters.
Figure 2. Proper Measurement Equipment Setup
JP1

LT3957
3
TERMINAL OPTIONS
DC1544A has both GND and SGND terminals. The sche-
matic sho s that the GND and SGND pins of the IC are
not tied together outside the IC. They are internally con-
nected. It is important that po er ground currents do not
run on the SGND components. SGND is used to termi-
nate the signal ground components such as compensa-
tion and feedback. Input and output po er as ell as
input and output caps, catch diodes, etc. should all con-
nect to the GND plane. The SGND terminals are provided
in case the customer ould like to make signal ground
measurements, but they do not need to be used. Im-
properly connecting input po er to the SGND terminal
results in noisy behavior of the IC.
EN/UVLO (enable / undervoltage lockout) is provided as
a terminal so that the part can quickly be placed in shut-
do n by tying EN/UVLO to GND. The EN/UVLO pin is
already being used as an undervoltage lockout threshold
for the VIN ith resistors R1 and R2. Undervoltage lock-
out stops the IC from s itching hen VIN is too lo , but
shutdo n further reduces the VIN pin quiescent current
hen EN/UVLO is tied directly to GND. It is okay to leave
the EN/UVLO terminal floating.
INTVCC is provided as a terminal to be able to po er
INTVCC externally or to tie INTVCC directly to VIN hen
VIN remains belo 8V. It is okay to leave the INTVCC
terminal floating.
SYNC is provided as a terminal to be able to externally
synchronize the internal po er s itching frequency. If
SYNC is not used, the terminal should be left floating and
the JP1 position should be set at ‘NO SYNC’. If SYNC is
used, the s itching frequency of SYNC should be 20%
higher than the programmed s itching frequency of the
IC and the JP1 position must be set at ‘SYNC’. Please
see the datasheet for details regarding the use of SYNC
and the s itching frequency range.

LT3957
4
C11 OPT
0402
1210
1210
D1
PDS360
1 23
1210 1210
C7
22nF
R2 95.3k 1%
C1
2.2uF 50V
1210
C13 OPT
R6 15.8k 1%
R4 41.2k 1%
0402
0402
C5 4.7uF 50V
0603
0402
0402 0402
06030402
0402 0402 0402
0402
CDRH104RNP-100NC
1210
C2 2.2uF 50V
E4
GND
E1
INTVCC
C9
4.7uF 10V
C3 4.7uF 50V
E6
VOUT
24V @ 600mA
E5
SYNC
NOTES: UNLESS OTHERWISE SPECIFIED,
1. ALL CAPACITORS AND RESISTORS ARE 0402. 2. ALL CAPACITOR VALUES ARE IN MICROFARADS.
3. ALL RESISTOR VALUES ARE IN OHMS.
E3
VIN
4.5V - 20V
E2
SGND
C10 OPT
R7 0
C4 4.7uF 50V
C6 50V
4.7uF
R3 6.8k
R5
226k 0402 1%
E9
SGND
E7
GND
E10
GND
U1
LT3957EUHE
FBX 31
GND
17
GND
14
GND
16
SYNC
34
RT
33
GND
15
INTVCC
28
SW 38
VIN 27
EN/UVLO
25
VC
30
SS
32
SG N D
37
SW 21
GND
13
GND
12
SG N D
4
SG N D
23
SW 8
SENSE2 3 SENSE1 6
SW 9
SW 20
NC 10 NC 35 NC 36 NC 1 NC 2
SG N D
24
300kHz
C12 OPT
INTVCC
L1 10uH
E8
EN/UVLO
JP1
SYNC
NO SYNC
1 3 2
C8
0.33uF
R1
200k
1%