marutsu TB67H452FTG User manual

Instruction Manual
for Evaluation Board of TB67H452FTG
July 10, 2019
Rev.1.1

【Outline】
The TB67H452FTG is a tw -phase bip lar driver using a PWM ch pper f r dual
stepping m t rs with the cl ck c ntr l system. Ad pted 130 nm anal g pr cess
achieves the rating f 40 V and 2.0 A.
The IC has f ur H-bridge circuits and an perati n m de switching circuit.
By switching the perati n m de, it can c ntr l up t f ur brushed DC m t rs as
well as tw stepping m t rs.
This evaluati n b ard m unts necessary c mp nents t evaluate the IC. Any
special preparati n is n t needed. Please sense high c ntr llability f stepping
m t rs and brushed DC m t rs by using the TB67H452FTG.
【N te】
In using, please be careful ab ut the thermal c nditi n sufficiently.
As f r each c ntr l signal, please refer t the IC specificati n by accessing t the
bel w URL.
http://t shiba.semic n-
st rage.c m/us/pr duct/linear/m t rdriver/detail.TB67H452FTG.html
Further, the applicati n f this evaluati n b ard is limited t the purp se f
evaluating and learning the m t r c ntr l. Please d n t ship them t a market.

Basic N tes in Using Evaluati n B ard
P wer supply v ltage and perating v ltage range
Apply the v ltage t the VM pin in evaluating the IC.
In case f using the level select pin m unted n this evaluati n b ard, the v ltage sh uld be applied t the
VDD pin.
Th ugh the abs lute maximum rating f the VM p wer supply v ltage is +40 V, evaluate the IC within the
rated perating range f +6.3 V t 38.0 V.
The VDD v ltage sh uld be within the l gic input v ltage range f +3.3 V t 5.0 V in using the level select pin.
P wer n and ff sequence
There are n special pr cedures in applying a p wer supply and shutd wn since the IC implements the under
v ltage detecti n circuit (UVLO).
H wever, it is rec mmended t turn ff the m t r perati n during the p wer n and the shutd wn where
the VM v ltage is unstable. Start the m t r perati n by switching the input signals after the p wer supply
v ltage bec mes stable.
Output current
M t r current sh uld be 2.0 A r less that c rresp nds t the perating range.
H wever, the maximum current f the actual usage is limited depending n the usage c nditi ns (the ambient
temperature, the radiati n path, the exciting design, etc.). C nfigure the m st appr priate current value after
calculating the heat and evaluating the b ard under the perating envir nment.
C ntr l input
It is rec mmended t c nfigure the input signals f ENABLE_AB, ENABLE_CD, AB_MODE1, AB_MODE2,
CD_MODE1, CD_MODE2, CLK_AB and CLK_CD t l w level while the VM v ltage is n t supplied.
When the l gic signal is input with ut the VM v ltage supply, the electr m tive f rce is n t generated.

N tes in Using Evaluati n B ard –Err r detecti n circuits
Thermal shutd wn circuit (TSD)
When the IC detects an ver temperature (150℃(typ.)), the internal circuit turns ff the utput
MOSFETs. Reassert the VM p wer supply r use the standby m de t release this functi n. The TSD is
triggered when the IC is ver heated irregularly. Make sure n t t use the TSD functi n aggressively.
Over current pr tecti n (ISD)
When the current f the utput transist rs exceeds 4.0 A (typ.), the internal circuit turns ff the utput
MOSFETs. The VM p wer supply is shut d wn and utputs are turned ff till the VM p wer supply is
applied again. Reassert the VM p wer supply r use the standby m de t release this functi n. The
ISD is triggered when the utputs are in ver current state irregularly. Make sure n t t use the ISD
functi n aggressively.
Under v ltage detecti n circuit (UVLO)
When the VM pin v ltage falls t 5.7 V (typ.), the internal circuit turns ff the utput MOSFETs.
Internal circuits are reset when the UVLO is enabled.
It is released when the VM pin v ltage reaches 5.7 V (typ.).
＊Value in perati n and release f each pr tecti n circuit is f r y ur reference and is n t guaranteed.

Setting Evaluation Board 1
Setting otor control ode
M t r c ntr l m de is set by using MODE0,
MODE 1, and MODE2 pins.
This evaluati n b ard has a level select pin f r
setting the perati n f the TB67H452FTG (sh wn
in the ph t bel w).
*It is set t the l w level.
When selecting the functi n by using the level
select pin, input high level fr m the VDD pin.
MODE0 MODE1 MODE2 Motor control ode
H H H Stepping M t r (S) ×2
L H H DC M t r (L) (C mbinati n)×2
H L H Stepping M t r (L) (C mbinati n)×1
L L H DC M t r (S) ×4
H H L DC M t r (L) (C mbinati n)×1＋
Stepping M t r (S)
L H L DC M t r (S) ×2＋Stepper M t r (S)
H L L Inhibited
L L L Standby M de
Mode select pin
VDD pin

VrefA VrefB
R_RSA
R_RSB
R_RSD
R_RSC
VrefC VrefD
Charge
Fast
Slow
Setting otor current Setting otor current
Setting Evaluation Board 2
Wavefor s of otor current Value of setting otor current
R_VRFA, R_VRFB
R_VRFC, R_VRFC
Mounting area
I ut(max) = VREF(gain) x
VREF(gain) = 1/5.0 (typ.)
Vref(V)
R_RS(Ω)
R_RS = 0.22 Ω
By implementing potentiometers to R_VRFA,
R_VRFB, R_VRFC, and R_VRFD, the VCC voltage of
the internal regulator or the externally supplied
VDD voltage can be divided, and generating the
Vref voltage is possible

C_OSCM
R_OSCM
Charge
Fast
Slow
Setting chopping frequency of otor constant current
Chopping frequency [kHz] C_OSCM[pF] R_OSCM[kΩ]
150 150 180
140 180 100
130 180 150
120 220 100
110 180 220
100 270 120
90 330 68
80 330 130
70 390 130
60 470 120
50 560 180
40 820 68
Setting Evaluation Board 3
Wavefor s of otor current Value of setting otor current
Set the ch pping frequency by referring t the table
sh wn bel w. The resist r f 120 kΩ is ad pted t
R_OSCM and the capacit r f 270 pF is ad pted t
C_OSCM in rder t pr vide the frequency f 100
kHz at the time f shipment.

VMGND
Evaluation Board Connection Method 1
Power supply
VM
(10 V to 47 V)
MODE0 MODE1 MODE2 Motor control ode
H H H Stepping M t r (S) ×2
2-phase
bipolar
stepping
otor 2
2-phase
bipolar
Stepping
otor 1
Power supply
for switching
VDD
(3.3 V to 5 V)
Vref_B
(for phase B)
Vref_A (for phase A)
Vref_C
(for phase C)
Vref_D (for phase D)
Reference voltage for
otor current setting
Vref (0 V to 3.6 V)

VMGND
Power supply
VM
(10 V to 47 V)
MODE0 MODE1 MODE2 Motor control ode
L L H DC M t r (S) ×4
Evaluation Board Connection Method 2
Brushed
DC otor C
Brushed
DC otor D
Brushed
DC otor B
Brushed
DC otor A
Power supply
for switching
VDD
(3.3 V to 5 V) Vref_B
(for B axis)
Vref_C
(for C axis)
Vref_A (for A axis) Vref_D (for D axis)
Reference voltage for
otor current setting
Vref (0 V to 3.6 V)

Circuit Diagra of Evaluation Board
3-pin tri er
resistors

●This product was not designed for use with devices which could cause
personal injury in the event of failure or malfunction, including devices for
use in areas including medical, military, aviation, aerospace, nuclear control,
other types of safety mechanisms, etc., or for use in devices which require a
high standard of safety. Do not use this product for such applications. This
company assumes no liability for damages which may result from use of the
product.
◆Important Note ◆
Manufactured and Distributed by Marutsuelec Co., Ltd.
5-2-2, Seiki Daiichi Building 7F, Sotokanda, Chiyoda-ku,
Tokyo 101-0021, Japan
Tel：[phone] FAX：[phone]
https://www.marutsu.com