NB6L295MNGEVB, NB6L295MMNGEVB
http://onsemi.com
5
Step 2: CML & LVPECL Output Load Termination
NB6L295M −CML Outputs (see Figures 4 and 7)
The CML Qx and Qx outputs must be externally DC
loaded and AC terminated. A “split” or dual power supply
technique can be used to take advantage of terminating the
CML outputs into 50 Wto Ground of an oscilloscope or a
frequency counter. Since VTT = VCC, offsetting VCC to 0 V
yields VTT = 0 V or Ground (SMAGND).
NB6L295 −LVPECL Outputs (see Figures 5 and 6)
The LVPECL Qx and Qx outputs have standard, open
emitter outputs and must be externally DC loaded and AC
terminated.
Taking advantage of the internal 50 Wto ground of the test
equipment, a split power supply technique will assure the
equal output loading and termination of both outputs.
Connect the Qx and Qx outputs of the device to the
oscilloscope with equally matched cables. Both outputs
must be equally loaded and terminated. The outputs are now
DC loaded and AC terminated with 50 Wto VTT, which is
the Ground internal to the oscilloscope. Since VTT = VCC −
2 V, offsetting VCC to +2.0 V yields VTT = 0 V or Ground
(SMAGND).
The VTT terminal connects to the isolated SMAGND
connector ground plane, and is not to be confused with the
device ground pin, DUTGND.
NOTE: When a single−ended output is being used, the
unconnected output for the pair must be
terminated to VTT through a 50 Wresistor for
best operation. Unused output pairs may be left
unconnected. Since VTT = 0 V, a standard 50 W
SMA termination plug can be used.
Step 3: Connect and Setup Inputs
Set the signal generator amplitude to appropriate logic levels
For Clock, set the generator output for a square wave clock
signal with a 50% duty cycle.
For Differential Mode
Connect the differential outputs of the generator with
equally matched cables to the differential inputs of the
device (INx and INx). The differential inputs of the
NB6L295 incorporate internal 50 Wtermination resistors.
For Single−Ended Mode
Connect the single−ended output of the generator to the
INx input of the device. Vth must be applied to the
complementary input (INx) when operating in single−ended
mode. Refer to the device datasheet for details on
single−ended operation.
The VTx and VTx termination pins each have a trace from
package pin to a node where it can be connected to either
VCC, DUTGND or SMAGND, depending on the user’s
need.
Step 4: Program the SDI
The internal delay registers of the NB6L295/NB6L295M
may be programmed by a) the onboard PLD or b) by using
the three−lines for an external Serial Data Interface (SDI)
consisting of a SERIAL DATA (SDATA) input, a SERIAL
CLOCK (SCLK) input, and a SERIAL LOAD (SLOAD) as
follows:
a) Onboard PLD
When using the onboard PLD for the SDI source,
1. Install the three jumpers located at J4
2. Insure PLDVCC power is applied
3. The 11−bit switches will program the NB6L295’s
11−bit shift register. Set SW2 and SW4 switches to
the desired values for the 11−bit word
4. Load the program values by depressing
momentary switch SW3, or send a pulse signal
(125 ns min) through J1.
Refer to the NB6L295 datasheet for details on the proper
settings for these switches.
b. External SDI
An external SDI source can also program the
NB6L295/NB6L295M. See datasheet DC Table, AC Table,
as well as Figures 7 and 8. When using an external SDI
source, remove the three jumpers at J4.
To use the SDI ports, generate input SCLK, SDATA, and
SLOAD signals via the appropriate SMA connectors with
OFFSET LVCMOS/LVTTL LEVELS, i.e. +2.0 V HIGH
and −1.3 V LOW for a 3.3 V LVPECL power supply. The
SCLK signal will sample the information presented on
SDATA line. Values are loaded and indexed into a 11−bit
shift register. The register shifts once per rising edge of the
SCLK input. The serial input SDATA bits must each meet
setup and hold timing to the respective SCLK rising edge as
specified in the AC Characteristics section of the datasheet
document. The LEAST Significant Bit (LSB), PSEL, is
indexed in first followed by MSEL and D0, D1, D2, D3, D4,
D5, D6, and D7, through MOST Significant Bit (MSB), D8,
indexed in last. A Pulse on the SLOAD pin after the SHIFT
register is fully indexed (11 clocks) will load and latch the
data values for the internal registers.
The SLOAD pulse Low to HIGH rising edge transition
transfers the data from the SHIFT register to the LATCH
register. The SLOAD Pulse HIGH to LOW transition will
lock the new data values into the LATCH register.
After the PLD programs the NB6L295/NB6L295M,
PLDVCC can be disconnected.
Input/Output Enable −EN: When switch SW1 is in the UP
position or is externally connected to a LOW through J15
SMA connector, the outputs are ENABLED.
To monitor the Qx and Qx outputs on an oscilloscope or
frequency counter:
•The power supply needs to be DC offset
•Assure that the instrument has internal 50 W
termination impedance to ground
•Ensure the oscilloscope is triggered properly
