ON Semiconductor NB6L295MNGEVB User manual

©Semiconductor Components Industries, LLC, 2012
April, 2012−Rev. 3
1Publication Order Number:
EVBUM2082/D
NB6L295MNGEVB,
NB6L295MMNGEVB
NB6L295MNG/
NB6L295MMNG Evaluation
Board User's Manual
Introduction and Board Description
The NB6L295M Evaluation Board was designed to
provide a flexible and convenient platform to quickly
evaluate, characterize and verify the operation and
performance of either the NB6L295MMNG (CML) or the
NB6L295MNG (LVPECL) Dual Channel Programmable
Delay.
This evaluation board manual contains:
•Information on the NB6L295M Evaluation Board
•Appropriate Lab Setup
•Detailed Board Features
•Bill of Materials
This manual should be used in conjunction with the device
datasheet NB6L295M/D or NB6L295/D which contains full
technical details on the device specifications and operation.
The NB6L295M Evaluation Board was also designed to
accommodate a custom QFN−24 socket. Therefore, some
external components were installed on the bottom side of the
board.
Board Features
•On board programmable SDI circuitry minimizing
cabling, or, external SDI accessed through SMA
connectors.
•Convenient and compact board layout
•2.5 V or 3.3 V single or split−power supply operation
(banana jack connectors for VCC, SMAGND and
DUTGND; Separate PLDVCC power supply for on
board PLD
•CML or LVPECL differential output signals are
accessed via SMA connectors with provision for load
termination resistors
•SMA connectors are provided for 1) all high−speed
differential input & (CML or LVPECL) output signals
and 2) for external SDI & control signals access
Board Layout
The evaluation board is constructed in four layers. The top
layer is the primary trace layer and is made with polyimide
material. This layer provides a high−bandwidth 50 W
controlled trace impedance environment for the equal length
inputs and outputs. The second layer is a copper ground
plane.
Layer Stack
L1 Signal −“High and Low Speed”
L2 SMA Ground
L3 VCC (Device positive power supply) and DUTGND
(Device negative power supply)
L4 Signal −“Low Speed”
What measurements can you expect to make?
With this evaluation board, the following measurements
could be performed in single ended or differential modes of
operation.
•Propagation and Programmed Delay
•Output Rise and Fall Time
•Frequency Performance
•Jitter
•VCMR −Common Mode Range
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EVAL BOARD USER’S MANUAL

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Figure 1. NB6L295MNGEVB Evaluation Board Photo
Figure 2. NB6L295MMNGEVB Evaluation Board Photo

NB6L295MNGEVB, NB6L295MMNGEVB
http://onsemi.com
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D
U
T
G
N
D
S
M
A
G
N
D
D
U
T
V
C
C
P
L
D
V
C
C
Q1 Q0
External Control
Inputs for SDI
PD1 PD0
Data / Clock IN1 Data / Clock IN0
Figure 3. NB6L295M Evaluation Board Layout Overview
On−Board SDI
Control for 11−Bit
Delay Register
Push Button to
Load Selected Dx
Delay Bits
PLD for SDI
Control
DUTGND = PLDGND

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TEST AND MEASUREMENT SETUP AND PROCEDURE
Basic Lab Equipment (or Equivalent)
•Agilent Signal Generator #8133A for INx / INx,
external Clock or Data source
•Tektronix TDS8000 Oscilloscope or Frequency Counter
•Agilent #6624A DC Power Supply
•Digital Voltmeter
•Matched high−speed cables with SMA connectors
Lab Setup
A typical lab setup for taking time domain measurements
in differential mode operation is shown in Figures 6 and 7.
The following steps should be followed for proper
equipment setup:
Step 1: Connect Power Supply
The NB6L295M and NB6L295 have positive supply pins,
VCC, VCC0 and VCC1, and negative supply pins,
(DUT)GND. The SMAGND (VTT) terminal is the isolated
termination ground plane for the outputs, only, and is not to
be confused with the device ground pin, (DUT)GND.
Three power levels must be provided to the board, VCC,
DUTGND, and SMAGND. Connect a power supplies to
banana jack connectors for VCC, PLDVCC, DUTGND and
SMAGND, which are provided on the bottom of the board.
By−pass capacitors have been installed from VCC to
SMAGND and from DUTGND to SMAGND at the banana
jacks.
DUTGND = PLDGND, therefore, when device power
supply is 2.5 V or 3.3 V, PLDVCC = DUTVCC. The
exposed pad on the PCB for the QFN−24 package is
connected to DUTGND.
Figure 4. “Split” or Dual Power Supply Connections
for NB6L295M, CML Outputs
+2.5 V
Dual Power Supplies
VCC DUTGND
SMAGND
0 V +2.5 V
−+−+
Table 1. NB6L295M, CML OUTPUTS OFFSET POWER
SUPPLY CONFIGURATIONS
Device Pin
Power Supply
Connector
Color “Spilt” Power Supply
PLDVCC Yellow PLDVCC = 0 V
VCC Red VCC = 0 V
SMAGND Black VTT = 0 V
DUTGND Black DUTGND = −2.5 V or −3.3 V
Figure 5. “Split” or Dual Power Supply Connections
for NB6L295, LVPECL Outputs
+3.3 V
Dual Power Supplies
VCC DUTGND
SMAGND
2.0 V +1.3 V
−+−+
Table 2. NB6L295, LVPECL OUTPUTS “SPLIT”
POWER SUPPLY CONFIGURATIONS
Device Pin
Power Supply
Connector
Color “Spilt” Power Supply
PLDVCC Yellow PLDVCC = +2.0 V
VCC Red VCC = +2.0 V
SMAGND Black VTT = 0 V
DUTGND Black DUTGND = −0.5 V or −1.3 V

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Step 2: CML & LVPECL Output Load Termination
NB6L295M −CML Outputs (see Figures 4 and 7)
The CML Qx and Qx outputs must be externally DC
loaded and AC terminated. A “split” or dual power supply
technique can be used to take advantage of terminating the
CML outputs into 50 Wto Ground of an oscilloscope or a
frequency counter. Since VTT = VCC, offsetting VCC to 0 V
yields VTT = 0 V or Ground (SMAGND).
NB6L295 −LVPECL Outputs (see Figures 5 and 6)
The LVPECL Qx and Qx outputs have standard, open
emitter outputs and must be externally DC loaded and AC
terminated.
Taking advantage of the internal 50 Wto ground of the test
equipment, a split power supply technique will assure the
equal output loading and termination of both outputs.
Connect the Qx and Qx outputs of the device to the
oscilloscope with equally matched cables. Both outputs
must be equally loaded and terminated. The outputs are now
DC loaded and AC terminated with 50 Wto VTT, which is
the Ground internal to the oscilloscope. Since VTT = VCC −
2 V, offsetting VCC to +2.0 V yields VTT = 0 V or Ground
(SMAGND).
The VTT terminal connects to the isolated SMAGND
connector ground plane, and is not to be confused with the
device ground pin, DUTGND.
NOTE: When a single−ended output is being used, the
unconnected output for the pair must be
terminated to VTT through a 50 Wresistor for
best operation. Unused output pairs may be left
unconnected. Since VTT = 0 V, a standard 50 W
SMA termination plug can be used.
Step 3: Connect and Setup Inputs
Set the signal generator amplitude to appropriate logic levels
For Clock, set the generator output for a square wave clock
signal with a 50% duty cycle.
For Differential Mode
Connect the differential outputs of the generator with
equally matched cables to the differential inputs of the
device (INx and INx). The differential inputs of the
NB6L295 incorporate internal 50 Wtermination resistors.
For Single−Ended Mode
Connect the single−ended output of the generator to the
INx input of the device. Vth must be applied to the
complementary input (INx) when operating in single−ended
mode. Refer to the device datasheet for details on
single−ended operation.
The VTx and VTx termination pins each have a trace from
package pin to a node where it can be connected to either
VCC, DUTGND or SMAGND, depending on the user’s
need.
Step 4: Program the SDI
The internal delay registers of the NB6L295/NB6L295M
may be programmed by a) the onboard PLD or b) by using
the three−lines for an external Serial Data Interface (SDI)
consisting of a SERIAL DATA (SDATA) input, a SERIAL
CLOCK (SCLK) input, and a SERIAL LOAD (SLOAD) as
follows:
a) Onboard PLD
When using the onboard PLD for the SDI source,
1. Install the three jumpers located at J4
2. Insure PLDVCC power is applied
3. The 11−bit switches will program the NB6L295’s
11−bit shift register. Set SW2 and SW4 switches to
the desired values for the 11−bit word
4. Load the program values by depressing
momentary switch SW3, or send a pulse signal
(125 ns min) through J1.
Refer to the NB6L295 datasheet for details on the proper
settings for these switches.
b. External SDI
An external SDI source can also program the
NB6L295/NB6L295M. See datasheet DC Table, AC Table,
as well as Figures 7 and 8. When using an external SDI
source, remove the three jumpers at J4.
To use the SDI ports, generate input SCLK, SDATA, and
SLOAD signals via the appropriate SMA connectors with
OFFSET LVCMOS/LVTTL LEVELS, i.e. +2.0 V HIGH
and −1.3 V LOW for a 3.3 V LVPECL power supply. The
SCLK signal will sample the information presented on
SDATA line. Values are loaded and indexed into a 11−bit
shift register. The register shifts once per rising edge of the
SCLK input. The serial input SDATA bits must each meet
setup and hold timing to the respective SCLK rising edge as
specified in the AC Characteristics section of the datasheet
document. The LEAST Significant Bit (LSB), PSEL, is
indexed in first followed by MSEL and D0, D1, D2, D3, D4,
D5, D6, and D7, through MOST Significant Bit (MSB), D8,
indexed in last. A Pulse on the SLOAD pin after the SHIFT
register is fully indexed (11 clocks) will load and latch the
data values for the internal registers.
The SLOAD pulse Low to HIGH rising edge transition
transfers the data from the SHIFT register to the LATCH
register. The SLOAD Pulse HIGH to LOW transition will
lock the new data values into the LATCH register.
After the PLD programs the NB6L295/NB6L295M,
PLDVCC can be disconnected.
Input/Output Enable −EN: When switch SW1 is in the UP
position or is externally connected to a LOW through J15
SMA connector, the outputs are ENABLED.
To monitor the Qx and Qx outputs on an oscilloscope or
frequency counter:
•The power supply needs to be DC offset
•Assure that the instrument has internal 50 W
termination impedance to ground
•Ensure the oscilloscope is triggered properly

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Figure 6. Offset Power Supply Connections
for LVPECL Outputs, NB6L295
Signal
Generator
SMAGND = 0 V VCC = +2.0 V PLDVCC = +2.0 V
DUTGND = −0.5 V / −1.3 V
IN1
IN1
Trigger
Signal Generator
IN0
IN0
Trigger
Digital Oscilloscope or
Frequency Counter
50 W
50 W
50 W
50 W
50 W
Q0
Q0
Q1
Q1
Trigger

NB6L295MNGEVB, NB6L295MMNGEVB
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Figure 7. Offset Power Supply Connections
for CML Outputs, NB6L295M
Signal
Generator
SMAGND = 0 V VCC = 0 V PLDVCC = 0 V
DUTGND = −2.5 V / −3.3 V
IN1
IN1
Trigger
Signal Generator
IN0
IN0
Trigger
Digital Oscilloscope or
Frequency Counter
50 W
50 W
50 W
50 W
50 W
Q0
Q0
Q1
Q1
Trigger

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5 5
4 4
3 3
2 2
1 1
D D C C
B B A A
SCLK
SLOAD
SDIN
<Doc> <RevCode> <Title>
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13Wednesday, May 16, 2007
Title Size Document Number Rev
Date: Sheet of
DUT_SDIN
EN_
IN1 IN1_
Q1_
IN0
Q1
Q0_
Q0
Q0_ Q0 Q1_
IN0_
IN1
EN_
IN0_
Q1
DUT_SLOAD
IN1_
DUT_SCLK
IN0
VT0
PLD_SDATA
PLD_SCLK
PLD_SLOAD
VT0_ VT1_
VT1
VT1_
VT0_
VT0
VT1
DUT_GND
SMA_GND
DUTVCC
DUT_GND
DUTVCC
SMA_GND
SMA_GND
DUTVCC
DUT_GND
SMA_GND
DUT_GND
DUTVCC
DUT_GND
SMA_GND SMA_GND SMA_GND
DUTVCC
DUT_GND
SMA_GND
DUTVCC
DUTVCC
DUT_GND
DUT_GND
DUT_GND
DUTVCC
DUT_GND
J10 Q0
R6
DNI
J6
/IN0
J7
IN0
U1
QFN-24 Socket
1 2 3 4 5 6
7 8 9 10 11 12
13 14 15 16 17 18
192021222324
25
26 27 28
1 2
3
5 6
789101112
13 14 15 16 17 18
192021222324
EP EP EP
EP
R2
DNI
SG7
Solder Gap
J9
/IN1
SW1 /EN
2
1 3
4 6
J4
6-pin Header
12
34
56
J11 /Q0
SG6
Solder Gap
U6
NB6L295M
8
11
1
9
20 16 17 18
3 7 5 4
25
6
2
10 21 22 23 24
14 13 12 19 15
IN1
GND
VCC
IN1_
GND
VCC0
Q0
SLOAD
VT1
SCLK
SDIN
EP
VCC
EN_ VT1_ VT0_ IN0_ IN0 VT0
Q1
Q1_
VCC1 VCC0
VCC1
J5
/EN
SG8
Solder Gap
J3
SDIN
R5
DNI
J13 /Q1
SG1
Solder Gap
R8
DNI
R1 DNI
R4
DNI
J8
IN1
SG5
Solder Gap
SG2
Solder Gap
J1
SLOAD
TP1
/EN SG3
Solder Gap
R3 DNI
J2
SCLK
J12 Q1
SG4
Solder Gap
R7
Q0_
DNI
4

NB6L295MNGEVB, NB6L295MMNGEVB
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5 5
4 4
3 3
2 2
1 1
D D C C
B B A A
DIP Switches & PLD
<Doc> <RevCode> <Title>
B
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Title Size Document Number Rev Date: Sheet of
CLK_OE
CLK_4MHz
PLD_TDI
PLD_TMS
PLD_TDO
PLD_TCK
PLD_SDATA
PLD_SCLK
PLD_SLOAD
SMA_GND
DUT_GND
DUT_GND
DUT_GND
DUT_GND
DUT_GND
DUT_GND DUT_GND
DUT_GND DUT_GND
2_5V2_5V
2_5V
PLDVCC
PLDVCC
PLDVCC
PLDVCC
PLDVCC
PLDVCC
LED9
Red LED
12
R27 300
LED11
Red LED
12
LED1
Red LED
12
R19 150K R11 150K
TP2
4MHz CLK
LED3
Red LED
12
U3
74ACT04
1
13
3
11
5 9
2 12 4 10 6 8
14
7
A1 A2 A3 A4 A5 A6
Y1 Y2 Y3 Y4 Y5 Y6
VDDVSS
R32 300
Y1 4MHz Oscillat or
1 2 3
4
OE GND OUT
VDD
R25 1K
R12 150K
TP4 SDATA
LED4
Red LED
12
TP10
R18 150K
TP5 SCLK
R29 300
TP11
U4
74ACT04
1
13
3
11
5 9
2 12 4 10 6 8
14
7
A1 A2 A3 A4 A5 A6
Y1 Y2 Y3 Y4 Y5 Y6
VDDVSS
TP12
R13 150K
R35 300
TP13
R34 300
LED5
Red LED
12
TP6
R26 300
TP7
R31 300
SW4
M P
1 2
4 3
R9 150K R14 150K
TP14 START
R15 150K
LED6
Red LED
12
R16 150K
J14
JTAG HEADER
12 34 56 78 910
SW2
DELAY VALUE
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
R17 150K
R28 300
R33 300
R23
150K
LED7
Red LED
12
R22
1K
LED10
Red LED
12
LED8
Red LED
12
R21
1K
R20
1K
J15
START
R30 300
LED2
Red LED
12
R10 150K
TP8 TP9
U2
EPM7032AETC44
1 5
13
4
14 15
7
18
9
19 20 21 22 23 25
16
17
27
28 30 31 33 34
24
35 26
37
6
29
8
10
32
11
42 43
36
40 38 39
12
41
44 2 3
TDI
NC/S3
MC14
GNDIO
MC15 MC16
TMS
MC32
VCCIO1
MC31 MC30 MC29 MC28 MC27 MC26
GNDINT
VCCINT
MC24
M3 M2 M1 M0
N2
GNDIO
N1
TCK
GCLK1 MC8
VCCIO2
MC10 MC11
TDO
MC12
Spare1 Spare2
GNDINT
GCLK2
PLD_OEn
RCFGn
MC13
VCCINT
SCLK/S0
SDAT/S1
SLD/S2
TP3 SLOAD
SW3 START
1 2
3 4
R24 300

NB6L295MNGEVB, NB6L295MMNGEVB
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GND
5 5
4 4
3 3
2 2
1 1
D D C C B B A A
DUT
VCC
Caps near power connectors
DUT
GND
Place One Cap by Each DUT VCC pin
Place One Cap by Each DUT GND pin Three Power P
lanes:
DUTVCC (2.5 −3.3 V)
SMAGND (0 o
r DUTVCC)
DUTGND
(GND)
PCB NOTES: 1.) Use .062 FR4 board mater
ohm
Power and Hardwar
e
SMA
Input Termination Voltages (VT)
2.5 −3.3V
Place One Cap by Each PLD (U2) VCC pin
Low−Drop regulator for oscillator
SMA
GND
DUT
VCC
DUT
GND
Place Cap by Y1 pin 4
DUT Socket Mounting Holes
2.5 −3.3V
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33Wednesday, May 16, 2007
Title Size Document Number Rev Date: Sheet of
VT 1_
VT0 VT0_
VT 1
SMA_GND
DUT_GND
DUT_GND SMA_GND
DUT_GND
DUT_GND
SMA_GND
DUTVCC
DUTVCC
DUT_GND
SMA_GND
DUTVCC
DUTVCC
DUT_GND
SMA_GND
2_ 5V
DUTVCC
DUT_GND
DUTVCC
SMA_GND
DUTVCC SMA_GND
DUT_GND
DUTVCC
DUT_GND
SMA_GND
SMA_GND
SMA_GND SMA_GND
SMA_GND
PLDVCC
DUT_GND
PLDVCC
DUT_GND
PLDVCC
C30 0.1uF
TP25
PLD VCC
TP21
SMA GND
C13
0.0 1uF
M3
#4-40 Hex Standoff, 3/4
M1
#4-40 Hex Standoff, 3/4
C27
0.0 1uF
M8
#4-40 Phillips Panhead 1/4
M13 0.1 Shunt
TP18
/V T1
C10
0.0 1uF
M10
#4-40 Phillips Panhead 1/4
M15 0.1 Shunt M11 0.1 Shunt
C29 0.0 1uF
X2
0.095 Hole in 0 .200 Pad
C17
0.0 1uF
M12
#4-40 Phillips Panhead 1/4
M9 0.1 Shunt
TP24
DUT GND
X3
0.095 Hole in 0 .200 Pad
+C14
22uF 16V 20%
+C19
22u F 16V 20%
M7 0.1 Shunt
X4
0.095 Hole in 0 .200 Pad
C16
0.1uF
J17
6-p in Header
1 2
3 4
5 6
C21
0.1uF
M6
0.1 Shunt
C15
0.01 uF
M4
0.1 Shunt
C9
0.0 1uF
TP16
VT 1
C20 0.0 1uF
J23
PLD V CC 1
2
1
2
C12
0.0 1uF
X1
0.095 Hole in 0 .200 Pad
C6
1 uF
16V
J19
6-p in Header
1 2
3 4
5 6
TP22
SMA GND
J16
6- pin Header
1 2
3 4
5 6
C26
0.0 1uF
TP17
/VT 0
M5
#4-40 Hex Standoff, 3/4
TP15
VT0
C18 0.01 uF
C2
0.0 1uF
TP23
DUT GND
U5
LP3 985
1 3 4
5
2
VIN EN BYP
VOUT
GND
TP19 2.5V
X5
0.064 Hole in 0. 125 Pad
M14
#4-40 Phillips Panhead 1/4
C3
0.0 1uF
X6
0.064 Hole in 0. 125 Pad
C1
0.0 1uF
C7
0.0 1uF
J20
DUT VCC 1
2
1
2X7
0.064 Hole in 0. 125 Pad
C11
0.01 uF
J22
DUT GND 1
2
1
2
C4
0.0 1uF
X8
0.064 Hole in 0. 125 Pad
C5
1 uF
16V
C22 0.0 1uF
C8
0.0 1uF
X10 Mounting Hole
+C28
22uF 16V 20%
X1 1 Mounting Hole
X9 Mounting Hol e
C23
0.0 1uF
X12 Mounting Hol e
C24 0.01 uF
TP20
DUT VCC
J18
6- pin Header
1 2
3 4
5 6
C25 0.0 1uF
M2
#4-40 Hex Standoff, 3/4
J21
SM A GND 1
2
1
2

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Table 3. NB6L295MMNGEVB BILL OF MATERIALS
Item Qty Part Number Value Ref. Des. PCB Footprint Vendor Vendor PN Manufacturer
1 22 C0603C103K5RACTU 0.01 mFC1,C2,C3,C4,C7,C8,C9,C10,C11 603 Digikey 399−1091−1−ND Kemet
C12,C13,C15,C17,C18,C20,C22
C23,C24,C25,C26,C27,C29
2 2 C0805C105K4RACTU 1 mFC6,C5 805 Digikey 399−1284−1−ND Kemet
3 3 T494D226K016AS 22 mFC14,C19,C28 EIA−7343−31 Digikey 399−1782−1−ND Kemet
4 3 ECJ−1VB1C104K 0.1 mFC16,C21,C30 603 Digikey PCC1762CT−ND Panasonic
5 13 142−0701−801 SMA J1,J2,J3,J5,J6,J7,J8,J9, CON_SMA_142−0701−80x
JOHNSON
Digi−Key J502−ND Johnson Components
J10,J11,J12,J13,J15
6 5 10−89−1061 6−pin Header J4,J16,J17,J18,J19 Digikey WM6806−ND Molex
7 1 10−89−1101 JTAG HEADER J14 Digikey WM6810−ND Molex
8 1 571−0500 Red BANANA JACK J20 CON2_571−0500
DELTRON
Mouser 164−6219 Deltron
9 2 571−0100 BLK BANANA JACK J22,J21 CON2_571−0500
DELTRON
Mouser 164−6218 Deltron
10 1 571−0700 Yellow BANANA JACK J23 CON2_571−0500
DELTRON
Mouser 164−7170 Deltron
11 11 597−3111−407F Red LED LED1,LED2,LED3,LED4,LED5, LED_1206_AK Digikey 350−1565−1−ND Dialight
LED6,LED7,LED8,LED9,
LED10,LED11
12 4 1895 #4−40 Hex Standoff, 3/4 M1,M2,M3,M5 Digikey 1895K−ND Keystone
13 7 382811−50.1 Shunt M4,M6,M7,M9,M11,M13,M15 Digikey A26229−ND AMP/Tyco
14 4 PMS 440 0025 PH #4−40 Phillips Panhead
1/4
M8,M10,M12,M14 Digikey H342−ND Building Fasteners
15 8 DNI R1,R2,R3,R4,R5,R6,R7,R8 603
16 12 ERJ−3GEYJ154V 150k R9,R10,R11,R12,R13,R14, 603 Digikey P150KGCT−ND Panasonic
R15,R16,R17,R18,R19,R23
17 4 ERJ−3GEYJ102V 1k R20,R21,R22,R25 603 Digikey P1.0KGCT−ND Panasonic
18 11 ERJ−3GEYJ301V 300 R24,R26,R27,R28,R29,R30, 603 Digikey P300GCT−ND Panasonic
R31,R32,R33,R34,R35
20 1 GT13MSCBE SW SPDT SW1 SWS_GT13MSCBE_ITT Digikey CKN2092CT−ND C&K
21 1 76PSB09ST SW PianoDIP−9 SW2 SW_DIP_76PSB09
GRAYHILL
Digikey GH7145−ND Grayhill
22 1 B3S−1002 Push Button Switch SW3 SW_EVQPLD_PAN Digi−Key SW416−ND Omron
23 1 76PSB02ST SW PianoDIP−2 SW4 SW_DIP_76PSB02
GRAYHILL
Digikey GH7131−ND Grayhill
24 17 5015 TP_5015_KEYSTONE TP1,TP2,TP3,TP4,TP5,TP14, TP_5015_KEYSTONE Digikey 5015KCT−ND Keystone
TP15,TP16,TP17,TP18,TP19,
TP20,TP21,TP22,TP23,TP24,
TP25
26 1 NB6L295 or
NB6L295M
DUT U1 QFN−24 ON Semiconductor
27 1 EPM7032AETC44−10 EPM7032AETC44 U2 TQFP80P1200X1200X120−
44N
Arrow EPM7032AETC44−10 Altera
28 2 74ACT04SC 74ACT04 U3,U4 SO14 Digi−Key 74ACT04SC−ND Fairchild
29 1 LP3985IM5−2.5/NOPB LP3985 U5 SOT23−5Digi−Key LP3985IM5−2.5CT−N
D
National Semi
33 1 ECS−3525−040−B−TR 4MHz Oscillator Y1 OSCS_3525_ECS Digikey XC1047CT−ND ECS

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