Maxim Integrated MAX9277 User manual

General Description
The MAX9277/MAX9281 are 3.12Gbps Gigabit Multimedia
Serial Link (GMSL) serializers with 3- or 4-data lane LVDS
input (oLDI) and a CML serial output programmable for
50Ω coax or 100Ω shielded twisted pair (STP) cable drive.
The MAX9281 has HDCP content protection but other-
wise is the same as the MAX9277. The serializers pair
with any GMSL deserializer capable of coax input. When
programmed for STP output they are backward compat-
ible with any GMSL deserializer. The output amplitude is
programmable 100mV to 500mV single-ended (coax) or
100mV to 400mV differential (STP).
The audio channel supports L-PCM I2S stereo and up to
eight channels of L-PCM in TDM mode. Sample rates of
32kHz to 192kHz are supported with sample depth up to
32 bits.
The embedded control channel operates at 9.6kbps to
1Mbps in UART-UART and UART-I2C modes, and up to
1Mbps in I2C-I2C mode. Using the control channel, a µC
can program serializer, deserializer and peripheral device
registers at any time, independent of video timing, and
manage HDCP operation (MAX9281). A GPO output sup-
ports touch-screen controller interrupt requests from the
remote end of the link.
For use with longer cables, the serializers have program-
mable pre/deemphasis. Programmable spread spectrum
is available on the serial output. The serial output meets
ISO 10605 and IEC61000-4-2 ESD standards. The core
supply is 1.7 to 1.9V and the I/O supply is 1.7 to 3.6V. The
package is a lead-free, 48-pin, 7mm x 7mm TQFN with
exposed pad and 0.5mm lead pitch.
Applications
● High-Resolution Automotive Navigation
● Rear-Seat Infotainment
● Megapixel Camera Systems
Features and Benets
● Ideal for High-Definition Video Applications
• Drives Low-Cost 50Ω Coax Cable and FAKRA
Connectors or 100Ω STP
• 104MHz High-Bandwidth Mode Supports
1920x720p/60Hz Display With 24-Bit Color
• Serializer Pre/Deemphasis Allows 15m Cable at
Full Speed
• Up to 192kHz Sample Rate and 32-Bit Sample
Depth For 7.1 Channel HD Audio
● Multiple Data Rates for System Flexibility
• Up to 3.12Gbps Serial-Bit Rate
• 6.25MHz to 104MHz Pixel Clock
• 9.6kbps to 1Mbps Control Channel in UART,
mixed UART/I2C, or I2C Mode with Clock Stretch
Capability
● Reduces EMI and Shielding Requirements
• Serial Output Programmable for 100mV to 500mV
Single-Ended or 100mV to 400mV Di󰀨erential
• Programmable Spread Spectrum Reduces EMI
• Bypassable Input PLL for Pixel Clock Jitter
Attenuation
• Tracks Spread Spectrum on Input
• High-Immunity Mode for Maximum Control-
Channel Noise Rejection
● Peripheral Features for System Power-Up and
Verification
• Built-In PRBS Generator for BER Testing of the
Serial Link
• Programmable Choice of 9 Default Device
Addresses
• Dedicated “Up/Down” GPO for Touch-Screen
Interrupt and Other Uses
• Remote/Local Wake-Up from Sleep Mode
● Meets Rigorous Automotive and Industrial
Requirements
• -40ºC to +105ºC Operating Temperature
• 8kV Contact and 15kV Air ISO 10605 and
IEC 61000-4-2 ESD Protection
Ordering Information appears at end of data sheet.
19-6764; Rev 3; 10/17
MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
EVALUATION KIT AVAILABLE

MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
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TABLE OF CONTENTS
General Description ............................................................................ 1
Applications .................................................................................. 1
Features and Benefits .......................................................................... 1
Absolute Maximum Ratings ...................................................................... 8
Package Thermal Characteristics ................................................................. 8
DC Electrical Characteristics ..................................................................... 8
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Typical Operating Characteristics ................................................................ 15
Pin Configuration ............................................................................. 17
Pin Description............................................................................... 17
Functional Diagram ........................................................................... 20
Detailed Description........................................................................... 26
Register Mapping ...........................................................................26
Input Bit Map...............................................................................27
Serial Link Signaling and Data Format ...........................................................29
Reserved Bit (RES)/CNTL1....................................................................30
Data-Rate Selection .........................................................................30
High-Bandwidth Mode .......................................................................30
Audio Channel..............................................................................30
Audio Channel Input ......................................................................32
Reverse Control Channel .....................................................................33
Control Channel and Register Programming ......................................................34
UART Interface ..........................................................................34
Interfacing Command-Byte-Only I2C Devices
With UART ..............................................................................35
UART Bypass Mode ......................................................................35
I2C Interface ...............................................................................37
START and STOP Conditions ...............................................................37
Bit Transfer..............................................................................37
Acknowledge ............................................................................38
Slave Address ...........................................................................38
Bus Reset...............................................................................38
Format for Writing ........................................................................38
Format for Reading .......................................................................39
I2C Communication with Remote Side Devices .................................................40
I2C Address Translation ......................................................................40
GPO/GPI Control ...........................................................................40

MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
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TABLE OF CONTENTS (continued)
Pre/Deemphasis Driver.......................................................................40
Spread Spectrum ...........................................................................40
Manual Programming of the
Spread-Spectrum Divider .....................................................................42
Serial Output ...............................................................................42
Coax Splitter Mode ..........................................................................42
Configuration Inputs .........................................................................42
High-Immunity Reverse
Control Channel Mode .......................................................................42
Sleep Mode................................................................................44
Power-Down Mode ..........................................................................44
Configuration Link ...........................................................................44
Link Startup Procedure ........................................................................ 45
High-Bandwidth Digital Content Protection (HDCP) .................................................. 48
Encryption Enable...........................................................................48
Synchronization of Encryption .................................................................48
Repeater Support ...........................................................................48
HDCP Authentication Procedures ................................................................ 49
HDCP Protocol Summary .....................................................................49
Example Repeater Network—Two µCs ........................................................53
Detection and Action Upon
New Device Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Notification of Start of Authentication and
Enable of Encryption to Downstream Links .......................................................57
Applications Information........................................................................ 57
Self PRBS Test .............................................................................57
Dual µC Control ............................................................................57
Jitter-Filtering PLL...........................................................................57
RXCLKIN Spread Tracking ....................................................................57
Changing the Clock Frequency.................................................................57
Providing a Frame Sync
(Camera Applications)........................................................................58
Software Programming of the
Device Addresses ...........................................................................58
3-Level Configuration Inputs...................................................................58
Configuration Blocking .......................................................................58
Compatibility with other GMSL Devices ..........................................................58
Key Memory ...............................................................................58
HS/VS/DE Inversion .........................................................................59

MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
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TABLE OF CONTENTS (continued)
WS/SCK Inversion ..........................................................................59
Line-Fault Detection .........................................................................59
Internal Input Pulldowns ......................................................................59
Choosing I2C/UART Pullup Resistors ...........................................................59
AC-Coupling ...............................................................................60
Selection of AC-Coupling Capacitors ............................................................60
Power-Supply Circuits and Bypassing ...........................................................60
Power-Supply Table .........................................................................60
Cables and Connectors ......................................................................61
Board Layout ...............................................................................61
ESD Protection .............................................................................61
Typical Application Circuit ...................................................................... 71
Ordering Information .......................................................................... 71
Chip Information.............................................................................. 71
Package Information .......................................................................... 71
Revision History .............................................................................. 72

MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
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LIST OF FIGURES
Figure 1. Serial-Output Parameters............................................................... 21
Figure 2. Output Waveforms at OUT+, OUT-........................................................ 21
Figure 3. Single-Ended Output Template .......................................................... 21
Figure 4. Line Fault Detector Circuit .............................................................. 22
Figure 5. Worst-Case Pattern Input ............................................................... 22
Figure 6. I2C Timing Parameters ................................................................. 23
Figure 7. Differential Output Template ............................................................. 23
Figure 8. Input Setup and Hold Times ............................................................. 23
Figure 9. LVDS Receiver Input Skew Margin........................................................ 24
Figure 10. GPI-to-GPO Delay ................................................................... 24
Figure 11. Serializer Delay ...................................................................... 24
Figure 12. Link Startup Time .................................................................... 24
Figure 13. Power-Up Delay ..................................................................... 25
Figure 14. Input I2S Timing Parameters............................................................ 25
Figure 15. LVDS Input Timing ................................................................... 28
Figure 16. LVDS Clock and Bit Assignment ........................................................ 28
Figure 17. 3-Channel Mode Serial Data Format ..................................................... 29
Figure 18. 4-Channel Mode Serial Data Format ..................................................... 29
Figure 19. High-Bandwidth Mode Serial Data Format................................................. 30
Figure 21. 8-Channel TDM (24-Bit Samples, Padded with Zeros) ....................................... 32
Figure 22. 6-Channel TDM (24-Bit Samples, No Padding) ............................................. 32
Figure 20. Audio Channel Input Format............................................................ 32
Figure 23. Stereo I2S (24-Bit Samples, Padded with Zeros)............................................ 33
Figure 24. Stereo I2S (16-Bit Samples, No Padding).................................................. 33
Figure 25. GMSL UART Protocol for Base Mode .................................................... 34
Figure 26. GMSL UART Data Format for Base Mode................................................. 35
Figure 27. Sync Byte (0x79)..................................................................... 35
Figure 28. ACK Byte (0xC3)..................................................................... 35
Figure 29. Format Conversion between GMSL UART and I2C with Register Address (I2CMETHOD = 0) ........ 36
Figure 30. Format Conversion between GMSL UART and I2C without Register Address (I2CMETHOD = 1)...... 36

MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
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LIST OF FIGURES (continued)
Figure 31. START and STOP Conditions........................................................... 37
Figure 32. Bit Transfer ......................................................................... 37
Figure 33. Acknowledge........................................................................ 38
Figure 34. Slave Address....................................................................... 38
Figure 35. Format for I2C Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 36. Format for Write to Multiple Registers .................................................... 39
Figure 37. Format for I2C Read .................................................................. 39
Figure 38. 2:1 Coax Splitter Connection Diagram.................................................... 43
Figure 39. Coax Connection Diagram ............................................................. 43
Figure 40. State Diagram, CDS = LOW (Video Display Application) ..................................... 46
Figure 41. State Diagram, CDS = HIGH (Image Sensing Application) .................................... 47
Figure 42. Example Network with One Repeater and Two µCs (Tx = GMSL Serializers, Rx = Deserializers) ..... 53
Figure 43. Human Body Model ESD Test Circuit..................................................... 61
Figure 44. IEC 61000-4-2 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 45. ISO 10605 Contact Discharge ESD Test Circuit ............................................ 61

MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
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Table 1. Device Address Defaults (Register 0x00, 0x01) .............................................. 26
Table 2. Input Map (See Figure 15, Figure 16)...................................................... 27
Table 3. Data-Rate Selection Table............................................................... 30
Table 4. Maximum Audio WS Frequency (kHz) for Various RXCLKIN_ Frequencies......................... 31
Table 5. I2C Bit-Rate Ranges ................................................................... 40
Table 6. TP/COAX Drive Current (400mV Output Drive Levels) ..........................................41
Table 7. Serial Output Spread ....................................................................41
Table 8. Spread Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 9. Modulation Coefficients and Maximum SDIV Settings ......................................... 42
Table 10. CONF[1:0] Input Map .................................................................. 43
Table 11. Reverse Control Channel Modes ......................................................... 44
Table 12. Fast High-Immunity Mode Requirements................................................... 44
Table 13. Startup Procedure for Video-Display Applications (CDS = Low)................................. 45
Table 14. Startup Procedure for Image-Sensing Applications........................................... 46
Table 15. Startup, HDCP Authentication, and Normal Operation (Deserializer is not a Repeater)—First Part of the
HDCP Authentication Protocol................................................................... 49
Table 16. Link Integrity Check (Normal)—Performed Every 128 Frames After
Encryption is Enabled ......................................................................... 51
Table 17. Optional Enhanced Link Integrity Check—Performed Every 16 Frames After Encryption is Enabled .... 52
Table 18. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First and Second Parts of the
HDCP Authentication Protocol................................................................... 53
Table 19. MAX9277/MAX9281 Feature Compatibility ................................................. 58
Table 20. Line Fault Mapping.................................................................... 59
Table 21. Typical Power-Supply Currents (Using Worst-Case Input Pattern, VAVDD = VDVDD = VIOVDD = 1.8V,
VLVDSVDD = 3.3V, TA = +25°C, SSEN = High, No HDCP)............................................ 60
Table 22. Additional Supply Current from HDCP (MAX9281 Only)....................................... 60
Table 23. Suggested Connectors and Cables for GMSL .............................................. 61
Table 24. Register Table ....................................................................... 62
Table 25. HDCP Register Table (MAX9281 Only) .................................................... 68
LIST OF TABLES

AVDD to AGND ....................................................-0.5V to +1.9V
DVDD to AGND....................................................-0.5V to +1.9V
IOVDD to AGND...................................................-0.5V to +3.9V
LVDSVDD to AGND .............................................-0.5V to +3.9V
GND to AGND ......................................................-0.5V to +0.5V
LMN_ to AGND (15mA current limit) ....................-0.5V to +3.9V
OUT+, OUT- to AGND..........................................-0.5V to +1.9V
All Other Pins to AGND.......................-0.5V to (VIOVDD + 0.5V)
OUT+, OUT- Short Circuit to Ground or Supply........Continuous
Continuous Power Dissipation (TA = +70ºC)
TQFN (derate 40mW/ºC above +70ºC) ........................3200mW
Junction Temperature...................................................... +150ºC
Storage Temperature.........................................-65ºC to +150ºC
Lead Temperature (soldering, 10s) ................................. +300ºC
Soldering Temperature (reflow) ....................................... +260ºC
TQFN
Junction-to-Case Thermal Resistance (θJC)................ 1°C/W Junction-to-Ambient Thermal Resistance (θJA)......... 25°C/W
(Note 2)
(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, VLVDSVDD = 3.0V to 3.6V, RL = 100Ω ±1% (differential), TA = -40°C to +105°C,
unless otherwise noted. Differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID /2|.
Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25°C.) (Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SINGLE-ENDED INPUTS (CX/TP, PWDN, MS/CNTL0, CDS/CNTL3, SD, SCK, WS, AUTOS, CNTL1, CNTL2, HIM)
High-Level Input Voltage VIH1
(CX/TP, PWDN, MS/CNTL0, CDS/
CNTL3, AUTOS, HIM)
0.65 x
VIOVDD V
SD, SCK, WS, CNTL1, CNTL2 0.7 x
VIOVDD
Low-Level Input Voltage VIL1 0.35 x
VIOVDD V
Input Current IIN1 VIN = 0V to VIOVDD -10 +20 µA
THREE-LEVEL LOGIC INPUTS (CONF0, CONF1, ADD0, ADD1, BWS)
High-Level Input Voltage VIH 0.7 x
VIOVDD V
Low-Level Input Voltage VIL 0.3 x
VIOVDD V
Mid-Level Input Current IINM (Note 4) -10 +10 µA
Input Current IIN -150 +150 µA
SINGLE-ENDED OUTPUT (GPO)
High Level Output Voltage VOH1 IOUT = -2mA VIOVDD -
0.2 V
Low Level Output Voltage VOL1 IOUT = 2mA 0.2 V
OUTPUT Short-Circuit
Current IOS VOUT = 0V VIOVDD = 3.0V to 3.6V 16 35 64 mA
VIOVDD = 1.7V to 1.9V 3 12 21
MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
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Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Note 1: AGND, GND connected to PCB ground.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
DC Electrical Characteristics

(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, VLVDSVDD = 3.0V to 3.6V, RL = 100Ω ±1% (differential), TA = -40°C to +105°C,
unless otherwise noted. Differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID /2|.
Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25°C.) (Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
OPEN-DRAIN INPUT/OUTPUT (RX/SDA, TX/SCL, LFLT)
High-Level Input Voltage VIH2 0.7 x
VIOVDD V
Low-Level Input Voltage VIL2 0.3 x
VIOVDD V
Input Current IIN2 (Note 5) RX/SDA, TX/SCL -110 +5 µA
LFLT -80 +5
Low-Level Output Voltage VOL2 IOUT = 3mA VIOVDD = 1.7V to 1.9V 0.4 V
VIOVDD = 3.0V to 3.6V 0.3
Input Capacitance CIN Each pin (Note 9) 10 pF
DIFFERENTIAL SERIAL OUTPUT (OUT+, OUT-)
Di󰀨erential Output Voltage VOD
Pre-emphasis o󰀨 (Figure 1) 300 400 500
mV3.3dB preemphasis setting (Figure 2) 350 610
3.3dB deemphasis setting (Figure 2) 240 425
Change in VOD Between
Complementary Output States ΔVOD Preemphasis o󰀨, deemphasis only 15 mV
Output O󰀨set Voltage
(VOUT+ + VOUT-)/2 = VOS VOS Preemphasis o󰀨 1.1 1.4 1.56 V
Change in VOS between
Complementary Output States ΔVOS 15 mV
Output Short-Circuit Current IOS
VOUT+ or VOUT- = 0V -62 mA
VOUT+ or VOUT- = 1.9V 25
Magnitude of Di󰀨erential
Output Short-Circuit Current IOSD VOD = 0V 25 mA
Output Termination Resistance
(Internal) ROUT From OUT+, OUT- to VAVDD 45 54 63 Ω
SINGLE-ENDED SERIAL OUTPUT (OUT+, OUT-)
Single-Ended Output Voltage VOUT
Pre-emphasis o󰀨, high drive (Figure 3) 375 500 625
mV
3.3dB preemphasis setting, high drive
(Figure 2)435 765
3.3dB deemphasis setting, high drive
(Figure 2)300 535
Output Short-Circuit Current IOS
VOUT+ or VOUT- = 0V -69 mA
VOUT+ or VOUT- = 1.9V 32
Output Termination Resistance
(Internal) RO From OUT+ or OUT- to VAVDD 45 54 63 Ω
MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
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DC Electrical Characteristics (continued)

(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, VLVDSVDD = 3.0V to 3.6V, RL = 100Ω ±1% (differential), TA = -40°C to +105°C,
unless otherwise noted. Differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID /2|.
Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25°C.) (Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REVERSE CONTROL-CHANNEL RECEIVER (OUT+, OUT-)
High Switching Threshold VCHR
Normal-immunity mode 27 mV
High-immunity mode 40
Low Switching Threshold VCLR
Normal-immunity mode -27 mV
High-immunity mode -40
LINE FAULT DETECTION INPUT (LMN_)
Short-to-GND Threshold VTG (Figure 4) 0.3 V
Normal Threshold VTN (Figure 4) 0.57 1.07 V
Open Threshold VTO (Figure 4) 1.45 VIO +
0.06 V
Open Input Voltage VIO (Figure 4) 1.47 1.75 V
Short-to-Battery Threshold VTE (Figure 4) 2.47 V
LVDS INPUTS (RXIN_, RXCLKIN_)
Di󰀨erential Input High
Threshold VTH VCM = 1.2V 50 mV
Di󰀨erential Input Low
Threshold VTL VCM = 1.2V -50 mV
Input Di󰀨erential Termination
Resistance RTERM 85 110 135 Ω
Input Current IIN+, IIN-
PWDN = high or low, IN+ and IN- are
shorted -25 +25 µA
Power-O󰀨 Input Current IIN0+, IIN0- VAVDD = VDVDD = VIOVDD = 0V -40 +40 µA
POWER SUPPLY
Total Supply Current
(AVDD + DVDD + IOVDD)
(Note 6) (Worst-Case
Pattern) (Figure 5)
IWCS
BWS = low
fPCLKIN_ = 16.6MHz 100 125
mA
fPCLKIN_ = 33.3MHz 106 140
fPCLKIN_ = 66.6MHz 123 155
fPCLKIN_ = 104MHz 146 190
BWS = mid fPCLKIN_ = 36.6MHz 108 145
fPCLKIN_ = 104MHz 152 195
LVDSVDD Worst-Case
Supply Current (Figure 5,
Note 6)
IWCS
BWS = low
fPCLKIN_ = 16.6MHz 24 30
mA
fPCLKIN_ = 33.3MHz 24 30
fPCLKIN_ = 66.6MHz 24 30
fPCLKIN_ = 104MHz 24 30
BWS = mid fPCLKIN_ = 36.6MHz 29 35
fPCLKIN_ = 104MHz 29 35
MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
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DC Electrical Characteristics (continued)