Maxim Integrated MAX9277 User manual

General Description
The MAX9277/MAX9281 are 3.12Gbps Gigabit Multimedia
Serial Link (GMSL) serializers with 3- or 4-data lane LVDS
input (oLDI) and a CML serial output programmable for
50Ω coax or 100Ω shielded twisted pair (STP) cable drive.
The MAX9281 has HDCP content protection but other-
wise is the same as the MAX9277. The serializers pair
with any GMSL deserializer capable of coax input. When
programmed for STP output they are backward compat-
ible with any GMSL deserializer. The output amplitude is
programmable 100mV to 500mV single-ended (coax) or
100mV to 400mV differential (STP).
The audio channel supports L-PCM I2S stereo and up to
eight channels of L-PCM in TDM mode. Sample rates of
32kHz to 192kHz are supported with sample depth up to
32 bits.
The embedded control channel operates at 9.6kbps to
1Mbps in UART-UART and UART-I2C modes, and up to
1Mbps in I2C-I2C mode. Using the control channel, a µC
can program serializer, deserializer and peripheral device
registers at any time, independent of video timing, and
manage HDCP operation (MAX9281). A GPO output sup-
ports touch-screen controller interrupt requests from the
remote end of the link.
For use with longer cables, the serializers have program-
mable pre/deemphasis. Programmable spread spectrum
is available on the serial output. The serial output meets
ISO 10605 and IEC61000-4-2 ESD standards. The core
supply is 1.7 to 1.9V and the I/O supply is 1.7 to 3.6V. The
package is a lead-free, 48-pin, 7mm x 7mm TQFN with
exposed pad and 0.5mm lead pitch.
Applications
● High-Resolution Automotive Navigation
● Rear-Seat Infotainment
● Megapixel Camera Systems
Features and Benets
● Ideal for High-Definition Video Applications
• Drives Low-Cost 50Ω Coax Cable and FAKRA
Connectors or 100Ω STP
• 104MHz High-Bandwidth Mode Supports
1920x720p/60Hz Display With 24-Bit Color
• Serializer Pre/Deemphasis Allows 15m Cable at
Full Speed
• Up to 192kHz Sample Rate and 32-Bit Sample
Depth For 7.1 Channel HD Audio
● Multiple Data Rates for System Flexibility
• Up to 3.12Gbps Serial-Bit Rate
• 6.25MHz to 104MHz Pixel Clock
• 9.6kbps to 1Mbps Control Channel in UART,
mixed UART/I2C, or I2C Mode with Clock Stretch
Capability
● Reduces EMI and Shielding Requirements
• Serial Output Programmable for 100mV to 500mV
Single-Ended or 100mV to 400mV Di󰀨erential
• Programmable Spread Spectrum Reduces EMI
• Bypassable Input PLL for Pixel Clock Jitter
Attenuation
• Tracks Spread Spectrum on Input
• High-Immunity Mode for Maximum Control-
Channel Noise Rejection
● Peripheral Features for System Power-Up and
Verification
• Built-In PRBS Generator for BER Testing of the
Serial Link
• Programmable Choice of 9 Default Device
Addresses
• Dedicated “Up/Down” GPO for Touch-Screen
Interrupt and Other Uses
• Remote/Local Wake-Up from Sleep Mode
● Meets Rigorous Automotive and Industrial
Requirements
• -40ºC to +105ºC Operating Temperature
• 8kV Contact and 15kV Air ISO 10605 and
IEC 61000-4-2 ESD Protection
Ordering Information appears at end of data sheet.
19-6764; Rev 3; 10/17
MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
EVALUATION KIT AVAILABLE

MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
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TABLE OF CONTENTS
General Description ............................................................................ 1
Applications .................................................................................. 1
Features and Benefits .......................................................................... 1
Absolute Maximum Ratings ...................................................................... 8
Package Thermal Characteristics ................................................................. 8
DC Electrical Characteristics ..................................................................... 8
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Typical Operating Characteristics ................................................................ 15
Pin Configuration ............................................................................. 17
Pin Description............................................................................... 17
Functional Diagram ........................................................................... 20
Detailed Description........................................................................... 26
Register Mapping ...........................................................................26
Input Bit Map...............................................................................27
Serial Link Signaling and Data Format ...........................................................29
Reserved Bit (RES)/CNTL1....................................................................30
Data-Rate Selection .........................................................................30
High-Bandwidth Mode .......................................................................30
Audio Channel..............................................................................30
Audio Channel Input ......................................................................32
Reverse Control Channel .....................................................................33
Control Channel and Register Programming ......................................................34
UART Interface ..........................................................................34
Interfacing Command-Byte-Only I2C Devices
With UART ..............................................................................35
UART Bypass Mode ......................................................................35
I2C Interface ...............................................................................37
START and STOP Conditions ...............................................................37
Bit Transfer..............................................................................37
Acknowledge ............................................................................38
Slave Address ...........................................................................38
Bus Reset...............................................................................38
Format for Writing ........................................................................38
Format for Reading .......................................................................39
I2C Communication with Remote Side Devices .................................................40
I2C Address Translation ......................................................................40
GPO/GPI Control ...........................................................................40

MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
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TABLE OF CONTENTS (continued)
Pre/Deemphasis Driver.......................................................................40
Spread Spectrum ...........................................................................40
Manual Programming of the
Spread-Spectrum Divider .....................................................................42
Serial Output ...............................................................................42
Coax Splitter Mode ..........................................................................42
Configuration Inputs .........................................................................42
High-Immunity Reverse
Control Channel Mode .......................................................................42
Sleep Mode................................................................................44
Power-Down Mode ..........................................................................44
Configuration Link ...........................................................................44
Link Startup Procedure ........................................................................ 45
High-Bandwidth Digital Content Protection (HDCP) .................................................. 48
Encryption Enable...........................................................................48
Synchronization of Encryption .................................................................48
Repeater Support ...........................................................................48
HDCP Authentication Procedures ................................................................ 49
HDCP Protocol Summary .....................................................................49
Example Repeater Network—Two µCs ........................................................53
Detection and Action Upon
New Device Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Notification of Start of Authentication and
Enable of Encryption to Downstream Links .......................................................57
Applications Information........................................................................ 57
Self PRBS Test .............................................................................57
Dual µC Control ............................................................................57
Jitter-Filtering PLL...........................................................................57
RXCLKIN Spread Tracking ....................................................................57
Changing the Clock Frequency.................................................................57
Providing a Frame Sync
(Camera Applications)........................................................................58
Software Programming of the
Device Addresses ...........................................................................58
3-Level Configuration Inputs...................................................................58
Configuration Blocking .......................................................................58
Compatibility with other GMSL Devices ..........................................................58
Key Memory ...............................................................................58
HS/VS/DE Inversion .........................................................................59

MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
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TABLE OF CONTENTS (continued)
WS/SCK Inversion ..........................................................................59
Line-Fault Detection .........................................................................59
Internal Input Pulldowns ......................................................................59
Choosing I2C/UART Pullup Resistors ...........................................................59
AC-Coupling ...............................................................................60
Selection of AC-Coupling Capacitors ............................................................60
Power-Supply Circuits and Bypassing ...........................................................60
Power-Supply Table .........................................................................60
Cables and Connectors ......................................................................61
Board Layout ...............................................................................61
ESD Protection .............................................................................61
Typical Application Circuit ...................................................................... 71
Ordering Information .......................................................................... 71
Chip Information.............................................................................. 71
Package Information .......................................................................... 71
Revision History .............................................................................. 72

MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
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LIST OF FIGURES
Figure 1. Serial-Output Parameters............................................................... 21
Figure 2. Output Waveforms at OUT+, OUT-........................................................ 21
Figure 3. Single-Ended Output Template .......................................................... 21
Figure 4. Line Fault Detector Circuit .............................................................. 22
Figure 5. Worst-Case Pattern Input ............................................................... 22
Figure 6. I2C Timing Parameters ................................................................. 23
Figure 7. Differential Output Template ............................................................. 23
Figure 8. Input Setup and Hold Times ............................................................. 23
Figure 9. LVDS Receiver Input Skew Margin........................................................ 24
Figure 10. GPI-to-GPO Delay ................................................................... 24
Figure 11. Serializer Delay ...................................................................... 24
Figure 12. Link Startup Time .................................................................... 24
Figure 13. Power-Up Delay ..................................................................... 25
Figure 14. Input I2S Timing Parameters............................................................ 25
Figure 15. LVDS Input Timing ................................................................... 28
Figure 16. LVDS Clock and Bit Assignment ........................................................ 28
Figure 17. 3-Channel Mode Serial Data Format ..................................................... 29
Figure 18. 4-Channel Mode Serial Data Format ..................................................... 29
Figure 19. High-Bandwidth Mode Serial Data Format................................................. 30
Figure 21. 8-Channel TDM (24-Bit Samples, Padded with Zeros) ....................................... 32
Figure 22. 6-Channel TDM (24-Bit Samples, No Padding) ............................................. 32
Figure 20. Audio Channel Input Format............................................................ 32
Figure 23. Stereo I2S (24-Bit Samples, Padded with Zeros)............................................ 33
Figure 24. Stereo I2S (16-Bit Samples, No Padding).................................................. 33
Figure 25. GMSL UART Protocol for Base Mode .................................................... 34
Figure 26. GMSL UART Data Format for Base Mode................................................. 35
Figure 27. Sync Byte (0x79)..................................................................... 35
Figure 28. ACK Byte (0xC3)..................................................................... 35
Figure 29. Format Conversion between GMSL UART and I2C with Register Address (I2CMETHOD = 0) ........ 36
Figure 30. Format Conversion between GMSL UART and I2C without Register Address (I2CMETHOD = 1)...... 36

MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
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LIST OF FIGURES (continued)
Figure 31. START and STOP Conditions........................................................... 37
Figure 32. Bit Transfer ......................................................................... 37
Figure 33. Acknowledge........................................................................ 38
Figure 34. Slave Address....................................................................... 38
Figure 35. Format for I2C Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 36. Format for Write to Multiple Registers .................................................... 39
Figure 37. Format for I2C Read .................................................................. 39
Figure 38. 2:1 Coax Splitter Connection Diagram.................................................... 43
Figure 39. Coax Connection Diagram ............................................................. 43
Figure 40. State Diagram, CDS = LOW (Video Display Application) ..................................... 46
Figure 41. State Diagram, CDS = HIGH (Image Sensing Application) .................................... 47
Figure 42. Example Network with One Repeater and Two µCs (Tx = GMSL Serializers, Rx = Deserializers) ..... 53
Figure 43. Human Body Model ESD Test Circuit..................................................... 61
Figure 44. IEC 61000-4-2 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 45. ISO 10605 Contact Discharge ESD Test Circuit ............................................ 61

MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
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Table 1. Device Address Defaults (Register 0x00, 0x01) .............................................. 26
Table 2. Input Map (See Figure 15, Figure 16)...................................................... 27
Table 3. Data-Rate Selection Table............................................................... 30
Table 4. Maximum Audio WS Frequency (kHz) for Various RXCLKIN_ Frequencies......................... 31
Table 5. I2C Bit-Rate Ranges ................................................................... 40
Table 6. TP/COAX Drive Current (400mV Output Drive Levels) ..........................................41
Table 7. Serial Output Spread ....................................................................41
Table 8. Spread Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 9. Modulation Coefficients and Maximum SDIV Settings ......................................... 42
Table 10. CONF[1:0] Input Map .................................................................. 43
Table 11. Reverse Control Channel Modes ......................................................... 44
Table 12. Fast High-Immunity Mode Requirements................................................... 44
Table 13. Startup Procedure for Video-Display Applications (CDS = Low)................................. 45
Table 14. Startup Procedure for Image-Sensing Applications........................................... 46
Table 15. Startup, HDCP Authentication, and Normal Operation (Deserializer is not a Repeater)—First Part of the
HDCP Authentication Protocol................................................................... 49
Table 16. Link Integrity Check (Normal)—Performed Every 128 Frames After
Encryption is Enabled ......................................................................... 51
Table 17. Optional Enhanced Link Integrity Check—Performed Every 16 Frames After Encryption is Enabled .... 52
Table 18. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First and Second Parts of the
HDCP Authentication Protocol................................................................... 53
Table 19. MAX9277/MAX9281 Feature Compatibility ................................................. 58
Table 20. Line Fault Mapping.................................................................... 59
Table 21. Typical Power-Supply Currents (Using Worst-Case Input Pattern, VAVDD = VDVDD = VIOVDD = 1.8V,
VLVDSVDD = 3.3V, TA = +25°C, SSEN = High, No HDCP)............................................ 60
Table 22. Additional Supply Current from HDCP (MAX9281 Only)....................................... 60
Table 23. Suggested Connectors and Cables for GMSL .............................................. 61
Table 24. Register Table ....................................................................... 62
Table 25. HDCP Register Table (MAX9281 Only) .................................................... 68
LIST OF TABLES

AVDD to AGND ....................................................-0.5V to +1.9V
DVDD to AGND....................................................-0.5V to +1.9V
IOVDD to AGND...................................................-0.5V to +3.9V
LVDSVDD to AGND .............................................-0.5V to +3.9V
GND to AGND ......................................................-0.5V to +0.5V
LMN_ to AGND (15mA current limit) ....................-0.5V to +3.9V
OUT+, OUT- to AGND..........................................-0.5V to +1.9V
All Other Pins to AGND.......................-0.5V to (VIOVDD + 0.5V)
OUT+, OUT- Short Circuit to Ground or Supply........Continuous
Continuous Power Dissipation (TA = +70ºC)
TQFN (derate 40mW/ºC above +70ºC) ........................3200mW
Junction Temperature...................................................... +150ºC
Storage Temperature.........................................-65ºC to +150ºC
Lead Temperature (soldering, 10s) ................................. +300ºC
Soldering Temperature (reflow) ....................................... +260ºC
TQFN
Junction-to-Case Thermal Resistance (θJC)................ 1°C/W Junction-to-Ambient Thermal Resistance (θJA)......... 25°C/W
(Note 2)
(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, VLVDSVDD = 3.0V to 3.6V, RL = 100Ω ±1% (differential), TA = -40°C to +105°C,
unless otherwise noted. Differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID /2|.
Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25°C.) (Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SINGLE-ENDED INPUTS (CX/TP, PWDN, MS/CNTL0, CDS/CNTL3, SD, SCK, WS, AUTOS, CNTL1, CNTL2, HIM)
High-Level Input Voltage VIH1
(CX/TP, PWDN, MS/CNTL0, CDS/
CNTL3, AUTOS, HIM)
0.65 x
VIOVDD V
SD, SCK, WS, CNTL1, CNTL2 0.7 x
VIOVDD
Low-Level Input Voltage VIL1 0.35 x
VIOVDD V
Input Current IIN1 VIN = 0V to VIOVDD -10 +20 µA
THREE-LEVEL LOGIC INPUTS (CONF0, CONF1, ADD0, ADD1, BWS)
High-Level Input Voltage VIH 0.7 x
VIOVDD V
Low-Level Input Voltage VIL 0.3 x
VIOVDD V
Mid-Level Input Current IINM (Note 4) -10 +10 µA
Input Current IIN -150 +150 µA
SINGLE-ENDED OUTPUT (GPO)
High Level Output Voltage VOH1 IOUT = -2mA VIOVDD -
0.2 V
Low Level Output Voltage VOL1 IOUT = 2mA 0.2 V
OUTPUT Short-Circuit
Current IOS VOUT = 0V VIOVDD = 3.0V to 3.6V 16 35 64 mA
VIOVDD = 1.7V to 1.9V 3 12 21
MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
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Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Note 1: AGND, GND connected to PCB ground.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
DC Electrical Characteristics

(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, VLVDSVDD = 3.0V to 3.6V, RL = 100Ω ±1% (differential), TA = -40°C to +105°C,
unless otherwise noted. Differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID /2|.
Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25°C.) (Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
OPEN-DRAIN INPUT/OUTPUT (RX/SDA, TX/SCL, LFLT)
High-Level Input Voltage VIH2 0.7 x
VIOVDD V
Low-Level Input Voltage VIL2 0.3 x
VIOVDD V
Input Current IIN2 (Note 5) RX/SDA, TX/SCL -110 +5 µA
LFLT -80 +5
Low-Level Output Voltage VOL2 IOUT = 3mA VIOVDD = 1.7V to 1.9V 0.4 V
VIOVDD = 3.0V to 3.6V 0.3
Input Capacitance CIN Each pin (Note 9) 10 pF
DIFFERENTIAL SERIAL OUTPUT (OUT+, OUT-)
Di󰀨erential Output Voltage VOD
Pre-emphasis o󰀨 (Figure 1) 300 400 500
mV3.3dB preemphasis setting (Figure 2) 350 610
3.3dB deemphasis setting (Figure 2) 240 425
Change in VOD Between
Complementary Output States ΔVOD Preemphasis o󰀨, deemphasis only 15 mV
Output O󰀨set Voltage
(VOUT+ + VOUT-)/2 = VOS VOS Preemphasis o󰀨 1.1 1.4 1.56 V
Change in VOS between
Complementary Output States ΔVOS 15 mV
Output Short-Circuit Current IOS
VOUT+ or VOUT- = 0V -62 mA
VOUT+ or VOUT- = 1.9V 25
Magnitude of Di󰀨erential
Output Short-Circuit Current IOSD VOD = 0V 25 mA
Output Termination Resistance
(Internal) ROUT From OUT+, OUT- to VAVDD 45 54 63 Ω
SINGLE-ENDED SERIAL OUTPUT (OUT+, OUT-)
Single-Ended Output Voltage VOUT
Pre-emphasis o󰀨, high drive (Figure 3) 375 500 625
mV
3.3dB preemphasis setting, high drive
(Figure 2)435 765
3.3dB deemphasis setting, high drive
(Figure 2)300 535
Output Short-Circuit Current IOS
VOUT+ or VOUT- = 0V -69 mA
VOUT+ or VOUT- = 1.9V 32
Output Termination Resistance
(Internal) RO From OUT+ or OUT- to VAVDD 45 54 63 Ω
MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
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DC Electrical Characteristics (continued)

(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, VLVDSVDD = 3.0V to 3.6V, RL = 100Ω ±1% (differential), TA = -40°C to +105°C,
unless otherwise noted. Differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID /2|.
Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25°C.) (Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REVERSE CONTROL-CHANNEL RECEIVER (OUT+, OUT-)
High Switching Threshold VCHR
Normal-immunity mode 27 mV
High-immunity mode 40
Low Switching Threshold VCLR
Normal-immunity mode -27 mV
High-immunity mode -40
LINE FAULT DETECTION INPUT (LMN_)
Short-to-GND Threshold VTG (Figure 4) 0.3 V
Normal Threshold VTN (Figure 4) 0.57 1.07 V
Open Threshold VTO (Figure 4) 1.45 VIO +
0.06 V
Open Input Voltage VIO (Figure 4) 1.47 1.75 V
Short-to-Battery Threshold VTE (Figure 4) 2.47 V
LVDS INPUTS (RXIN_, RXCLKIN_)
Di󰀨erential Input High
Threshold VTH VCM = 1.2V 50 mV
Di󰀨erential Input Low
Threshold VTL VCM = 1.2V -50 mV
Input Di󰀨erential Termination
Resistance RTERM 85 110 135 Ω
Input Current IIN+, IIN-
PWDN = high or low, IN+ and IN- are
shorted -25 +25 µA
Power-O󰀨 Input Current IIN0+, IIN0- VAVDD = VDVDD = VIOVDD = 0V -40 +40 µA
POWER SUPPLY
Total Supply Current
(AVDD + DVDD + IOVDD)
(Note 6) (Worst-Case
Pattern) (Figure 5)
IWCS
BWS = low
fPCLKIN_ = 16.6MHz 100 125
mA
fPCLKIN_ = 33.3MHz 106 140
fPCLKIN_ = 66.6MHz 123 155
fPCLKIN_ = 104MHz 146 190
BWS = mid fPCLKIN_ = 36.6MHz 108 145
fPCLKIN_ = 104MHz 152 195
LVDSVDD Worst-Case
Supply Current (Figure 5,
Note 6)
IWCS
BWS = low
fPCLKIN_ = 16.6MHz 24 30
mA
fPCLKIN_ = 33.3MHz 24 30
fPCLKIN_ = 66.6MHz 24 30
fPCLKIN_ = 104MHz 24 30
BWS = mid fPCLKIN_ = 36.6MHz 29 35
fPCLKIN_ = 104MHz 29 35
MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
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DC Electrical Characteristics (continued)

(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, VLVDSVDD = 3.0V to 3.6V, RL = 100Ω ±1% (differential), TA = -40°C to +105°C,
unless otherwise noted. Differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID /2|.
Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25°C.) (Note 3)
(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, VLVDSVDD = 3.0V to 3.6V, RL = 100Ω ±1% (differential), TA = -40°C to +105°C,
unless otherwise noted. Differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|.
Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25°C.) (Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Sleep Mode Supply Current ICCS Single wake-up receiver enabled,
LVDS inputs not driven 42 170 µA
Power-Down Supply Current ICCZ PWDN = GND 6 120 µA
ESD PROTECTION
OUT+, OUT- (Note 6) VESD
Human body model, RD = 1.5kΩ,
CS = 100pF ±8
kV
IEC 61000-4-2,
RD = 330Ω,
CS = 150pF
Contact discharge ±10
Air discharge ±12
ISO 10605,
RD = 2kΩ,
CS = 330pF
Contact discharge ±10
Air discharge ±25
RXIN_, RXCLKIN_ (Note 7) VESD
Human body model, RD = 1.5kΩ,
CS = 100pF ±8
kV
IEC 61000-4-2,
RD = 330Ω,
CS = 150pF
Contact discharge ±6
Air discharge ±20
ISO 10605,
RD = 2kΩ,
CS = 330pF
Contact discharge ±8
Air discharge ±30
All Other Pins (Note 8) VESD Human body model, RD = 1.5kΩ,
CS = 100pF ±4 kV
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CLOCK INPUT (RXCLKIN)
Clock Frequency fRXCLKIN_
BWS = low, DRS = ‘1’ 8.33 16.66
MHz
BWS = low, DRS = ‘0’ 16.66 104
BWS = mid, DRS = ‘1’ 18.33 36.66
BWS = mid, DRS = ‘0’ 36.66 104
BWS = high, DRS = ‘1’ 6.25 12.5
BWS = high, DRS = ‘0’ 12.5 78
I2C/UART PORT TIMING
I2C/UART Bit Rate 9.6 1000 kbps
Output Rise Time tR30% to 70%, CL = 10pF to 100pF,
1kΩ pullup to IOVDD 20 150 ns
MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
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DC Electrical Characteristics (continued)
AC Electrical Characteristics

(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, VLVDSVDD = 3.0V to 3.6V, RL = 100Ω ±1% (differential), TA = -40°C to +105°C,
unless otherwise noted. Differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|.
Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25°C.) (Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Fall Time tF70% to 30%, CL = 10pF to 100pF,
1kΩ pullup to IOVDD 20 150 ns
I2C TIMING (Figure 6)
SCL Clock Frequency fSCL
Low fSCL range:
(I2CMSTBT = 010, I2CSLVSH = 10) 9.6 100 kHz
Mid fSCL range:
(I2CMSTBT 101, I2CSLVSH = 01) > 100 400 kHz
High fSCL range:
(I2CMSTBT = 111, I2CSLVSH = 00) > 400 1000 kHz
START Condition Hold Time tHD:STA fSCL range
Low 4.0
µsMid 0.6
High 0.26
Low Period of SCL Clock tLOW fSCL range
Low 4.7
µs
Mid 1.3
High
VIOVDD = 1.7V to
< 3V (Note 9) 0.6
VIOVDD = 3.0V
to 3.6V 0.5
High Period of SCL Clock tHIGH fSCL range
Low 4.0
µs
Mid 0.6
High 0.26
Repeated START Condition
Setup Time tSU:STA fSCL range
Low 4.7
µsMid 0.6
High 0.26
Data Hold Time tHD:DAT fSCL range
Low 0
µsMid 0
High 0
Data Setup Time tSU:DAT fSCL range
Low 250
ns
Mid 100
High 50
Setup Time for STOP
Condition tSU:STO fSCL range
Low 4.0
µsMid 0.6
High 0.26
Bus Free Time tBUF fSCL range
Low 4.7
µs
Mid 1.3
High 0.5
MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
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│ 12
AC Electrical Characteristics (continued)

(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, VLVDSVDD = 3.0V to 3.6V, RL = 100Ω ±1% (differential), TA = -40°C to +105°C,
unless otherwise noted. Differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|.
Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25°C.) (Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Data Valid Time
Note 14 tVD:DAT fSCL range
Low 3.45
µs
Mid 0.9
High
VIOVDD = 1.7V
to < 3V (Note
10)
0.55
VIOVDD = 3.0V
to 3.6V 0.45
Data Valid Acknowledge
Time
Note 14
tVD:ACK fSCL range
Low 3.45
µs
Mid 0.9
High
VIOVDD = 1.7V
to < 3V (Note
11)
0.55
VIOVDD = 3.0V
to 3.6V 0.45
Pulse Width of Spikes
Suppressed tSP fSCL range
Low 50
nsMid 50
High 50
Capacitive Load Each Bus
Line CBNote 12 100 pF
SWITCHING CHARACTERISTICS (Note 12)
Di󰀨erential Output Rise/Fall
Time tR, tF20% to 80%, VOD ≥ 400mV, RL = 100Ω, serial bit rate = 3.12Gbps 90 150 ps
Total Serial Output Jitter
(Di󰀨erential Output) tTSOJ1
3.12Gbps PRBS signal, measured at
VOD = 0V di󰀨erential, preemphasis
disabled (Figure 7)
0.21 UI
Deterministic Serial Output
Jitter (Di󰀨erential Output) tDSOJ2
3.12Gbps PRBS signal, measured at
VOD = 0V di󰀨erential, preemphasis
disabled (Figure 7)
0.09 UI
Total Serial Output Jitter
(Single-Ended Output) tTSOJ1 3.12Gbps PRBS signal, measured at VO/2, preemphasis disabled (Figure 3)0.19 UI
Deterministic Serial Output
Jitter (Single-Ended Output) tDSOJ2 3.12Gbps PRBS signal, measured at VO/2, preemphasis disabled (Figure 3)0.1 UI
CNTL_ Input Setup Time tSET (Figure 8) 3 ns
CNTL_ Input Hold Time tHOLD (Figure 8) 1.5 ns
RXIN_ Skew Margin tRSKM No RXCLKIN spread (Figure 9) 0.3 UI
MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
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│ 13
AC Electrical Characteristics (continued)

(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, VLVDSVDD = 3.0V to 3.6V, RL = 100Ω ±1% (differential), TA = -40°C to +105°C,
unless otherwise noted. Differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|.
Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25°C.) (Note 3)
Note 3: Limits are 100% production tested at TA = +105°C. Limits over the operating temperature range are guaranteed by design
and characterization, unless otherwise noted.
Note 4: To provide a midlevel, leave the input open, or, if driven, put driver in high impedance. High-impedance leakage current
must be less than ±10μA.
Note 5: IIN MIN due to voltage drop across the internal pullup resistor.
Note 6: HDCP not enabled (MAX9281 only). See Table 22 for additional supply current when HDCP is enabled.
Note 7: Specified pin to ground.
Note 8: Specified pin to all supply/ground.
Note 9: The I2C bus standard tLOW min = 0.5µs.
Note 10:The I2C bus standard tVD:DAT max = 0.45µs.
Note 11:The I2C bus standard tVD:ACK max = 0.45µs.
Note 12: Not production tested. Guaranteed by design.
Note 13: Measured in serial link bit times. Bit time = 1/(30 x fPCLKIN) for BWS = ‘0’ or open. Bit time = 1/(40 x fPCLKIN)
for BWS = ‘1’.
Note 14: I2C valid times apply only when the device is operating as a local side device.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GPI to GPO Delay tGPIO Deserializer GPI to serializer GPO
(Figure 10)350 µs
Serializer Delay (Note 13) tSD (Figure 11)Spread-spectrum enabled 5440 Bits
Spread-spectrum disabled 1920
Link Start Time tLOCK (Figure 12) 3.5 ms
Power-Up Time tPU (Figure 13) 8 ms
I2S/TDM INPUT TIMING
WS Frequency fWS (See Table 5) 8 192 kHz
Sample Word Length nWS (See Table 5) 8 32 Bits
SCK Frequency fSCK fSCK = fWS x nWS x (2 or 8) (8 x 2) x 2 (192 x 32) x 8 kHz
SCK Clock High Time tHC VSCK ≥ VIH, tSCK = 1/fSCK (Note 13) 0.35 x tSCK ns
SCK Clock Low Time tLC VSCK ≥ VIL, tSCK = 1/fSCK (Note 13) 0.35 x tSCK ns
SD, WS Setup Time tSET (Figure 14, Note 13) 2 ns
SD, WS Hold Time tHOLD (Figure 14, Note 13) 2 ns
MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
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│ 14
AC Electrical Characteristics (continued)

(VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25°C, unless otherwise noted.)
120
130
140
150
160
170
180
515 25 35 45 55 65 75 85 95 105
SUPPLY CURRENT (mA)
RXCLKIN FREQUENCY (MHz)
SUPPLY CURRENT
vs. RXCLKIN FREQUENCY (BWS = LOW)
toc01
PRBS ON,
COAX MODE,
SS OFF,
HDCP OFF
PREEMPHASIS = 0x00
PREEMPHASIS =
0x01 to 0x04
PREEMPHASIS =
0x0B to 0x0F
120
130
140
150
160
170
180
15 30 45 60 75 90 105
SUPPLY CURRENT (mA)
RXCLKIN FREQUENCY (MHz)
SUPPLY CURRENT
vs. RXCLKIN FREQUENCY (BWS = OPEN)
toc02
PRBS ON,
COAX MODE,
SS OFF,
HDCP OFF
PREEMPHASIS = 0x00
PREEMPHASIS =
0x01 to 0x04
PREEMPHASIS =
0x0B to 0x0F
120
130
140
150
160
170
180
520 35 50 65 80
SUPPLY CURRENT (mA)
RXCLKIN FREQUENCY (MHz)
SUPPLY CURRENT
vs. RXCLKIN FREQUENCY (BWS = HIGH)
toc03
PRBS ON,
COAX MODE,
SS OFF,
HDCP OFF
PREEMPHASIS = 0x00
PREEMPHASIS =
0x01 to 0x04
PREEMPHASIS =
0x0B to 0x0F
120
130
140
150
160
170
180
515 25 35 45 55 65 75 85 95 105
SUPPLY CURRENT (mA)
RXCLKIN FREQUENCY (MHz)
SUPPLY CURRENT
vs. RXCLKIN FREQUENCY (BWS = LOW)
toc04
PRBS ON,
COAX MODE,
PE OFF,
HDCP OFF
ALL SPREAD
VALUES
120
130
140
150
160
170
180
15 30 45 60 75 90 105
SUPPLY CURRENT (mA)
RXCLKIN FREQUENCY (MHz)
SUPPLY CURRENT
vs. RXCLKIN FREQUENCY (BWS = OPEN)
toc05
PRBS ON,
COAX MODE,
PE OFF,
HDCP OFF
ALL SPREAD
VALUES
MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
Maxim Integrated │ 15
www.maximintegrated.com
Typical Operating Characteristics

(VAVDD = VDVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25°C, unless otherwise noted.)
120
130
140
150
160
170
180
520 35 50 65 80
SUPPLY CURRENT (mA)
RXCLKIN FREQUENCY (MHz)
SUPPLY CURRENT
vs. RXCLKIN FREQUENCY (BWS = HIGH)
toc06
PRBS ON,
COAX MODE,
PE OFF,
HDCP OFF
ALL SPREAD
VALUES
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
31 31.5 32 32.5 33 33.5 34 34.5 35 35.5
OUTPUT POWER (dBm)
RXCLKIN FREQUENCY (MHz)
OUTPUT SPECTURM
vs. RXCLKIN FREQUENCY
(VARIOUS SPREAD) toc07
2% SPREAD
0% SPREAD
1% SPREAD
0.5% SPREAD
4% SPREAD
fPCLKIN = 33.3MHz
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
62 63 64 65 66 67 68 69 70 71
OUTPUT POWER (dBm)
RXCLKIN FREQUENCY (MHz)
OUTPUT SPECTURM
vs. RXCLKIN FREQUENCY
(VARIOUS SPREAD) toc08
2% SPREAD
0% SPREAD
1% SPREAD
0.5% SPREAD
4% SPREAD
fPCLKIN = 66.6MHz
0
20
40
60
80
100
120
0 5 10 15 20 25
RXCLKIN FREQUENCY (MHz)
CABLE LENGTH (m)
MAXIMUM RXCLKIN FREQUENCY
vs. COAX CABLE LENGTH (BER ≤ 10-10)
toc09
BER CAN BE AS LOW AS 10-12 FOR
CABLE LENGTHS LESS THAN 15m
OPTIMUM
PE/EQ
NO PE,
10.7dB EQ
NO PE/EQ
MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
Maxim Integrated │ 16
www.maximintegrated.com
Typical Operating Characteristics (continued)

PIN NAME FUNCTION
1–4, 7,
8, 11, 12
RXIN_-,
RXIN_+
LVDS Data Inputs. Set BWS = low to use RXIN0_ to RXIN2_ (3-channel mode). Set BWS = high or
open to use RXIN0_ to RXIN3_ (4-channel or high-bandwidth mode). Certain data bits encrypted
when HDCP is enabled (MAX9281 only, Table 2)
5, 14 LVDSVDD 3.3V LVDS Power Supply. Bypass LVDSVDD to AGND with 0.1µF and 0.001µF capacitors as close
as possible to the device with the smallest value capacitor closest to LVDSVDD.
6, 13, 21, 29 AGND Analog and LVDS Ground
9, 10 RXCLKIN-,
RXCLKIN+ LVDS Clock Input. Provides the PLL reference clock.
15, 32, 47 AVDD 1.8V Analog Power Supply. Bypass AVDD to EP with 0.1µF and 0.001µF capacitors as close as
possible to the device with the smaller capacitor closest to AVDD.
16 SD
I2S/TDM Serial-Data Input with Internal Pulldown to GND. Disable I2S/TDM encoding to use SD as
an additional control/data input latched on the selected edge of PCLKIN. Encrypted when HDCP is
enabled.
17 SCK I2S/TDM Serial-Clock Input with Internal Pulldown to GND
TOP VIEW
MAX9277
MAX9281
TQFN
(7mm x 7mm x 0.75mm)
13
14
15
16
17
18
19
20
21
22
23
24
AGND
+LVDSVDD
AVDD
SD
SCK
WS
CNTL1
CNTL2
AGND
DVDD
GND
IOVDD
48
47
46
45
44
43
42
41
40
39
38
37
123 4 5 6 7 8 9 10 11 12
CX/TP
*CONNECT EP TO GROUND PLANE
AVDD *EP
ADD1
AUTOS
MS/CNTL0
CDS/CNTL3
PWDN
BWS
ADD0
DVDD
GND
IOVDD
RXIN3+
RXIN3-
RXCLKIN+
RXCLKIN-
RXIN2+
RXIN2-
AGND
LVDSVDD
RXIN1+
RXIN1-
RXIN0+
RXIN0-
36 35 34 33 32 31 30 29 28 27 26 25
RX/SDA TX/SCL CONF1 LMN1 AGND OUT- OUT+ AVDD LMN0 LFLT
GPO/HIM
CONF0
MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
www.maximintegrated.com Maxim Integrated
│ 17
Pin Description
Pin Conguration

PIN NAME FUNCTION
18 WS I2S/TDM Word-Select Input with Internal Pulldown to GND
19 CNTL1
Control Input With Internal Pulldown to GND. Input data is latched every RXCLKIN_ cycle (Figure
15). CNTL1 is not available in 3-channel mode (BWS = low). Set BWS = high or open (4-channel or
high-bandwidth mode) to use this input. CNTL1 not encrypted when HDCP is on (MAX9281 only)
CNTL1 or RES (“Reserved” from VESA Standard Panel Specication) is mapped to internal bit
DIN27. See the Reserved Bit (RES)/CNTL1 section.
20 CNTL2
Control Input With Internal Pulldown to GND. Input data is latched every RXCLKIN_ cycle (Figure
15). CNTL2 is not available in 3-channel mode (BWS = low). Set BWS = high or open (4-channel or
high-bandwidth mode) to use this input. CNTL2 not encrypted when HDCP is on (MAX9281 only).
CNTL2 is mapped to internal bit DIN28.
22, 39 DVDD 1.8V Digital Power Supply. Bypass DVDD to GND with 0.1µF and 0.001µF capacitors as close as
possible to the device with the smaller value capacitor closest to DVDD.
23, 38 GND Digital and I/O Ground
24, 37 IOVDD
I/O Supply Voltage. 1.8V to 3.3V logic I/O Power Supply. Bypass IOVDD to GND with 0.1µF and
0.001µF capacitors as close as possible to the device with the smallest value capacitor closest to
IOVDD. IOVDD sets the voltage levels for all pins except for the LVDS inputs and OUT+/-.
25 RX/SDA
UART Receive/I2C Serial Data Input/Output with Internal 30kΩ Pullup to IOVDD. Function is
determined by the state of CONF[1:0] at power-up (Table 10). RX/SDA has an open-drain driver and
requires a pullup resistor.
RX: Input of the serializer’s UART.
SDA: Data input/output of the serializer’s I2C Master/Slave.
26 TX/SCL
UART Transmit/I2C Serial Clock Input/Output with Internal 30kΩ Pullup to IOVDD. Function is
determined by the state of CONF[1:0] at power-up (Table 10). TX/SCL has an open-drain driver and
requires a pullup resistor.
TX: Output of the serializer’s UART.
SCL: Clock input/output of the serializer’s I2C Master/Slave.
27 CONF1
Three-Level Conguration Input. The state of CONF1 latches at power-up or when resuming
from power-down mode (PWDN = low). Use 6kΩ (max) for pullup to IOVDD/pulldown to GND.
See Table 10 for details.
28 LMN1 Line-Fault Monitor Input 1 (see Figure 4 for details)
30 OUT- Inverting CML Coax/Twisted-Pair Serial Output
31 OUT+ Noninverting CML Coax/Twisted-Pair Serial Output
33 LMN0 Line-Fault Monitor Input 0 (see Figure 4 for details)
34 LFLT Active-Low Open-Drain Line-Fault Output. LFLT has a 60kΩ internal pullup to IOVDD. LFLT = low
indicates a line fault. LFLT is output high when PWDN = low.
35 GPO/HIM
General-Purpose Output/High Immunity Mode Input. Functions as HIM input with internal pulldown
to GND at power-up or when resuming from power-down mode (PWDN = low), and switches to GPO
output automatically after power-up.
HIM: Default HIGHIMM bit value is latched at power-up or when resuming from power-down mode
(PWDN = low) and is active-high. Connect HIM to IOVDD with a 30kΩ or less pullup resistor to set
high or leave open to set low. HIGHIMM can be programmed to a di󰀨erent value after power-up.
HIGHIMM in the deserializer must be set to the same value.
GPO: Output follows the state of the GPI (or INT) input on the deserializer. GPO is low after power-
up or when PWDN is low.
MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
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│ 18
Pin Description (continued)

PIN NAME FUNCTION
36 CONF0
Three-Level Conguration Input. The state of CONF0 latches at power-up or when resuming
from power-down mode (PWDN = low). Use 6kΩ (max) for pullup to IOVDD/pulldown to GND.
See Table 10 for details.
40 ADD0
Three-Level Address Selection Input. The state of ADD0 latches at power-up or when resuming from
power-down mode (PWDN = low). Use 6kΩ (max) for pullup to IOVDD/pulldown to GND. See Table
1for details.
41 BWS
Three-Level Bus Width Select Input. Set BWS to the same level on both sides of the serial link.
Set BWS = low with 6kΩ (max) pulldown for 3-channel mode. Set BWS = high with 6kΩ (max) pullup
to IOVDD for 4-channel mode.
Set BWS = open for high-bandwidth mode.
42 PWDN Active-Low, Power-Down Input with Internal Pulldown to EP. Set PWDN low to enter power-down
mode to reduce power consumption.
43 CDS/CNTL3
Control Direction Selection/Auxiliary Control Signal Input with Internal Pulldown to GND. Function is
determined by the CDSCNTL3 register bit and defaults to CDS on power-up.
CDS (CDSCNTL3 = 0): Control link direction selection input with internal pulldown to GND.
Set CDS = low when the control channel master µC is connected at the serializer. Set CDS = high
when the control channel master µC is connected at the deserializer.
CNTL3 (CDSCNTL3 = 1): Used only in high-bandwidth mode (BWS = open). CNTL3 not encrypted
when HDCP is enabled (MAX9281 only).
44 MS/CNTL0
Mode Select/Auxiliary Control Signal Input with Internal Pulldown to GND. Function is determined by
the MSCNTL0 register bit and defaults to MS on power-up.
MS (MSCNTL0 = 0): Set MS = low, to select base mode. Set MS = high to select the bypass mode.
CNTL0 (MSCNTL0 = 1): Used only in high-bandwidth mode (BWS = open). CNTL0 not encrypted
when HDCP is enabled (MAX9281 only).
45 AUTOS
Active-Low Auto-Start Input With Internal Pulldown to GND. Set AUTOS = high, to disable
serialization at power-up or when resuming from power-down mode (PWDN = low). Set AUTOS =
low, to enable serialization and automatic PLL range selection power-up or when resuming from
power-down mode.
46 ADD1
Three-Level Address Selection Input. The state of ADD1 latches at power-up or when resuming from
power-down mode (PWDN = low). Use 6kΩ (max) for pullup to IOVDD/pulldown to GND. See Table
1for details.
48 CX/TP Coax/Twisted Pair Input With Internal Pulldown to GND. Set CX/TP low for twisted-pair cable drive
(di󰀨erential output). Set CX/TP high for coax cable drive (single-ended output).
— EP Exposed Pad. EP is internally connected to AGND. MUST connect EP to the PCB ground plane
through an array of vias for proper thermal and electrical performance.
MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
www.maximintegrated.com Maxim Integrated
│ 19
Pin Description (continued)

SCRAMBLE /
PARITY/
8b/10b/
9b/10b/
ENCODE
LVDS TO
PARALLEL
CNTL1 (4-CH)
CNTL1 (9b10b)
PARALLEL
TO
SERIAL
MAX9277
MAX9281
REVERSE
CONTROL
CHANNEL
HDCP
ENCRYPT
(MAX9281
ONLY)
HDCP
DECRYPT
CONTROL
MS, CDS
UART/I
2
C
GPO/ HIMSD SCK WS TX /SCL RX /SDA AUTOSBWS CONF[3:0] ADD[1:0]
HDCP
KEYS
RGB
HS
VS
DE
HS
VS
DE
ACB
CNTL[3:0]
(9b10b)
DIN[28:27]
(30-BIT)
FCC
HDCP
CONTROL
AUDIO
FIFO
7x PLL
CONTROL
(9b10b)
SYNC
VIDEO
CLKDIV
SSPLL
RES/CNTL1
(4-CH)
CNTL0/MS,
CNTL3/CDS
CNTL2
CNTL1
RXIN3 (4CH)
RXIN2
RXIN1
RXIN0
RXCLKIN
RGB[23:18]
(4 CH OR 9b10b)
RGB[17:0]
CML TX
LMN1
LMN0
LFLT
OUT+
CX/TP
OUT-
RX
PWDN
FILTER
PLL LINE
FAULT
DETECT
CNTL2 (4-CH)
CNTL2 (9b10b)
CNTL0 CNTL3 (9b10b)
MS, CDS
MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
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│ 20
Functional Diagram