Maxim Integrated MAX77734 User manual

Maxim Integrated Page 1 of 15
MAX77734 I2C-Compatible Serial Interface
Implementation Guide
UG6464; Rev 0; 8/17
Abstract
This document serves as a guide to engineers designing with the MAX77734 serial interface. It details
the various communication protocols implemented in the 2-wire serial interface block of the
MAX77734, as well as some general information on the I
2
C specification.

Maxim Integrated Page 2 of 15
Table of Contents
Overview .............................................................................................................................................................................4
Features ...............................................................................................................................................................................4
Simplified Block Diagram................................................................................................................................................5
System Configuration ......................................................................................................................................................5
Hardware Implementation and Interface Power ......................................................................................................6
Data Transfer .....................................................................................................................................................................6
START and STOP Conditions ........................................................................................................................................6
Acknowledge Bit................................................................................................................................................................7
Slave Address.....................................................................................................................................................................7
Clock Stretching ................................................................................................................................................................7
General Call Address .......................................................................................................................................................7
Device ID.............................................................................................................................................................................7
Communication Speed ....................................................................................................................................................7
Communication Protocols ..............................................................................................................................................9
Writing to a Single Register.......................................................................................................................................9
Writing Multiple Bytes to Sequential Registers .................................................................................................10
Reading from a Single Register ............................................................................................................................... 12
Reading from Sequential Registers........................................................................................................................ 13
Engaging High-Speed Mode (HS-Mode) for Operation Up to 3.4MHz......................................................14
Revision History............................................................................................................................................................... 15

Maxim Integrated Page 3 of 15
List of Figures
Figure 1. Simplified block diagram. ...............................................................................................................................5
Figure 2. I2C system configuration. ..............................................................................................................................5
Figure 3. I2C START and STOP conditions. ................................................................................................................6
Figure 4. Writing to a single register. ..........................................................................................................................9
Figure 5. Writing multiple bytes...................................................................................................................................11
Figure 6. Reading from a single register.................................................................................................................... 12
Figure 7. Reading from multiple registers................................................................................................................. 13
Figure 8. Engaging high-speed mode.........................................................................................................................14
List of Tables
Table 1. MAX77734 Slave Addresses .........................................................................................................................7

Maxim Integrated Page 4 of 15
Overview
The MAX77734 features a revision 3.0 I2C-compatible, 2-wire serial interface consisting of a
bidirectional serial data line (SDA) and a serial clock line (SCL). As shown in the Simplified Block
Diagram, the I2C SDA and SCL signals are internally decoded by the devices used to communicate with
the top-level control logic as well as the charger, LDO, and current sinks. The MAX77734 is a slave-only
device that relies on an external bus master to generate SCL. SCL clock rates from 0Hz to 3.4MHz are
supported. I2C is an open-drain bus and, therefore, SDA and SCL require pullups.
The MAX77734 I2C communication controller implements 7-bit slave addressing. An I2C bus master
initiates communication with the slave by issuing a START condition followed by the slave address. The
OTP address is factory programmable for one of two options. All slave addresses not mentioned in the
slave address table (Table 1) are not acknowledged.
The devices use 8-bit registers with 8-bit register addressing. They support standard communication
protocols: (1) writing to a single register, (2) writing to multiple sequential registers with an
automatically incrementing data pointer, (3) reading from a single register, and (4) reading from
multiple sequential registers with an automatically incrementing data pointer.
For additional information on the I2C protocols, refer to the I2C bus specification available from NXP
(Philips) Semiconductors.
Features
• I2C Revision 3-Compatible Serial Communications Channel
• 0Hz to 100kHz (Standard Mode)
• 0Hz to 400kHz (Fast Mode)
• 0Hz to 1MHz (Fast Mode Plus)
• 0Hz to 3.4MHz (High-Speed Mode)
• Does not utilize I2C clock stretching

Maxim Integrated Page 5 of 15
Simplified Block Diagram
Figure 1. Simplified block diagram.
System Configuration
The I
2
C bus is a multimaster bus. The maximum number of devices that can attach to the bus is only
limited by bus capacitance.
A device on the I
2
C bus that sends data to the bus is called a transmitter. A device that receives data
from the bus is called a receiver. The device that initiates a data transfer and generates the SCL clock
signals to control the data transfer is a master. Any device that is being addressed by the master is
considered a slave. The MAX77734 I
2
C-compatible interface operates as a slave on the I
2
C bus with
transmit and receive capabilities.
Figure 2. I
2
C system configuration.

Maxim Integrated Page 6 of 15
Hardware Implementation and Interface Power
The MAX77734 I
2
C interface derives its power from V
IO
. Typically, a power input such as V
IO
would
require a local 0.1μF ceramic bypass capacitor to ground. However, in highly integrated power
distribution systems, a dedicated capacitor might not be necessary. If the impedance between V
IO
and
the next closest capacitor (≥0.1μF) is less than 100mΩin series with 10nH, then a local capacitor is not
needed. Otherwise, bypass V
IO
to GND with a 0.1µF ceramic capacitor.
V
IO
accepts voltages from 1.7V to 3.6V. Cycling V
IO
does not reset the I
2
C registers. V
SYS
must drop below
SYSPOR for the registers to reset. When V
IO
is less than V
IOUVLO
and V
SYS
is less than V
SYSUVLO
, SDA and
SCL are high impedance. Note that I
2
C is an open-drain bus and requires pullup resistors. Typical
applications place these pullups near the host controller.
Data Transfer
One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals. See the I
2
C
START and STOP Conditions section. Each transmit sequence is framed by a START (S) condition and a
STOP (P) condition. Each data packet is nine bits long: eight bits of data followed by the acknowledge
bit. Data is transferred with the MSB first.
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle high. A master device initiates communication
by issuing a START condition. A START condition is a high-to low transition on SDA with SCL high. A
STOP condition is a low-to-high transition on SDA, while SCL is high.
A START condition from the master signals the beginning of a transmission to the MAX77734. The
master terminates transmission by issuing a not-acknowledge followed by a STOP condition (see the
Acknowledge Bit section for information on not-acknowledge). The STOP condition frees the bus. To
issue a series of commands to the slave, the master can issue repeated START (Sr) commands instead
of a STOP command to maintain control of the bus. In general, a repeated START command is
functionally equivalent to a regular START command.
When a STOP condition or incorrect address is detected, the MAX77734 internally disconnects SCL
from the serial interface until the next START condition, minimizing digital noise and feedthrough.
Figure 3. I
2
C START and STOP conditions.

Maxim Integrated Page 7 of 15
Acknowledge Bit
Both the I2C bus master and the MAX77734 (slave) generate acknowledge bits when receiving data.
The acknowledge bit is the last bit of each 9-bit data packet. To generate an acknowledge (A), the
receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth
pulse) and keep it low during the high period of the clock pulse. To generate a not-acknowledge (NA),
the receiving device allows SDA to be pulled high before the rising edge of the acknowledge-related
clock pulse and leaves it high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful
data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an
unsuccessful data transfer, the bus master should reattempt communication at a later time.
The MAX77734 issues an ACK for all register addresses in the possible address space even if the
particular register does not exist.
Slave Address
Refer to the I2C Serial Interface and the Ordering Information section of the MAX77734 IC data sheet for
more information.
Table 1. MAX77734 Slave Addresses
ADDRESS 7-BIT SLAVE ADDRESS 8-BIT WRITE ADDRESS 8-BIT READ ADDRESS
Main Address (ADDR = 1) 0x48, 0b 100 1000 0x90 0b 1001 0000 0x91, 0b 1001 0001
Main Address (ADDR= 0) 0x40, 0b 100 0000 0x80, 0b 1000 0000 0x81, 0b 1000 0001
Test Mode 0x49, 0b 100 1001 0x92, 0b 1001 0010 0x93, 0b 1001 0011
Clock Stretching
In general, the clock signal generation for the I2C bus is the responsibility of the master device. The I2C
specification allows slow slave devices to alter the clock signal by holding down the clock line. The
process in which a slave device holds down the clock line is typically called clock stretching. The
MAX77734 does not use any form of clock stretching to hold down the clock line.
General Call Address
The MAX77734 does not implement the I2C specification’s general call address. If the MAX77734 sees
the general call address (0b0000_0000), it does not issue an acknowledge.
Device ID
The MAX77734 does not support the I2C Device ID feature.
Communication Speed
The MAX77734 is compatible with all four communication speed ranges as defined by the Revision 3
I2C specification:
• 0Hz to 100kHz (Standard Mode)
• 0Hz to 400kHz (Fast Mode)
• 0Hz to 1MHz (Fast Mode Plus)
• 0Hz to 3.4MHz (High-Speed Mode)

Maxim Integrated Page 8 of 15
Operating in standard mode, fast mode, and fast mode plus does not require any special protocols. The
main consideration when changing the bus speed through this range is the combination of the bus
capacitance and pullup resistors. Higher time constants created by the bus capacitance and pullup
resistance (C x R) slow the bus operation. Therefore, when increasing bus speeds, the pullup resistance
must be decreased to maintain a reasonable time constant. Refer to the Pullup Resistor Sizing section of
the I2C bus specification and user manual (available for free online) for detailed guidance on the pullup
resistor selection. In general, for bus capacitances of 200pF, a 100kHz bus needs 5.6kΩpullup resistors,
a 400kHz bus needs approximately 1.5kΩpullup resistors, and a 1MHz bus needs 680Ωpullup resistors.
Note that when the open-drain bus is low, the pullup resistor is dissipating power, and lower value pullup
resistors dissipate more power (V2/R).
Operating in high-speed mode requires some special considerations. For a full list of considerations,
refer to the I2C bus specification and user manual. The major considerations with respect to the
MAX77734 include the following:
• The I2C bus master should use current source pullups to shorten the signal rise time.
• The I2C slave must use a different set of input filters on its SDA and SCL lines to accommodate
for the higher bus speed.
• The communication protocols need to utilize the high-speed master code.
At power-up and after each STOP condition, the MAX77734 input filters are set for standard mode, fast
mode, and fast mode plus (i.e., 0Hz to 1MHz). To switch the input filters for high-speed mode, use the
high-speed master code protocols that are described in the Communication Protocols section.

Maxim Integrated Page 9 of 15
Communication Protocols
The MAX77734 supports both writing and reading from its registers.
Writing to a Single Register
Figure 4 shows the protocol for the I
2
C master device to write one byte of data to the MAX77734. This
protocol is the same as the SMBus specification’s write-byte protocol.
The write-byte protocol is as follows:
1. The master sends a START command (S).
2. The master sends the 7-bit slave address followed by a write bit (R/W= 0).
3. The addressed slave asserts an acknowledge (A) by pulling SDA low.
4. The master sends an 8-bit register pointer.
5. The slave acknowledges the register pointer.
6. The master sends a data byte.
7. The slave updates with the new data
8. The slave acknowledges or not-acknowledges the data byte. The next rising edge on SDA loads
the data byte into its target register and the data becomes active.
9. The master sends a STOP condition (P) or a repeated START condition (Sr). Issuing a P ensures
that the bus input filters are set for 1MHz or slower operation. Issuing an Sr leaves the bus input
filters in their current state.
Figure 4. Writing to a single register.

Maxim Integrated Page 10 of 15
Writing Multiple Bytes to Sequential Registers
Figure 5 shows the protocol for writing to sequential registers. This protocol is similar to the write-byte
protocol above, except the master continues to write after it receives the first byte of data. When the
master is done writing it issues a STOP or repeated START.
The writing to sequential registers protocol is as follows:
1. The master sends a START command (S).
2. The master sends the 7-bit slave address followed by a write bit (R/W= 0).
3. The addressed slave asserts an acknowledge (A) by pulling SDA low.
4. The master sends an 8-bit register pointer.
5. The slave acknowledges the register pointer.
6. The master sends a data byte.
7. The slave acknowledges the data byte. The next rising edge on SDA load the data byte into its
target register and the data becomes active.
8. Steps 6 to 7 are repeated as many times as the master requires.
9. During the last acknowledge related clock pulse, the master can issue an acknowledge or a not-
acknowledge.
10. The master sends a STOP condition (P) or a repeated START condition (Sr). Issuing a P ensures
that the bus input filters are set for 1MHz or slower operation. Issuing an Sr leaves the bus input
filters in their current state.