Maxim MAX4888A User manual

General Description
The MAX4888A/MAX4889A high-speed passive switches
route PCI Express®(PCIe) data between two possible
destinations. The MAX4888A is a quad single-pole/dou-
ble-throw (4 x SPDT) switch ideally suited for switching
two half lanes of PCIe data between two destinations. The
MAX4889A is an octal single-pole/double-throw (8 x
SPDT) switch ideal for switching four half lanes of PCIe
data between four destinations. The MAX4888A/
MAX4889A feature a single digital control input (SEL) to
switch signal paths.
The MAX4888A/MAX4889A are fully specified to oper-
ate from a single +3.0V to +3.6V power supply††. The
MAX4888A is available in a 3.5mm x 5.5mm, 28-pin
TQFN package. The MAX4889A is available in a 3.5mm
x 9.0mm, 42-pin TQFN package. Both devices operate
over the -40°C to +85°C temperature range.
Features
♦Single +3.0V to +3.6V Power-Supply Voltage
♦Low Same-Pair Skew of 7ps
♦Low 120µA (Max) Quiescent Current
♦Supports PCIe Gen I and Gen || Data Rates
♦Flow-Through Pin Configuration for Ease of
Layout
♦Industry-Compatible Pinout
♦Lead-Free Packaging
Applications
Desktop Computers
Servers/Storage Area Networks
Laptops
MAX4888A/MAX4889A
5.0Gbps PCI Express Passive Switches
________________________________________________________________ Maxim Integrated Products 1
MAX4888A
TOP VIEW
TQFN
11
12
13
14
V+
GND
*EP
V+
GND
28
+
27
26
25
V+
GND
V+
GND
12345678910
24 23 22 21 20 19 18 17 16 15
GND
N.C.
V+
COM2-
COM2+
COM1-
COM1+
N.C.
SEL
GND
NO2- NO2+ NO1- NO1+ V+ GND NC2- NC2+ NC1- NC1+
MAX4889A
TQFN
18
19
20
21
V+
GND
V+
GND
42
+
41
40
39
V+
GND
V+
GND
1234567891011121314151617
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
COM3-
V+
GND
COM4+
COM4-
GND
COM3+
GND
SEL
V+
COM2-
COM2+
V+
GND
COM1-
COM1+
GND
NC4+ NC4- NO3+ NO3- NO4+ NO4- NC3- NC3+ V+ NO2- NO2+ NO1- NO1+ NC2- NC2+ NC1- NC1+
*CONNECT EXPOSED PADDLE TO GROUND.
*EP
Pin Configurations
19-0770; Rev 2; 5/09
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
Typical Application Circuit appears at end of data sheet.
††Contact factory if operating at +2.5V or +1.8V.
PCI Express is a registered trademark of PCI-SIG Corp.
PART TEMP RANGE PIN-PACKAGE CONFIGURATION
MAX4888AETI+ -40°C to +85°C 28 TQFN-EP* Two Half Lanes
MAX4889AETO+ -40°C to +85°C 42 TQFN-EP* Four Half Lanes
Ordering Information/Selector Guide
+ Denotes lead(Pb)-free/RoHS-compliant package.
* EP = Exposed paddle.

MAX4888A/MAX4889A
5.0Gbps PCI Express Passive Switches
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V+ = +3.0V to +3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at V+ = +3.3V, TA= +25°C.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND, unless otherwise noted.)
V+ .............................................................................-0.3V to +4V
SEL, COM__, NO__, NC__ (Note 1) .............-0.3V to (V+ + 0.3V)
| COM__ - NO__ |, | COM__ - NC__ | (Note 1).................0 to +2V
Continuous Current (COM_ to NO__/NC__) .....................±70mA
Peak Current (COM__ to NO__/NC__)
(pulsed at 1ms, 10% duty cycle)..................................±70mA
Continuous Current (SEL).................................................±30mA
Peak Current (SEL)
(pulsed at 1ms, 10% duty cycle)................................±150mA
Continuous Power Dissipation (TA= +70°C)
28-Pin TQFN (derate 20.8mW/°C above +70°C) ....1666.7mW
42-Pin TQFN (derate 35.7mW/°C above +70°C) ....2857.1mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Junction Temperature......................................................+150°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ANALOG SWITCH
Analog-Signal Range VCOM_,
VNO_, VNC_ (V+ - 1.2) V
Voltage Between COM and
NO/NC
| VCOM_ -
VNO_ | ,
| VCOM_ -
VNC_ |
0 1.8 V
On-Resistance RON V+ = +3.0V, ICOM_ = 15mA,
VNO_ or VNC_ = 0V, +1.8V 7 
On-Resistance Match Between
Pairs of Same Channel RON V+ = +3.0V, ICOM_ = 15mA, VNO_ or VNC_ = 0V (Notes 3, 4) 0.1 1 
On-Resistance Match
Between Channels RON V+ = +3.0V, ICOM_ = 15mA, VNO_ or VNC_ = 0V (Notes 3, 4) 0.6 2 
On-Resistance Flatness RFLAT(ON) V+ = +3.0V, ICOM_ = 15mA
VNO_ or VNC_ = 0V, +1.8V (Notes 4, 5) 0.06 2 
NO_ or NC_ Off-Leakage
Current
INO_(OFF)
INC_(OFF)
V+ = +3.6V, VCOM_ = 0V, +1.8V,
VNO_ or VNC_ = +1.8V, 0V -1 +1 μA
COM_ On-Leakage
Current ICOM_(ON) V+ = +3.6V, VCOM_ = 0V, +1.8V, VNO_ or VNC_ = VCOM_or unconnected -1 +1 μA
Note 1: Signals on SEL, NO__, NC__ or COM__ exceeding V+ or GND are clamped by internal diodes. Limit forward-diode current
to maximum current rating.

MAX4888A/MAX4889A
5.0Gbps PCI Express Passive Switches
_______________________________________________________________________________________ 3
Note 2: All units are 100% production tested at TA= +85°C. Limits over the operating temperature range are guaranteed by design
and characterization and are not production tested.
Note 3: ΔRON = RON(MAX) - RON(MIN).
Note 4: Guaranteed by design. Not production tested.
Note 5: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the
specified analog signal range.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC
Turn-On Time tON V
NO_ or VNC_ = +1.0V, RL= 50, Figure 1 90 250 ns
Turn-Off Time tOFF V
NO_ or VNC_ = +1.0V, RL= 50, Figure 1 10 50 ns
Propagation Dela y tPD R
S= RL= 50, unbalanced, Figure 2 50 ps
Output Skew Between Pairs tSK1 RS= RL= 50, unbalanced; skew between
any two pairs, Figure 2 50 ps
Output Skew Between Same
Pair tSK2 RS= RL= 50, unbalanced; skew between two lines on same pair, Figure 2 10 ps
1MHz < f < 100MHz -0.5
On-Loss GLOS
RS= RL= 50,
unbalanced,
Figure 3 500MHz < f < 1.25GHz -1.4
dB
f = 50MHz -53
Crosstalk VCT1
Crosstalk between
any two pairs,
RS= RL= 50,
unbalanced,
Figure 3 f = 1.25GHz -32
dB
Signaling Data Rate BR RS= RL= 505.0 Gbps
f = 10MHz -56
Off-Isolation VISO
Signal = 0dBm,
RS= RL= 50,
Figure 3 f = 1.25GHz -26
dB
NO_/NC_ Off-Capacitance CNO_/NC_(OFF) Figure 4 1 pF
COM_ On-Capacitance CCOM_(ON) Figure 4 2 pF
LOG IC IN PU T
Input-Logic Low VIL 0.5 V
Input-Logic High VIH 1.4 V
Input-Logic Hysteresis VHYST 100 mV
Input Leakage Current IIN V
SEL = 0V or V+ -1 +1 μA
POWER SUPPLY
Power-Supply Range V+ 1.65 3.60 V
MAX4888A 60
V+ Supply Current I+ VSEL = 0V or V+ MAX4889A 120 μA
Input Leakage Current IIN V
SEL = 0V or V+ -1 +1 μA
ESD PROTECTION
COM_+, COM_- Human Body Model ±6 kV
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +3.0V to +3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at V+ = +3.3V, TA= +25°C.) (Note 2)

MAX4888A/MAX4889A
5.0Gbps PCI Express Passive Switches
4 _______________________________________________________________________________________
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
ON-RESISTANCE vs. VCOM_
VCOM_ (V)
RON (Ω)
MAX4888A/89A toc01
-0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
V+ = +3.3V
V+ = +2.5V
V+ = +1.8V
ON-RESISTANCE vs. VCOM_
(V+ = +1.8V)
VCOM_ (V)
RON (Ω)
MAX4888A/89A toc02
-0.1 0 0.1 0.2 0.3 0.4 0.5 0.6
0
2
4
6
8
10
12
14
TA= +85°C
TA= +25°C
TA= -40°C
ON-RESISTANCE vs. VCOM_
(V+ = +2.5V)
VCOM_ (V)
RON (Ω)
MAX4888A/89A toc03
-0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3
0
2
4
6
8
10
12
14
TA= +85°C
TA= +25°C
TA= -40°C
ON-RESISTANCE vs. VCOM_
(V+ = +3.3V)
VCOM_ (V)
RON (Ω)
MAX4888A/89A toc04
-0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1
0
2
4
6
8
10
12
14
TA= +85°C
TA= +25°C
TA= -40°C
SUPPLY CURRENT vs. TEMPERATURE
(MAX4889A)
TEMPERATURE (°C)
SUPPLY CURRENT (μA)
MAX4888A/89A toc05
-40 -15 10 35 60 85
0
10
20
30
40
50
60
70
80
V+ = +1.8V
V+ = +2.5V
V+ = +3.3V
LOGIC THRESHOLD vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
LOGIC THRESHOLD (V)
MAX4888A/89A toc06
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
VIH
VIL
TURN-ON/-OFF TIME vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
tON/tOFF (ns)
MAX4888A/89A toc07
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
0
20
40
60
80
100
120
140
160
180
200
220
240
NO_ tON
NO_ tOFF
NC_ tON
NC_ tOFF

MAX4888A/MAX4889A
5.0Gbps PCI Express Passive Switches
_______________________________________________________________________________________ 5
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
EYE DIAGRAM
(V+ = +3.3V, f = 1.25GHz,
600mVP-P PRBS SIGNAL, RS= RL = 50Ω)†
50ps/div
*PRBS = PSEUDORANDOM BIT SEQUENCE
†= GEN 1, 2.5Gbps; U1 = 400ps
VCOM_+
VCOM_-
50mV/div
MAX4888A/89A toc10
EYE DIAGRAM
(V+ = +1.8V, f = 2.5GHz,
600mVP-P PRBS SIGNAL, RS= RL= 50Ω)††
25ps/div
*PRBS = PSEUDORANDOM BIT SEQUENCE
†† = GEN 11, 5.0Gbps; U1 = 200ps
VCOM_+
VCOM_-
50mV/div
MAX4888A/89A toc11
EYE DIAGRAM
(V+ = +3.3V, f = 2.5GHz,
600mVP-P PRBS SIGNAL, RS= RL= 50Ω)††
25ps/div
*PRBS = PSEUDORANDOM BIT SEQUENCE
†† = GEN 11, 5.0Gbps; U1 = 200ps
VCOM_+
VCOM_-
50mV/div
MAX4888A/89A toc12
EYE DIAGRAM
(V+ = +2.5V, f = 2.5GHz,
600mVP-P PRBS SIGNAL, RS= RL= 50Ω)††
25ps/div
*PRBS = PSEUDORANDOM BIT SEQUENCE
†† = GEN 11, 5.0Gbps; U1 = 200ps
VCOM_+
VCOM_-
50mV/div
MAX4888A/89A toc12
EYE DIAGRAM
(V+ = +2.5V, f = 1.25GHz,
600mVP-P PRBS SIGNAL, RS= RL = 50Ω)†
50ps/div
*PRBS = PSEUDORANDOM BIT SEQUENCE
†= GEN 1, 2.5Gbps; U1 = 400ps
VCOM_+
VCOM_-
50mV/div
MAX4888A/89A toc09
EYE DIAGRAM
(V+ = +1.8V, f = 1.25GHz,
600mVP-P PRBS SIGNAL, RS= RL= 50Ω)†
50ps/div
*PRBS = PSEUDORANDOM BIT SEQUENCE
†= GEN 1, 2.5Gbps; U1 = 400ps
VCOM_+
VCOM_-
50mV/div
MAX4888A/89A toc08

MAX4888A/MAX4889A
5.0Gbps PCI Express Passive Switches
6 _______________________________________________________________________________________
Pin Description
PIN
MAX4888A MAX4889A
NAME FUNCTION
1, 10, 12, 14,
20, 25, 27
1, 4, 10, 14, 17,
19, 21, 39, 41 GND Ground
2 9 SEL Digital Control Input
3, 9 — N.C. No Connection. Not internally connected.
4 2 COM1+ Analog Switch 1. Common Positive Terminal.
5 3 COM1- Analog Switch 1. Common Negative Terminal.
6 6 COM2+ Analog Switch 2. Common Positive Terminal.
7 7 COM2- Analog Switch 2. Common Negative Terminal.
8, 11, 13, 19,
26, 28
5, 8, 13, 18,
20, 30,
40, 42
V+
Positive-Supply Voltage Input. Connect V+ to a +3.0V to +3.6V supply voltage.
Bypass V+ to GND with a 0.1μF capacitor placed as close to the device as
possible (See the Board Layout section).
15 31 NO2- Analog Switch 2. Normally Open Negative Terminal.
16 32 NO2+ Analog Switch 2. Normally Open Positive Terminal.
17 33 NO1- Analog Switch 1. Normally Open Negative Terminal.
18 34 NO1+ Analog Switch 1. Normally Open Positive Terminal.
21 35 NC2- Analog Switch 2. Normally Closed Negative Terminal.
22 36 NC2+ Analog Switch 2. Normally Closed Positive Terminal.
23 37 NC1- Analog Switch 1. Normally Closed Negative Terminal.
24 38 NC1+ Analog Switch 1. Normally Closed Positive Terminal.
— 11 COM3+ Analog Switch 3. Common Positive Terminal.
— 12 COM3- Analog Switch 3. Common Negative Terminal.
— 15 COM4+ Analog Switch 4. Common Positive Terminal.
— 16 COM4- Analog Switch 4. Common Negative Terminal.
— 22 NO4- Analog Switch 4. Normally Open Negative Terminal.
— 23 NO4+ Analog Switch 4. Normally Open Positive Terminal.
— 24 NO3- Analog Switch 3. Normally Open Negative Terminal.
— 25 NO3+ Analog Switch 3. Normally Open Positive Terminal.
— 26 NC4- Analog Switch 4. Normally Closed Negative Terminal.
— 27 NC4+ Analog Switch 4. Normally Closed Positive Terminal.
— 28 NC3- Analog Switch 3. Normally Closed Negative Terminal.
— 29 NC3+ Analog Switch 3. Normally Closed Positive Terminal.
— — EP Exposed Paddle. Connect EP to GND.

MAX4888A/MAX4889A
5.0Gbps PCI Express Passive Switches
_______________________________________________________________________________________ 7
tr< 5ns
tf< 5ns
50%
VIL
LOGIC
INPUT
VN_ = VNO_ OR VNC_
RL
COM_
GND
SEL
CLINCLUDES FIXTURE AND STRAY CAPACITANCE.
VOUT = VN_ (RL)
RL+ RON
VN_
VIH
tOFF
0V
NO_
OR NC_
0.9 x V0UT 0.9 x VOUT
tON
VOUT
SWITCH
OUTPUT
LOGIC
INPUT
V+
CL
+3.3V
VOUT
MAX4888A/MAX4889A
Figure 1. Switching Time
Test Circuits/Timing Diagrams

MAX4888A/MAX4889A
5.0Gbps PCI Express Passive Switches
8 _______________________________________________________________________________________
Test Circuits/Timing Diagrams (continued)
IN+
V+
+3.3V
IN-
OUT+
OUT-
VIN+
VIN-
VOUT+
VOUT-
NO_+ OR
NC_+
NO_- OR
NC_-
SEL
COM_+
COM_-
0V
+1.5V
0V
+1.5V
0V
+1.5V
0V
+1.5V
tPLHX tPHLX
tINRISE
tOUTRISE tOUTFALL
RISE-TIME PROPAGATION DELAY = tPLHX OR tPLHY
FALL-TIME PROPAGATION DELAY = tPHLX OR tPHLY
tSK1 = DIFFERENCE IN PROPAGATION DELAY (RISE-FALL)
50%
50%
50%
50%
90%
10% 10%
90%
10% 10%
RL
RL
50%
50%
50%
50%
tINFALL
90%
90%
tPHLY tPLHY
RS
RS
MAX4888A/MAX4889A
BETWEEN TWO LINES ON THE SAME PAIR
BETWEEN ANY TWO PAIRS
tSK2 = | tPLHX - tPHLY | OR | tPHLX - tPLHY |
Figure 2. Propagation Delay and Output Skew

MAX4888A/MAX4889A
5.0Gbps PCI Express Passive Switches
_______________________________________________________________________________________ 9
Detailed Description
The MAX4888A/MAX4889A high-speed passive switch-
es route PCIe data between two possible destinations.
The MAX4888A/MAX4889A are ideal for routing PCIe sig-
nals to change the system configuration. For example, in
a graphics application, the MAX4888A/MAX4889A create
two sets of eight lanes from a single 16-lane bus. The
MAX4888A/MAX4889A feature a single digital control
input (SEL) to switch signal paths.
The MAX4888A/MAX4889A are fully specified to oper-
ate from a single +3.0V to +3.6V power supply††.
Digital Control Input (SEL)
The MAX4888A/MAX4889A provide a single digital con-
trol input (SEL) to select the signal path between the
COM__ and NO__/NC__ channels. The truth tables for
the MAX4888A/MAX4889A are depicted in the
Functional Diagrams/Truth Table section. Drive SEL rail-
to-rail to minimize power consumption.
Analog Signal Levels
The MAX4888A/MAX4889A accept standard PCIe sig-
nals to a maximum of V+ - 1.2V. Signals on the COM_+
channels are routed to either the NO_+ or NC_+ chan-
nels, and signals on the COM_- channels are routed to
either the NO_- or NC_- channels. The MAX4888A/
MAX4889A are bidirectional switches, allowing COM__,
NO__, and NC__ to be used as either inputs or outputs.
CAPACITANCE
METER NC_ or
NO_
COM_
GND
SEL VIL OR VIH
0.1μF+3.3V
V+
MAX4888A/MAX4889A
Figure 4. Channel Off-/On-Capacitance
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
OFF-ISOLATION IS MEASURED BETWEEN COM_ AND "OFF" NO_ OR NC_ TERMINAL ON EACH SWITCH.
ON-LOSS IS MEASURED BETWEEN COM_ AND "ON" NO_ OR NC_ TERMINAL ON EACH SWITCH.
CROSSTALK IS MEASURED BETWEEN ANY TWO PAIRS.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
+3.3V
VOUT
V+
SEL
NC_
COM_
NO_
VIN
MAX4888A/MAX4889A
OFF-ISOLATION = 20log VOUT
VIN
ON-LOSS = 20log VOUT
VIN
CROSSTALK = 20log VOUT
VIN
NETWORK
ANALYZER
50Ω
50Ω50Ω
50Ω
MEAS REF
0.1μF
0V OR V+
50Ω
GND
Figure 3. On-Loss, Off-Isolation, and Crosstalk
Test Circuits/Timing Diagrams (continued)
††Contact factory if operating at +2.5V or +1.8V.

MAX4888A/MAX4889A
5.0Gbps PCI Express Passive Switches
10 ______________________________________________________________________________________
Functional Diagrams/Truth Table
MAX4888A
GND
SEL
0
1
ON
OFF
OFF
ON
COM__TO
NC__
COM__TO
NO__
V+
COM1+
COM1-
COM2+
COM2-
SEL
NC1+
NC1-
NO1+
NO1-
NC2+
NC2-
NO2+
NO2-
MAX4889A
GND
V+
COM1+
COM1-
COM4+
COM4-
SEL
NC1+
NC1-
NO1+
NO1-
COM2+
COM2-
NC2+
NC2-
NO2+
NO2-
COM3+
COM3-
NC3+
NC3-
NO3+
NO3-
NC4+
NC4-
NO4+
NO4-

MAX4888A/MAX4889A
5.0Gbps PCI Express Passive Switches
______________________________________________________________________________________ 11
Applications Information
PCIe Switching
The MAX4888A/MAX4889A primary applications are
aimed at reallocating PCIe lanes (see Figure 5). For
example, in graphics applications, several manufacturers
have found that it is possible to improve performance by
a factor of nearly two by splitting a single 16-lane PCIe
bus into two 8-lane buses. Two of the more prominent
examples are SLI™ (Scaled Link Interface) and
CrossFire™. The MAX4889A permits a computer
motherboard to operate properly with a single 16-lane
graphics card, and can later be updated to dual cards.
The same motherboard can be used with dual cards
where the user sets a jumper or a bit through software
to switch between single- or dual-card operation.
Common mode below 1V operation requirement.
Board Layout
High-speed switches require proper layout and design
procedures for optimum performance. Keep design-
controlled impedance PCB traces as short as possible
or follow impedance layouts per the PCIe specification.
Ensure that power-supply bypass capacitors are
placed as close to the device as possible. Multiple
bypass capacitors are recommended. Connect all
grounds and the exposed pad to large ground planes.
Common mode below 1V operation requirement.
ESD Protection
As with all Maxim devices, ESD-protection structures
are incorporated on all pins to protect against electro-
static discharges encountered during handling and
assembly. The COM_+ and COM_- lines have extra
protection against static electricity. Maxim’s engineers
have developed state-of-the-art structures to protect
these pins against ESD of ±6kV without damage. The
ESD structures withstand ±6kV of ESD in all states: nor-
mal operation, state output mode, and powered down.
Human Body Model
The MAX4889A COM_+ and COM_- pins are character-
ized for ±6kV ESD protection using the Human Body
Model (MIL-STD-883, Method 3015). Figure 6 shows
the Human Body Model and Figure 7 shows the current
waveform it generates when discharged into low
impedance. This model consists of a 100pF capacitor
charged to the ESD voltage of interest, which is then
discharged into the device through a resistor.
MAX4888A
MAX4889A
ONE LANE
DATA
DIRECTION
DATA IS ROUTED
TO EITHER
BOARD A OR B
NOTE: ONLY ONE LANE IS SHOWN FOR CLARITY
AB
Figure 5. The MAX4888A/MAX4889A Used as a Single-Lane
Switch
CrossFire is a trademark of ATI Technologies, Inc.
SLI is a trademark of NVIDIA Corporation.
Chip Information
PROCESS: CMOS
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
RC
1MΩ
RD
1500Ω
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 6. Human Body ESD Test Model
IP100%
90%
36.8%
tRL TIME
tDL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Ir
10%
0
0
AMPERES
Figure 7. Human Body Model Current Waveform

MAX4888A/MAX4889A
5.0Gbps PCI Express Passive Switches
12 ______________________________________________________________________________________
Typical Application Circuit
MAX4889A
COM1+
COM1-
COM2+
COM2-
COM3+
COM3-
COM4+
COM4-
CHANNEL SELECT
NC1+
SEL
NC1-
NC2+
NC2-
NC3+
NC3-
NC4+
NC4-
NO1+
NO1-
NO2+
NO2-
NO3+
NO3-
NO4+
NO4-
MAX4889A
COM1+
COM1-
COM2+
COM2-
COM3+
COM3-
COM4+
COM4-
CHANNEL SELECT
NC1+
SEL
NC1-
NC2+
NC2-
NC3+
NC3-
NC4+
NC4-
NO1+
NO1-
NO2+
NO2-
NO3+
NO3-
NO4+
NO4-
GRAPHICS
CARD 1
PCIe GRAPHICS INTERFACE
PCIe BUS
GRAPHICS
CARD 2
LANE 0 TX
LANE 1 TX
LANE 2 TX
LANE 3 TX
LANE 0 RX
LANE 1 RX
LANE 2 RX
LANE 3 RX

MAX4888A/MAX4889A
5.0Gbps PCI Express Passive Switches
______________________________________________________________________________________ 13
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
28 TQFN-EP T283555-1 21-0184
42 TQFN-EP T423590M-1 21-0181
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.

MAX4888A/MAX4889A
5.0Gbps PCI Express Passive Switches
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products. Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES CHANGED
0 4/07 Initial release —
2 5/09 Updated voltage range, style edits. 1, 2, 3, 5–9, 13, 14