Microchip Technology LX7720 User manual

© 2023 Microchip Technology Inc. LX7720 Daughter Board User Guide rev 3.1 - page 1
LX7720 Daughter Board User Guide
Description
The LX7720 daughter board contains a soldered in place LX7720-ES and peripherals to allow LX7720 functionality to be
quickly evaluated. Demonstration firmware is available for RTG4 FPGAs and SAM rad hard MCUs.
The LX7720 daughter board uses a high pin count (HPC) FMC connector for plug-in connection to an RTG4 FPGA DEV-
KIT (Figure 1 on page 1), an RT PolarFire FPGA RTPF-DEV-KIT, a PolarFire FPGA MPF300-EVAL-KIT, or a
SmartFusion2 SoC FPGA M2S150-ADV-DEV-KIT. A 40-way header provides the same signals for connection to other
FPGA boards such as a RT ProASIC3 FPGA ProASIC3 Starter Kit, that lack FMC connectivity. Linker boards are included
to route signals from the 40-way header to a SAMRH71F20 MCU Evaluation Kit (Figure 2 on page 2) and SAMRH71-
TFBGA-EK evaluation kit (Figure 3 on page 2) or a SAMRH707F18 MCU Evaluation Kit (Figure 4 on page 2).
Kit Contents
• LX7720 evaluation board SOL-12-000003-11 with soldered-in-place LX7720-ES engineering sample
• Engineering sample (-ES marking suffix) explanation sheet
• 24V 1.5A universal input AC adapter with 2.1mm x 5.5mm DC output connector, centre positive
• 20x 0.1" pitch shorting jumpers
• 2x 2-position 5mm pitch terminal block sockets type A, Adam Tech EB9A-02-C or equivalent to mate J30, and J31
• 2x 2-position 5mm pitch terminal block sockets type B, Molex 0395237002 or equivalent to mate J12 and J18
• 4-position 5mm pitch terminal block socket type B, Molex 0395237004 or equivalent, to mate J9
• 3-position 2.54mm pitch wire crimp housing Molex 50-57-9403 (latching) or 50-57-9003 (non-latching) to mate J13
• 6-position 2.54mm pitch wire crimp housing Molex 50-57-9406 (latching) or 50-57-9006 (non-latching) to mate J14
• 8-position 2.54mm pitch wire crimp housing Molex 50-57-9408 (latching) or 50-57-9008 (non-latching) to mate J15
• 20x Molex 16-02-0096 crimp sockets to suit 24 - 30AWG wire, for J13, J14, and J15 housings
• Linker board to connect to a SAMRH71F20-EK evaluation kit, plus a board with control switches and LEDs
• Linker board to connect to a SAMRH71-TFBGA-EK evaluation kit (which can also use the switch/LED board)
• Linker board to connect to a SAMRH707F18-EK evaluation kit, with LC filters for optional ∆Σ stream processing
• 4x 6mm, 4x 7mm, 4x 8mm, 5x 20mm, 1x 38mm nylon standoffs and 13x nuts for linker board height matching
• USB stick with documentation (see section 3 on page 3)
Ordering Information
Product Order Number
LX7720 Daughter Board LX7720-DB
Figure 1. LX7720 Daughter Board Connected to RTG4 DEV-KIT using the HPC FMC Connector

LX7720 Daughter Board User's Manual
FMC Connection to FPGA Evaluation Boards
© 2023 Microchip Technology Inc. LX7720 Daughter Board User Guide rev 3.1 - page 2
Figure 2. LX7720 Daughter Board Connected to SAMRH71F20-EK Evaluation Kit Using Included Linker Board
Figure 3. LX7720 Daughter Board Connected to SAMRH71-TFBGA-EK Evaluation Kit Using Included Linker Board
Figure 4. LX7720 Daughter Board Connected to SAMRH707F18-EK Evaluation Kit Using Included Linker Board

LX7720 Daughter Board User's Manual
FMC Connection to FPGA Evaluation Boards
© 2023 Microchip Technology Inc. LX7720 Daughter Board User Guide rev 3.1 - page 3
1 FMC Connection to FPGA Evaluation Boards
The LX7720-DB uses an HPC-FMC, J10, for signals to and from an external FPGA board, discussed in detail in Section 7
on page 17. Pinouts and FPGA resource allocations are provided for the following FPGA boards' HPC1-FMC connector:
• The RTG4 FPGA DEV-KIT (Table 17 on page 19)
• The PolarFire FPGA MPF300-EVAL-KIT (Table 17 on page 19)
• The RT PolarFire FPGA RTPF-DEV-KIT (Table 18 on page 20)
• The SmartFusion2 SoC FPGA M2S150-ADV-DEV-KIT (Table 19 on page 20)
2 Linker Adaptors to MCU Evaluation Boards
The 2x20 pin 0.1" pitch pin header, J20, provides the same signals as the HPC-FMC discussed above. Section 6 on page
16 details J20's pinout. The LX7720-DB includes linker adaptors for direct interconnection to MCU controller boards:
• The SAMRH71-EK linker (section 8 on page 22) routes J20 signaling to a SAMRH71F20-EK evaluation kit for the
SAMRH71F20 MCU. Table 21 on page 23 provides the pinout and MCU resource allocation. The kit comprises a
linker board connecting a SAMRH71F20-EK to the LX7720MLF-EVB, a small board with switches, and a ribbon cable:
 The linker board connects signals from the SAMRH71F20-EK's 0.1" headers J24 and J30 to J20
▫ All four LX7720 half-bridges are routed to the MCU PWM outputs, for BLDC and stepper compatibility
▫ 3 of the 4 motor phase current ∆Σ serial streams (SNS_OUT_A, B, and C) are routed to MCU TCLK inputs
▫ Two LX7720 bi-level (comparator) outputs are routed to MCU QDEC TIO inputs for quadrature encoder use
▫ The resolver/LVDT transformer primary differential drive (DMOD_IN_P, DMOD_IN_N) and associated ADC
Σ-Δ modulators ADC1, ADC2, and ADC3 are not routed to the MCU, but brought out to test point holes
 The switch board connects to GPIOs on SAMRH71F20-EK's 0.1" header J25 via a 20 way ribbon cable. The
SAMRH71F20 optionally uses GPIOs to monitor five push switches and operate two LEDs as status indicators
• The SAMRH71-TFBGA-EK linker (section 8 on page 22) routes J20 signaling to a SAMRH71-TFBGA-EK evaluation
kit for the SAMRH71F20 MCU. The same signals are routed as for the SAMRH71-EK linker discussed above:
 The linker board connects signals from the SAMRH71-TFBGA-EK's 0.1" headers J5 and J7 to J20
▫ All four LX7720 half-bridges are routed to the MCU PWM outputs, for BLDC and stepper compatibility
▫ 3 of the 4 motor phase current ∆Σ serial streams (SNS_OUT_A, B, and C) are routed to MCU TCLK inputs
▫ Two LX7720 bi-level (comparator) outputs are routed to MCU QDEC TIO inputs for quadrature encoder use
▫ The resolver/LVDT transformer primary differential drive (DMOD_IN_P, DMOD_IN_N) and associated ADC
Σ-Δ modulators ADC1, ADC2, and ADC3 are not routed to the MCU, but brought out to test point holes
 The switch board connects to GPIOs on SAMRH71-TFBGA-EK 0.1" header J9 via a 20 way ribbon cable.
• The SAMRH707-EK linker (section 9 on page 28) routes J20 signaling to a SAMRH707-EK evaluation kit for the
SAMRH707F18 MCU. Table 11 on page 30 provides the pinout and MCU resource allocation.
 The linker board connects signals from SAMRH707-EK 0.1" headers J18, J19, and J20 to J20
▫ All four LX7720 half-bridges are routable to the MCU PWM outputs, for BLDC and stepper compatibility
▫ The resolver/LVDT transformer primary differential drive (DMOD_IN_P, DMOD_IN_N) is routable to the 4th
pair of MCU PWM outputs instead of the 4th LX7720 half-bridge. This eases operation of either a 3-phase
BLDC plus resolver/LVDT, or a bipolar stepper motor without resolver/LVDT without external wiring
▫ 3 of the 4 motor phase current ∆Σ serial streams (SNS_OUT_A, B, and C) are routed to MCU TCLK inputs
▫ All 4 phase current ∆Σ serial streams (SNS_OUT_A x) and the 3 resolver/LVDT Σ-Δ serial streams (ADCx)
are processed on the linker board by RLC passive filters ((Figure 28 on page 28). This allows any of the
LX7720's ∆Σ serial streams to be acquired by MCU ADC channels instead of by DSP firmware
▫ Two LX7720 bi-level (comparator) outputs are routed to MCU QDEC TIO inputs for quadrature encoder use
3 Documentation and Support
The USB stick (contents also available here) included with the LX7720-DB includes the following:
• RTG4 targeted binaries and Libero source projects for the following motor control systems (see separate User Guide):
 BLDC motor, either sensorless or using a resolver
 Stepper motor
• GUI binaries and source for sensorless or resolver-feedback BLDCs (BLDC motor v4.1) and stepper motors (Stepper
motor v1.0) for the setup of LX7720-DB connected to an RTG4 DEV-KIT
• SAMRH71F20 targeted binary and MPLAB source project for a BLDC motor with encoder (see separate User Guide)
• Altium schematic and PCB files for the LX7720-DB and the linker boards
• FPGA IP user guides on the USB stick are from https://www.microchip.com/en-us/products/fpgas-and-plds/ip-core-
tools. The Microchip Libero library offers IP that can be downloaded under the Libero license
• For application support, use the Microchip Technical Support Portal

LX7720 Daughter Board User's Manual
Board Sockets and Link Configuration
© 2023 Microchip Technology Inc. LX7720 Daughter Board User Guide rev 3.1 - page 4
4 Board Sockets and Link Configuration
Figure 5 below identifies major circuit blocks, LEDs, and connectors.
Figure 6 on page 5 identifies link headers that configure signal and power supply options on the board, and set LX7720
pin configurations.
Table 1 on page 5 summarizes the functions of all connectors and link headers, and provides clickable links to the
appropriate parts of section 5 starting on page 8, which provides more detail and schematic around each one.
Default settings in Table 1 are highlighted in grey, and indicated in Figure 7 on page 7 for quick identification. These
defaults configure the board's power supplies to be generated internally from the 24V external DC supply plugged into J11
(VGS = 15V, VCC = 5V, VDD = 3.3V, VEE = internal), and selects control signals to be those provided at J10 (RTG4 FMC
connector) or J20 (40-way controller header).
Section 6 on page 16 provides pinouts for the controller interface connectors J10 and J20.
Figure 5. Location Diagram for Connectors, Circuit Blocks, and Power Rail Status LEDs
J9:
Motor Coil D
Motor Coil C
Motor Coil B
Motor Coil A
Motor Driver C
Motor Driver B
Motor Driver
A
J11 and SW1: 24V
DC Supply and Fuse
J12: VMPS Motor Supply input 20V to 60V J15: BL1 to BLI6 inputs J31: VGS External Supply 10V to 18V
J18: 3.3V input or output J14: ADC1 to ADC3 inputs
J13: DMOD_OUT
J10: RTG4 Interface
J20: Controller Interface
J30: 5V input or output
J26: MOD_CLK
(ext. 24-32MHz)
R3: VREF adjust
VGS Internal
Supply 15V
regulator
D13: VPMS_IN LED
D15: 5V LED
D12: 3V3_SMC LED
D16: 3.3V LED
D14: VGS LED
J27: CP_CLK
Y2: MOD_CLK
(
internal 27MHz
)
J4: VEE External Supply
range -VGS to -8V

LX7720 Daughter Board User's Manual
Board Sockets and Link Configuration
© 2023 Microchip Technology Inc. LX7720 Daughter Board User Guide rev 3.1 - page 5
Figure 6. Location Diagram for Configuration Links
Table 1. Configuration Link and Connector Settings Summary
Fitment Selection See Section Notes
Link 2 to 1 Use LX7720's internal 2.5V ±0.8% voltage reference
J1 Link 2 to 3 Use on-board adjustable voltage reference U2 5.6, page 11 Voltage
reference
Link 1 to 2 Connect signal ground SGND to motor ground MGND
J2 Open Signal ground SGND is isolated from motor ground MGND 5.7, page 11 SGND to
MGND link
Link 1 to 2 Fit when using external negative VEE supply via the J4 header
J3 Open Internal VEE supply is used. Do not attach an external supply to the J4 header 5.4, page 10 VEE select
Pin 1: VEE
Pin 2: GND
When using external VEE supply in the range -VGS to -8V, apply VEE to header
J4, and ensure that J3 is fitted with a link to select the external VEE supply option
External -VGS
to -8V VEE
J4
Open Internal VEE supply is used. J4 is available to monitor the VEE voltage
5.4, page 10 Internal VEE
Open, or
Link 1 to 2
Select longer DMOD_OUT_N pin 44 and DMOD_OUT_P pin 46 driver
propagation delay by setting LX7720 DMOD_BW pin 114 = low
J5
Pin 1 to VDD
Select shorter DMOD_OUT_N pin 44 and DMOD_OUT_P pin 46 driver
propagation delay by setting LX7720 DMOD_BW pin 114 = high. Nearby VDD
points include J38 pin 1 and J40 pin 1
5.14,
page 15
Resolver/LVDT
driver
propagation
delay
J1
J6
J36
J8
J35
J40 J39 J32
J16
J17
J5
J38
J19
J2
J3
J7

LX7720 Daughter Board User's Manual
Board Sockets and Link Configuration
© 2023 Microchip Technology Inc. LX7720 Daughter Board User Guide rev 3.1 - page 6
Fitment Selection See Section Notes
Link 1 to 2
Enables the LC filter comprising L1, C29, C30, and R6 between LX7720
DMOD_OUT_N pin 44 and DMOD_OUT_P pin 46 outputs. The filter shapes the
PWM output waveform to drive a resolver or LVDT primary
J6
Open The LX7720 DMOD_OUT_N pin 44 and DMOD_OUT_P pin 46 outputs remain
unfiltered PWM
5.14,
page 15
Resolver/LVDT
driver filter
Link 1 to 2
Couple the filtered resolver/LVDT driver outputs LX7720 DMOD_OUT_N pin 44
and DMOD_OUT_P pin 46 to LX7720 ADC3_N pin 36 and ADC3_P pin 37 for
measurement of the drive amplitude and fault detection
Resolver/LVDT
driver
measurement
J7,
J8
Open LX7720 ADC3_N pin 36 and ADC3_P pin 37 are available for other purposes
5.14,
page 15
ADC3 inputs
J10 HPC1-FMC
connector
HPC1-FMC connector to RTG4 Development Kit board. The same signals are
provided to this FMC connector and the 40-pin header J20, so connect to one or
the other but not both
6, page 16 RTG4 interface
J11 24V DC
Power Input
J12 Pin 1: VMPS
Pin 2: GND
J11 is the board's main 24V supply using the supplied AC adapter. 24V is also the
default VMPS supply by diode-OR from J11 to the alternative VMPS input at J12.
To use an external VMPS supply in the range 24V to 60V, apply the VPMS supply
to J12. For VMPS supplies in the range 20V to 24V, apply the voltage to both J11
and J12, with this voltage replacing the AC adapter's 24V at J11
24V supply
VPMS supply
J13 DMOD
outputs
Resolver/LVDT driver outputs LX7720 DMOD_OUT_N pin 44 and DMOD_OUT_P
pin 46 outputs. If J6 is linked to enable the on-board LC filter, then the filtered
drive outputs are available at J13 pins 2 and 3. If J6 is open, then the raw PWM
drive outputs are available at J13 pins 1 and 3
5.14,
page 15
Resolver/LVDT
driver outputs
J14 ADC Inputs The 3 differential inputs {ADC1_P, ADC1_N}, {ADC2_P, ADC2_N}, and {ADC3_P,
ADC3_N} feed the ADC1, ADC2, and ADC3 sigma delta modulators
5.14,
page 15 ADC1 to ADC3
J15 BLI Inputs BLI1 to BLI6 inputs, VCC, and GND. BLI_TH is set to VCC/2 by R4 and R5 5.13, page 14 BLI inputs
Link 1 to 2 Fit when not using J16 to measure VDD (nominally 3.3V) supply current Normal usage
Shunt resistor
or ammeter Replace link with current measuring device if desired for VDD from regulator U4 Measure V
current
J16
Open External VDD supply in the range 2.75V to 3.6V at connector J18
5.3, page 9
External 2.75V
to 3.6V VDD
Link 1 to 2 Fit when not using J17 to measure VCC (nominally 5V) supply current from
regulator U10 Normal usage
Shunt resistor
or ammeter Replace link with current measuring device if desired for VCC from regulator U10 Measure VCC current
J17
Open External VCC supply in the range 4.5V to 5.5V at connector J30
5.3, page 9
External 4.5V
to 5.5V VCC
J18 Pin 1: VDD
Pin 2: GND
When using external VDD supply in the range 2.75V to 3.6V, apply the VDD
supply to J18, and ensure that J16 is open so that regulator U4 is not back-driven 5.5, page 10 External 2.75V
to 3.6V VDD
Link 2 to 1
VDD supply is 3.3V from FMC connector J10 pins C39, D32, D36, D38, and D40.
J16 also needs to be linked. Do not apply an external VDD supply to either J18 or
J20 pin 30 with an RTG4 Development Kit board plugged into J10, because this
will back-drive the RTG4 Development Kit's 3.3V supply
VDD = 3.3V
from J10
Link 2 to 3 VDD supply is from 3.3V regulator U4. Configure J36 for desired U4 voltage
source also
VDD = internal
3.3V
J19
Open
VDD supply is 2.75V to 3.6V from either 40-pin header J20 pin 30 or from J18.
Ensure that J16 is also open so that regulator U4 or an RTG4 Development Kit
board plugged into J10 are not back-driven
5.5, page 10
2.75V to 3.6V
VDD from J20
pin 30 or J18
J20 Controller
connector
40 pin header to external MCU or FPGA controller. The same signals are
provided to this 40-pin header and the FMC connector J10, so connect to J10 or
to J20, but not to both
6, page 16 Controller
interface
J26 SMA socket External 24MHz to 32MHz MOD_CLK. R136 = 33Ω must be fitted 5.8, page 12 MOD_CLK
J27 SMA socket External 100kHz to 300kHz CP_CLK. R135 = 33Ω must be fitted 5.9, page 12 Charge pump
J30 Pin 1: VCC
Pin 2: GND
When using external VCC supply in the range 4.5V to 5.5V, apply the VCC supply
to J30, and ensure that J17 is open so that regulator U10 is not back-driven 5.3, page 9 External 4.5V
to 5.5V VCC
J31 Pin 1: VGS
Pin 2: GND
When using external VGS supply in the range 10V to 18V, apply the VGS supply
to J31, and ensure that link J32 is open so that regulator U3 is not back-driven
Table 2, page
8
External 10V to
18V VGS
Link 1 to 2 Fit when using internal 15V supply for VGS, and not using J32 to measure 15V
supply current Normal usage
Shunt resistor
or ammeter
Replace link with current measuring device if desired when using internal 15V
supply for VGS
Measure VGS
current
J32
Open External VGS supply in the range 10V to 18V at connector J31
Table 2, page
8
External 10V to
18V VGS

LX7720 Daughter Board User's Manual
Board Sockets and Link Configuration
© 2023 Microchip Technology Inc. LX7720 Daughter Board User Guide rev 3.1 - page 7
Fitment Selection See Section Notes
Link 2 to 1 VCC (5V) regulator U10 source is the VGS rail selected by J32 Normal usage
Link 2 to 3 VCC (5V) regulator U10 source is 12V from FMC connector J10 pins C35 & C37 RTG4 source
J35
Open
VCC (5V) regulator U10 source is unpowered. Provide an external 4.5V to 5.5V at
connector J30, and ensure that link J17 is open so that regulator U10 is not back-
driven
Table 2, page
8 External 4.5V
to 5.5V VCC
Link 2 to 1 VDD (3.3V) regulator U4 source is the VGS rail selected by J32 Normal usage
Link 2 to 3 VDD (3.3V) regulator U4 source is 12V from FMC connector J10 pins C35 and
C37 RTG4 source
J36
Open VDD (3.3V) regulator U4 source is unpowered. Provide an external 2.7V to 3.6V
at connector J18, and leave link J16 open so that regulator U4 is not back-driven
5.3, page 9
External 2.75V
to 3.6V VDD
Link 2 to 1 Enable Simultaneous Conduction Protection by setting LX7720 SCP pin 117 =
high SCP on
Link 2 to 3
LX7720 SCP pin 117 is controlled by an external signal on FMC connector J10
pin K23 or 40 pin header J20 pin 29. A pull-down resistor ensures that
Simultaneous Conduction Protection is disabled by default if the external signal is
open
Managed by
controller on
J10 or J20
J38
Open Disable Simultaneous Conduction Protection by setting LX7720 SCP pin 117 =
low
5.10, page 13
SCP off
Link 2 to 1 Disable Safe Mode by setting LX7720 SM_EN pin 17 = low Safe Mode off
Link 2 to 3
LX7720 SM_EN pin 17 is controlled by an external signal on FMC connector J10
pin H17 or 40 pin header J20 pin 27. A pull-up resistor ensures that Safe Mode is
enabled by default if the external signal is open
Managed by
controller on
J10 or J20
J39
Open Enable Safe Mode by setting LX7720 SM_EN pin 17 = high
5.12,
page 14
Safe Mode on
Link 2 to 1 Put LX7720 into reset condition by setting LX7720 RESET pin 18 = high. Reset
clears latched OC_FAULT, PR_FAULT, and/or over-temperature shutdown faults Reset on
Link 2 to 3
LX7720 RESET pin 18 is controlled by an external signal on FMC connector J10
pin G16 or 40 pin header J20 pin 31. A pull-down resistor ensures that LX7720
remains out of reset condition if the external signal is open
Managed by
controller on
J10 or J20
J40
Open Lock LX7720 out of reset condition by setting RESET pin 18 = low
5.11, page 13
Reset off
Figure 7. Default Shorting Jumper Positions, as highlighted in grey in Table 1

LX7720 Daughter Board User's Manual
LX7720 Daughter Board Configuration Options
© 2023 Microchip Technology Inc. LX7720 Daughter Board User Guide rev 3.1 - page 8
5 LX7720 Daughter Board Configuration Options
5.1 24V Evaluation Board and VMPS Supplies
J11 is the evaluation board's main 24V supply using the supplied AC adapter. 24V is also the default VMPS motor supply
by diode-OR from J11 to the alternative VMPS input at J12 (Figure 8). To use an external VMPS supply in the range 24V
to 60V, apply the desired VPMS supply to J12. For VMPS supplies in the range 20V to 24V, apply the voltage to both J11
and J12, with this voltage replacing the AC adapter's 24V at J11.
Figure 8. 24V Evaluation Board and VMPS Supplies
5.2 VGS Gate Driver Supply (15V) Regulator Settings
The header J32 selects either the on-board 15V regulator, or an external 10V to 18V power supply connected to J31
(Table 2, Figure 10). If LX7720's internal VEE charge pump is used (section 5.4 on page 10), VGS(min) = 12V not 10V.
Table 2. VGS Gate Driver Supply (15V) Link Settings
VGS Regulator Source J32 Link J31 Connector
VGS is 15V using on-board regulator U3 supplied by external 24V
AC adapter connected to DC power socket J11
Link 1 to 2 or insert ammeter
to measure VGS current Open
VGS is external 10V to 18V at connector J31 (using external VEE)
VGS is external 12V to 18V at connector J31 (using internal VEE) Open External 10V to 18V power supply
D11
STPS5L60S
BOOT
1
VIN
2
EN
3
SS/TR
4
RT/CLK
5PWRGD 6
VSENSE 7
COMP 8
GND 9
PH 10
EPAD
11
U3
TPS54160ADRCR
TP1
VIN_JCK
VGS_R
C57
2.2uF/100V/1210
C58
2.2uF/100V/1210
C59
2.2uF/100V/1210
C60
2.2uF/100V/1210
R44
332K/1%/0805
R46
56.2K/1%/0805
C61
0.01uF/100V/0805
R47
165K/1%/0805
R48
76.8K/1%/0805
C63
2700pF/50V/0805
C62
5.6pF/50V/0805
L2 33uH/2.7A
MSS1260-333MLB
C56
33uF/25V/1206
R45
178K/1%/0805
VGS
C52
0.1uF/25V/0805
C53
1uF/25V/0805
C54
4.7uF/25V/0805
C55
10uF/25V/0805
15V
R50
100K/0805
C70
33uF/25V/1206
D14
LTST-C190GKT
GREEN,10mA
1
2
J31
OSTOQ027150
12
J32
HDR_2_100MIL
VGS_R
C51 0.1uF/50V/0805
R49
10K/1%/0805
R56
1K/1%/0805
VGS
.
.
.
Figure 9. VGS Gate Driver Supply (15V) Regulator Schematic (Rev. D)

LX7720 Daughter Board User's Manual
LX7720 Daughter Board Configuration Options
© 2023 Microchip Technology Inc. LX7720 Daughter Board User Guide rev 3.1 - page 9
VGS
C52
0.1uF/25V/0805
C53
1uF/25V/0805
C54
4.7uF/25V/0805
C55
10uF/25V/0805
15V
D14
LTST-C190GK
T
GREEN,10m
A
1
2
J31
OSTOQ027150
12
J32
HDR_2_100MIL
R56
1K/1%/0805
VGS
VIN
5
VIN
6
VIN
15
VIN
16 SW 14
SW 13
SW 8
SW 7
EN
19
RT
20
SS/TRK
1
COMP
4
GND
9
GND
10
GND
11
AGND
12
EP
21
BOOT 17
FB 2
PGOOD 3
VCC 18
U3
LM20242MHX/NOPB
VIN_JCK
C57
2.2uF/100V/1210
C58
2.2uF/100V/1210
C59
2.2uF/100V/1210
C60
2.2uF/100V/1210
R44
322K/1%/0805
R46
56.2K/1%/0805
R47
243K/1%/0805
C61
0.01uF/100V/0805
R48
120K/1%/0805
C63
3300pF/50V/0805
C62
1uF/50V/0805
R50 100K/0805
VGS_R
R45
178K/1%/0805
R49 10K/1%/0805
C56
33uF/25V/1206
C70
33uF/25V/1206
L2 33uH/2.7A
MSS1260-333MLB
TP1
C51
0.1uF/50V/0805
.
.
Figure 10. VGS Gate Driver Supply (15V) Regulator Schematic (Rev. E)
5.3 VCC Signal Supply (5V) Regulator Settings
The headers J35 and J17 select either the on-board 5V regulator and its power source, or an external 4.5V to 5.5V power
supply connected to J30 (Table 3, Figure 11).
Table 3. VCC Signal Supply (5V) Regulator Link Settings
VCC Regulator Source J35 Link J17 Link J30 Connector
VCC is on-board 5V using regulator U10 supplied by VGS rail Link 2 to 1 Open
VCC is on-board 5V using regulator U10 supplied by 12V from FMC
connector J10 pins C35 and C36 (RTG4 board) Link 2 to 3
Link 1 to 2 or insert
ammeter to measure
VCC current Open
VCC is external 4.5V to 5.5V at connector J30
Regulator U10 is unpowered Open Open External 4.5V to
5.5V power supply
VIN
1
GND
3
OUT 2
ADJ 4 EN
5
TAB 6
U10
REG103GA-A
R51
37.4k/1%/0805
R53
13k/1%/0805
VCC
D15
LTST-C190GKT
GREEN,10mA
1
2
J30
OSTOQ0271
5
12
J17
HDR_2_100MIL
VCC_R
C65
0.1uF/25V/0805
C64
1uF/25V/0805
R52 0/0805 C66
0.1uF/25V/0805
C67
4.7uF/25V/0805
R57
300R/0805
C116
0.1uF/25V/0805
C117
4.7uF/25V/0805
VGS
VCC
11
22
3
J35
HDR_3_100MIL
1
2P0V_FMC
12V/15V_VIN_U10
.
.
Figure 11. 5V Regulator Schematic

LX7720 Daughter Board User's Manual
LX7720 Daughter Board Configuration Options
© 2023 Microchip Technology Inc. LX7720 Daughter Board User Guide rev 3.1 - page 10
5.4 VEE Negative Supply Settings
The header J3 selects either the LX7720's internal VEE charge pump, or an external -8V to -VGS power supply
connected to J4 (Table 4, Figure 12). If the internal VEE charge pump is used, VGS(min) = 12V (section 5.2 on page 8).
Table 4. VEE Negative Supply Link Settings
VEE Regulator Source J3 Link Fitment J4 Connector Usage
Use LX7720's internal VEE charge pump Open Open
Use external -8V to -VGS power supply Link 1 to 2 -8V to -VGS power supply
Figure 12. VEE Regulator Schematic
5.5 VDD Logic Supply (3.3V) Regulator Settings
The headers J36, J19, and J16 select either the on-board 3.3V regulator and its power source, or an external 2.7V to 3.6V
power supply connected to J18 (Table 5, Figure 13).
While the LX7720 allows a logic supply range of 2.1V to 5.5V, the LX7720 daughter board's allowed range is 2.7V to
3.6V. This limitation is due to the supply range of the 27MHz oscillator module Y2, and the SN74LVTH16245A bus
transceivers that interface both the 2x20 pin controller interface header J20 and the RTG4 interface FMC connector J10.
Table 5. VDD Logic Supply (3.3V) Regulator Link Settings
VDD Regulator Source J36 Link J19 Link J16 Link J18 Connector
VDD is on-board 3.3V using regulator U4 supplied by VGS rail Link 2 to 1 Open
VDD is on-board 3.3V using regulator U4 supplied by 12V from
FMC connector J10 pins C35 and C36 (RTG4 board) Link 2 to 3 Link 2 to 3 Open
VDD is external 3.3V from FMC connector J10 pins C39, D32,
D36, D38, and D40 (RTG4 board) Regulator U4 is unpowered Open Link 2 to 1
Link 1 to 2 or
insert ammeter
to measure
VDD current Open
VDD is external 2.7V to 3.6V at connector J18
Regulator U4 is unpowered Open Open Open External 2.7V to
3.6V power supply

LX7720 Daughter Board User's Manual
LX7720 Daughter Board Configuration Options
© 2023 Microchip Technology Inc. LX7720 Daughter Board User Guide rev 3.1 - page 11
C104
1uF/25V/0805
C105
0.1uF/25V/0805
R102 0/0805
1
2
J18
OSTOQ027150
VDD_R
VDD_3P3V
VDD_3P3V_FMC
12
J16
HDR_2_100MIL
R105
150R/0805
D16
LTST-C190GKT
GREEN,10mA
C106
0.1uF/25V/0805
C107
4.7uF/10V/0805
11
22
3
J19
HDR_3_100MIL
C118
0.1uF/25V/0805
C119
4.7uF/10V/0805
VIN
1
GND
3
OUT 2
ADJ 4 EN
5
TAB 6
U4
REG103GA-A
R103
13k/1%/0805
R101
20k/1%/0805
VDD_3P3V
VDD_3P3V_FMC
VGS
11
22
3
J36
HDR_3_100MIL
12P0V_FMC
12V/15V_VIN_U4
.
.
Figure 13. VDD Logic Supply (3.3V) Regulator Schematic
5.6 Reference Voltage Selection
The 3-pin header J1 selects either the LX7720's internal 2.5V ±0.8% reference or an external reference U2, adjustable by
potentiometer R3 (Table 6, Figure 14). The adjustment range is 2.3V to 2.7V.
Table 6. LX7720 Reference Voltage Selection Link Settings
Voltage Reference Source J1 Link
Use the LX7720's internal 2.5V ±0.8% voltage reference Link 2 to 1
Use external adjustable reference U2. Use R3 to adjust the voltage within the range 2.3V to 2.7V Link 2 to 3
Figure 14. Reference Voltage Selection Schematic
5.7 Motor Ground MGND to Signal Ground SGND Connection
The 2-pin header J2 joins MGND to SGND on the PCB. If the link is open, ensure that there is a reliable DC path in the
system under evaluation between MGND to SGND. The absolute maximum potential difference allowed between MGND
and SGND is ±10V.
Table 7. LX7720 MGND to SGND Link Settings
Voltage Reference Source J2 Link
Signal ground SGND is isolated from motor ground MGND Open
Signal ground SGND is connected to the motor ground MGND on the PCB Link 1 to 2

LX7720 Daughter Board User's Manual
LX7720 Daughter Board Configuration Options
© 2023 Microchip Technology Inc. LX7720 Daughter Board User Guide rev 3.1 - page 12
5.8 MOD_CLK Input Selection
There are 4 possible sources for the 24MHz to 32MHz modulator clock, MOD_CLK_D at LX7720 pin 31. The 2x20 pin
controller interface header J20 and RTG4 Interface FMC connector J10 are wired in parallel to deliver an external
modulator clock MOD_CLK_C, which is buffered by a gate in U11 (SN74LVTH16245A) to become MOD_CLK. As shown
in Figure 15 below, MOD_CLK, a 27MHz oscillator module Y2, and an external clock at SMA connector J26 are summed
through resistors to become the final MOD_CLK_D delivered to the LX7720.
Factory build has both R73 and R136 not fitted, so the default clock source is from headers J20 and J10 (Table 8).
The modulator clock should be in the frequency range 24MHz to 32MHz, with a logic swing of 0V to VDD (default 3.3V).
Table 8. LX7720 MOD_CLK Input Selection
MOD_CLK Input Source R73 R136 R143
External 24MHz to 32MHz square wave clock on either J20 pin 18 or J10
pin H8 (drive one pin, leave the other pin Hi-Z). Ideal logic swing is 0V to
VDD, but the SN74LVTH16245A buffer is over-voltage tolerant to 5.5V
Not fitted (default) Not fitted (default) 33Ω (default)
External 24MHz to 32MHz square wave clock on SMA connector J26
delivering a logic swing of 0V to VDD into 50Ω Not fitted (default) 33Ω Not fitted
Internal 27MHz square wave clock from oscillator module Y2 0Ω Not fitted (default) Not fitted
TRISTA
1
E-PAD
7GND
3OUTPUT 4
VDD 6
NC1
2NC2 5
Y2
ASVMPC-27.000MHZ-LR-T
R73 0R/0805/DNL MOD_CLK_D
R140
49.9/1%/0805
1
2 3 4 5
J2
6
MOD_CLK R143 33R
R136 33R / DNL
VDD_3P3
V
C90
0.1uF/25V/0805
.
.
Figure 15. MOD_CLK Internal 27MHz Oscillator and External SMA Input Schematic
5.9 Charge Pump CP_CLK Selection
There are 4 possible sources for the 100kHz to 300kHz charge pump clock, CP_CLK_D at LX7720 pin 13. The 2x20 pin
controller interface header J20 and RTG4 Interface FMC connector J10 are wired in parallel to deliver an external clock
CP_CLK_C, which is buffered by a gate in U12 (SN74LVTH16245A) to become CP_CLK. As shown in Figure 16 below,
CP_CLK and an external clock at SMA connector J27 are summed through resistors to become the final CP_CLK_D
delivered to the LX7720.
Factory build has R135 not fitted, so the default clock source is from headers J20 and J10 (Table 9).
The charge pump clock should be in the frequency range 100kHz to 300kHz, with a logic swing of 0V to VDD (default
3.3V).
Table 9. LX7720 CP_CLK Input Selection
CP_CLK Input Source R135 R142
External 100kHz to 300kHz square wave clock on either J20 pin 17 or J10
pin G21 (drive one pin, leave the other pin Hi-Z). Ideal logic swing is 0V to
VDD, but the SN74LVTH16245A buffer is over-voltage tolerant to 5.5V
Not fitted (default) 33Ω (default)
External 100kHz to 300kHz square wave clock on SMA connector J27
delivering a logic swing of 0V to VDD into 50Ω 33Ω Not fitted

LX7720 Daughter Board User's Manual
LX7720 Daughter Board Configuration Options
© 2023 Microchip Technology Inc. LX7720 Daughter Board User Guide rev 3.1 - page 13
Figure 16. CP_CLK Selection and External SMA Input Schematic
5.10 Simultaneous Conduction Protection (LX7720 SCP pin 117)
Simultaneous conduction protection prevents the upper and lower driver for each half-bridge being on simultaneously.
When disabled, the upper and lower drivers are operated independently with no overlap prevention.
Table 10. Simultaneous Conduction Protection Link Settings
Simultaneous Conduction Protection J38 Link
Simultaneous Conduction Protection is enabled (LX7720 SCP pin 117 = high) Link 2 to 1
Simultaneous Conduction Protection is controlled by an external signal on FMC connector J10 pin K23
(RTG4 board) or 40 pin header J20 pin 29 (other controller).
A pull-down resistor ensures that Simultaneous Conduction Protection is disabled by default if the external
signal is open
Link 2 to 3
Simultaneous Conduction Protection is disabled (LX7720 SCP pin 117 = low) Open
Figure 17. Simultaneous Conduction Protection Schematic
5.11 Reset (LX7720 RESET pin 18)
The LX7720's active-high reset input clears latched OC_FAULT, PR_FAULT, and/or over-temperature shutdown faults.
Table 11. Reset Link Settings
Reset J40 Link
Put LX7720 into reset condition by setting LX7720 RESET pin 18 = low.
Reset clears latched OC_FAULT, PR_FAULT, and/or over-temperature shutdown faults Link 2 to 1
LX7720 RESET pin 18 is controlled by an external signal on FMC connector J10 pin G16 (RTG4 board) or
40 pin header J20 pin 31 (other controller).
A pull-down resistor ensures that LX7720 remains out of reset condition if the external signal is open
Link 2 to 3
Lock LX7720 out of reset condition by setting RESET pin 18 = low Open

LX7720 Daughter Board User's Manual
LX7720 Daughter Board Configuration Options
© 2023 Microchip Technology Inc. LX7720 Daughter Board User Guide rev 3.1 - page 14
Figure 18. Reset Schematic
5.12 Safe Mode (LX7720 SM_EN pin 17)
The LX7720's active-high Safe Mode input enables protection countermeasures when faults are detected.
Table 12. Safe Mode Link Settings
Safe Mode J39 Link
Disable Safe Mode by setting LX7720 SM_EN pin 17 = low Link 2 to 1
LX7720 SM_EN pin 17 is controlled by an external signal on FMC connector J10 pin H17 or 40 pin header
J20 pin 27.
A pull-up resistor ensures that Safe Mode is enabled by default if the external signal is open
Link 2 to 3
Enable Safe Mode by setting LX7720 SM_EN pin 17 = high Open
Figure 19. Safe Mode Schematic
5.13 Bi-Level Comparator Inputs BL1 to BL6
The LX7720's 6 bi-level comparator inputs BLI1 to BLI6 are routed to connector J15 pins 3 to 8 respectively. The common
comparator threshold LX7720 BLI_TH pin 119 is set to VCC/2 by R4 & R5.
The LX7720's 6 bi-level comparator outputs BLO1 to BLO6 are routed to the FMC connector (Table 16 on page 18) and
to the 40-way header J20 (Table 14 on page 16).
Figure 20. Bi-Level Comparator Inputs BL1 to BL6 Schematic

LX7720 Daughter Board User's Manual
LX7720 Daughter Board Configuration Options
© 2023 Microchip Technology Inc. LX7720 Daughter Board User Guide rev 3.1 - page 15
5.14 Resolver/LVDT Interface
Links J5 to J8 configure the resolver/LVDT driver outputs with or without LC filtering for primary drive wave shaping.
Link J5 is left open by default to set LX7720 DMOD_BW pin 114 = low, selecting the longer DMOD_OUT_N pin 44 and
DMOD_OUT_P pin 46 driver propagation delay. To select the shorter driver propagation delay, set LX7720 DMOD_BW
pin 114 = high by connecting J5 pin 1 to VDD. Nearby VDD points include J38 pin 1 and J40 pin 1.
Standard connections for the AMCI R11X-A10/7 resolver used to develop the RTG4 programming are:
• Links J5 to J8: all open
• Primary: J13 pin 1: black/white, J13 pin 2: n/c, J13 pin 3: red/white
• Secondary 1: J14 pin 3: red, J14 pin 4: black
• Secondary 2: J14 pin 5: blue, J14 pin 6: yellow
Table 13. Resolver/LVDT Link Settings
Resolver/LVDT Options J6 Link J7 Link J8 Link J14 Connector J13 Connector
Resolver/LVDT driver outputs DMOD_OUT_P and
DMOD_OUT_N routed directly to J13 without filtering Open DMOD_OUT_P: pin 1 DMOD_OUT_N: pin 3
Resolver/LVDT driver outputs DMOD_OUT_P and
DMOD_OUT_N routed to J13 with LC filtering. The filter
shapes the PWM output waveform
Link 1 to 2
Open Open
ADC1, ADC2,
and ADC3
available for
general use
Resolver/LVDT driver outputs DMOD_OUT_P and
DMOD_OUT_N routed to J13 with LC filtering. The filter
shapes the PWM output waveform. ADC_3 is used to
monitor the filtered drive output for closed loop control of
the drive amplitude and for fault detection
Link 1 to 2 Link 1 to 2 Link 1 to 2
Only ADC1 and
ADC2 available
for general use
DMOD_OUT_P: pin 2
DMOD_OUT_N: pin 3
Figure 21. Resolver/LVDT Driver and ADC1, ADC2, ADC3 Inputs and Sigma-Delta Modulator Outputs

LX7720 Daughter Board User's Manual
Control and Acquisition Signals Header J20
© 2023 Microchip Technology Inc. LX7720 Daughter Board User Guide rev 3.1 - page 16
5.15 Motor Connections
Standard connections for the Trinamic QBL4208-41-04-006 24V, 8 phase, 3 pole BLDC motor used to develop the RTG4
programming are J9 pin 1: yellow (coil A), pin 2: red (coil B), pin 3: black (coil C).
Figure 22. Motor Winding Connections Schematic
5.16 Motor Current Sense Resistors
The board is fitted on the underside with 0.25Ω, 1%, 2512 size current sense resistors in each of the four half-bridge
outputs. These are R109, R115, R131, and R132 for outputs A, B, C, and D respectively. The 0.25Ω current sense
resistors provide ±1.4A full scale and ±1A linear ranges for the current sense Σ-Δ modulators, corresponding to a ±350mV
and a ±250mV sense voltage respectively. To raise the current range, fit additional resistors in the 4 empty 2512 positions
R34, R35, R40, and R41 which are in parallel with R109, R115, R131, and R132. For example, fitting 0.22Ω resistors in
parallel will raise the linear sense range to ±2.14A as the effective current sense resistance drops from 0.25Ω to 0.117Ω.
6 Control and Acquisition Signals Header J20
J20 is a 2x20 pin 0.1" pitch pin header which provides access to LX7720 signals (Table 14 on page 16) to an external
control system without FMC support.
Note:
• Buffered 3.3V high speed signals are highlighted in blue in the signal tables
 Buffered signals are passed through one of the two on-board SN74LVTH16245A bus buffers U11 and U12
 Buffer output voltage swing is GND to VDD. VDD is normally 3.3V supplied by on-board regulator U4
 See section 5.5 on page 10 for details on selecting an alternative VDD supply voltage in the range 2.75V to 3.6V
• Unbuffered 3.3V low speed signals directly from LX7720 pins are highlighted in red
• Unbuffered 3.3V control signals to LX7720 pins passing through a link header are highlighted in green
 See Table 1 on page 5 for link header configuration details
 External SM_EN and SCP signals from J20 override the EVB's switch settings
 Pressing the on-board reset switch always reset the LX7720 (RESET = hi), overriding the J20 signal
• Control inputs have 100kΩ pulldown resistors, defaulting half-bridge outputs to off
Table 14. LX7720 Control and Acquisition Signals Header J20 Pinout
Pin Signal Name Signal Function Pin Signal Name Signal Function
1 UD_IN_A_C Buffered UD_IN_A FET drive input 2 LD_IN_A_C Buffered LD_IN_A FET drive input
3 SNS_OUT_A_C Buffered SNS_OUT_A bit stream output 4 GND Ground
5 UD_IN_B_C Buffered UD_IN_B FET drive input 6 LD_IN_B_C Buffered LD_IN_B FET drive input
7 SNS_OUT_B_C Buffered SNS_OUT_B bit stream output 8 GND Ground
9 UD_IN_C_C Buffered UD_IN_C FET drive input 10 LD_IN_C_C Buffered LD_IN_C FET drive input
11 SNS_OUT_C_C Buffered SNS_OUT_C bit stream output 12 GND Ground
13 UD_IN_D_C Buffered UD_IN_D FET drive input 14 LD_IN_D_C Buffered LD_IN_DFET drive input
15 SNS_OUT_D_C Buffered SNS_OUT_D bit stream output 16 GND Ground
17 CP_CLK_C Buffered CP_PLK charge pump clock input 18 MOD_CLK_C Buffered MOD_CLK mod clock input
19 CLK_OUT_C Buffered CLK_OUT mod clock output 20 GND Ground
21 DMOD_IN_P_C Buffered DMOD_IN_P drive input 22 DMOD_IN_N_C Buffered DMOD_IN_N drive input
23 ADC1_C Buffered ADC1 bit stream output 24 GND Ground
25 ADC2_C Buffered ADC2 bit stream output 26 ADC3_C Buffered ADC3 bit stream output
27 SM_EN SM_EN input via J39 link header 28 GND Ground
29 SCP SCP input via J38 link header 30 VDD_3P3V VDD supply, normally 3.3V
31 RESET RESET input via J40 link header 32 OC_FAULT OC_FAULT output
33 PR_FAULT PR_FAULT output 34 OTW_FAULT OTW_FAULT output
35 BLO1 Bi-Level Detector output 1 36 BLO2 Bi-Level Detector output 2
37 BLO3 Bi-Level Detector output 3 38 BLO4 Bi-Level Detector output 4
39 BLO5 Bi-Level Detector output 5 40 BLO6 Bi-Level Detector output 6

LX7720 Daughter Board User's Manual
FMC-HPC Connector J10
© 2023 Microchip Technology Inc. LX7720 Daughter Board User Guide rev 3.1 - page 17
7 FMC-HPC Connector J10
The HPC-FMC pinout is provided in Table 15 on page 17 and Table 16 on page 18. See the note in section 6 on the
previous page explaining the color code used to highlight table entries.
7.1 Height Matching the LX7720MLF-EVB and Target FPGA Boards
The LX7720-DB needs to be 10mm higher in height than the target FPGA board for the heights to match with the FMC
connectors mated (presuming a standard 1.6mm FPGA board PCB thickness). The LX7720-DB is fitted as standard with
four 25mm standoffs for feet. This matches the RTG4 DEV_KIT's standard 15mm standoffs when plugged together. For
other boards, the included 7mm and 8mm standoffs can be joined to make 15mm standoffs to replace to the target FPGA
board existing standoffs.
7.2 FPGA Resource Mapping
Pinouts and FPGA resource allocations are provided for the following FPGA boards' HPC1-FMC connector:
• The RTG4 FPGA DEV-KIT (Table 17 on page 19)
• The PolarFire FPGA MPF300-EVAL-KIT (Table 17 on page 19)
• The RT PolarFire FPGA RTPF-DEV-KIT (Table 18 on page 20)
• The SmartFusion2 SoC FPGA M2S150-ADV-DEV-KIT (Table 19 on page 20)
Table 15. LX7720 Control and Acquisition Signals HPC-FMC Connector J10 Pinout (A to E)
Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal
A1 GND B1 - C1 GND D1 - E1 GND
A2 - B2 GND C2 - D2 GND E2 -
A3 - B3 GND C3 - D3 GND E3 -
A4 GND B4 - C4 GND D4 - E4 GND
A5 GND B5 - C5 GND D5 - E5 GND
A6 - B6 GND C6 - D6 GND E6 -
A7 - B7 GND C7 - D7 GND E7 -
A8 GND B8 - C8 GND D8 - E8 GND
A9 GND B9 - C9 GND D9 - E9 -
A10 - B10 GND C10 - D10 GND E10 UD_IN_B_C
A11 - B11 GND C11 ADC1_C D11 - E11 GND
A12 GND B12 - C12 GND D12 - E12 -
A13 GND B13 - C13 GND D13 GND E13 -
A14 - B14 GND C14 - D14 - E14 GND
A15 - B15 GND C15 - D15 - E15 -
A16 GND B16 - C16 GND D16 GND E16 -
A17 GND B17 - C17 GND D17 - E17 GND
A18 - B18 GND C18 - D18 - E18 -
A19 - B19 GND C19 - D19 GND E19 -
A20 GND B20 - C20 GND D20 - E20 GND
A21 GND B21 - C21 GND D21 - E21 -
A22 - B22 GND C22 - D22 GND E22 -
A23 - B23 GND C23 - D23 - E23 GND
A24 GND B24 - C24 GND D24 - E24 -
A25 GND B25 - C25 GND D25 GND E25 -
A26 - B26 GND C26 - D26 - E26 GND
A27 - B27 GND C27 UD_IN_A_C D27 LD_IN_C_C E27 -
A28 GND B28 - C28 GND D28 GND E28 -
A29 GND B29 - C29 GND D29 - E29 GND
A30 - B30 GND C30 - D30 - E30 -
A31 - B31 GND C31 - D31 - E31 -
A32 GND B32 - C32 GND D32 VDD_3P3V_FMC E32 GND
A33 GND B33 - C33 GND D33 - E33 -
A34 - B34 GND C34 - D34 - E34 -
A35 - B35 GND C35 12P0V_FMC D35 - E35 GND
A36 GND B36 - C36 GND D36 VDD_3P3V_FMC E36 -
A37 GND B37 - C37 12P0V_FMC D37 GND E37 -
A38 - B38 GND C38 GND D38 VDD_3P3V_FMC E38 GND
A39 - B39 GND C39 VDD_3P3V_FMC D39 GND E39 VADJ
A40 GND B40 - C40 GND D40 VDD_3P3V_FMC E40 GND

LX7720 Daughter Board User's Manual
FMC-HPC Connector J10
© 2023 Microchip Technology Inc. LX7720 Daughter Board User Guide rev 3.1 - page 18
Table 16. LX7720 Control and Acquisition Signals HPC-FMC Connector J10 Pinout (F to K)
Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal
F1 - G1 GND H1 - J1 GND K1 -
F2 GND G2 - H2 - J2 - K2 GND
F3 GND G3 - H3 GND J3 - K3 GND
F4 - G4 GND H4 - J4 GND K4 -
F5 - G5 GND H5 - J5 GND K5 -
F6 GND G6 - H6 GND J6 - K6 GND
F7 UD_IN_C_C G7 - H7 CLK_OUT_C J7 - K7 -
F8 LD_IN_B_C G8 GND H8 MOD_CLK_C J8 GND K8 -
F9 GND G9 ADC3_C H9 GND J9 - K9 GND
F10 - G10 - H10 ADC2_C J10 - K10 -
F11 LD_IN_A_C G11 GND H11 - J11 GND K11 -
F12 GND G12 - H12 GND J12 - K12 GND
F13 SNS_OUT_A_C G13 - H13 SNS_OUT_D_C J13 - K13 -
F14 SNS_OUT_B_C G14 GND H14 SNS_OUT_C_C J14 GND K14 -
F15 GND G15 - H15 GND J15 - K15 GND
F16 - G16 RESET H16 - J16 - K16 -
F17 - G17 GND H17 SM_EN J17 GND K17 -
F18 GND G18 OTW_FAULT H18 GND J18 - K18 GND
F19 BLO4 G19 - H19 OC_FAULT J19 - K19 -
F20 - G20 GND H20 PR_FAULT J20 GND K20 -
F21 GND G21 CP_CLK_C H21 GND J21 - K21 GND
F22 - G22 - H22 - J22 - K22 -
F23 - G23 GND H23 DMOD_IN_N_C J23 GND K23 SCP
F24 GND G24 DMOD_IN_P_C H24 GND J24 - K24 GND
F25 - G25 UD_IN_D_C H25 LD_IN_D_C J25 - K25 -
F26 - G26 GND H26 - J26 GND K26 -
F27 GND G27 - H27 GND J27 - K27 GND
F28 - G28 BLO6 H28 - J28 - K28 -
F29 - G29 GND H29 - J29 GND K29 -
F30 GND G30 BLO5 H30 GND J30 - K30 GND
F31 - G31 BLO3 H31 - J31 - K31 -
F32 - G32 GND H32 - J32 GND K32 -
F33 GND G33 - H33 GND J33 - K33 GND
F34 - G34 - H34 BLO2 J34 - K34 -
F35 - G35 GND H35 BLO1 J35 GND K35 -
F36 GND G36 - H36 GND J36 - K36 GND
F37 - G37 - H37 - J37 - K37 -
F38 - G38 GND H38 - J38 GND K38 -
F39 GND G39 VADJ H39 GND J39 VIO_B_M2C K39 GND
F40 VADJ G40 GND H40 VADJ J40 GND K40 VIO_B_M2C

LX7720 Daughter Board User's Manual
FMC-HPC Connector J10
© 2023 Microchip Technology Inc. LX7720 Daughter Board User Guide rev 3.1 - page 19
Table 17. Mapping of HPC1-FMC pins, LX7720 pins, and RTG4 and PolarFire FPGA pins
FMC
Pin
LX7720 Signal
Name LX7720 Signal Type and Function RTG4 Pin Number
RTG4 Pin
Name
PolarFire
Pin Number
PolarFire Pin
Name
C11 ADC1_C Buffered ADC2 bit stream output J11 MSIO248NB6 G16 GPIO5NB2
C27 UD_IN_A_C Buffered UD_IN_A FET drive input A8 MSIO261NB6 D6 GPIO13NB2
D27 LD_IN_C_C Buffered LD_IN_C FET drive input B8 MSIO252NB6 G11 GPIO18NB2
E10 UD_IN_B_C Buffered UD_IN_B FET drive input F18 MSIO287NB5 T4 GPIO217NB4
F7 UD_IN_C_C Buffered UD_IN_C FET drive input J19 MSIO296PB5 AB9 GPIO183PB4
F8 LD_IN_B_C Buffered LD_IN_B FET drive input H19 MSIO296NB5 AA8 GPIO183NB4
F11 LD_IN_A_C Buffered LD_IN_A FET drive input F20 MSIO299NB5 AB6 GPIO179NB4
F13 SNS_OUT_A_C Buffered SNS_OUT_A bit stream output D19 MSIO294PB5 T7 GPIO218PB4
F14 SNS_OUT_B_C Buffered SNS_OUT_B bit stream output C19 MSIO294NB5 U7 GPIO218NB4
F19 BLO4 Bi-Level Detector output 4 C13 MSIO277PB5 AB4 GPIO177PB4
G9 ADC3_C Buffered ADC3 bit stream output K10 MSIO242PB6 H16 GPIO32PB2
G16 RESET RESET input via J40 link header G15 MSIO269NB6 E12 GPIO23NB2
G18 OTW_FAULT OTW_FAULT output D11 MSIO268PB6 D10 GPIO26PB2
G21 CP_CLK_C Buffered 150kHz ±50kHz CP_CLK charge
pump clock input B10 MSIO270PB6 B9 GPIO25PB2
G24 DMOD_IN_P_C Buffered DMOD_IN_P drive input B5 MSIO255PB6 D8 GPIO14PB2
G25 UD_IN_D_C Buffered UD_IN_D FET drive input B6 MSIO255NB6 C8 GPIO14NB2
G28 BLO6 Bi-Level Detector output 6 C6 MSIO246NB6 H11 GPIO4NB2
G30 BLO5 Bi-Level Detector output 5 C3 MSIO243PB6 B10 GPIO28PB2
G31 BLO3 Bi-Level Detector output 3 B3 MSIO243NB6 A10 GPIO28NB2
H7 CLK_OUT_C Buffered CLK_OUT Σ-Δ mod clock output H8 MSIO245PB6 L19 GPIO34PB2
H8 MOD_CLK_C Buffered 24MHz to 32MHz MOD_CLK Σ-Δ
modulator clock input H9 MSIO245NB6 L18 GPIO34NB2
H10 ADC2_C Buffered ADC2 bit stream output F9 MSIO258PB6 J18 GPIO33PB2
H13 SNS_OUT_D_C Buffered SNS_OUT_D bit stream output G10 MSIO257PB6 K15 GPIO0PB2
H14 SNS_OUT_C_C Buffered SNS_OUT_C bit stream output G11 MSIO257NB6 J15 GPIO0NB2
H17 SM_EN SM_EN input via J39 link header D14 MSIO273NB6 K17 GPIO35NB2
H19 OC_FAULT OC_FAULT output E9 MSIO259PB6 A7 GPIO16PB2
H20 PR_FAULT PR_FAULT output D9 MSIO259NB6 A8 GPIO16NB2
H23 DMOD_IN_N_C Buffered DMOD_IN_N drive input C9 MSIO256NB6 B6 GPIO17NB2
H25 LD_IN_D_C Buffered LD_IN_D FET drive input A4 MSIO247PB6 H13 GPIO1PB2
H34 BLO2 Bi-Level Detector output 2 F7 MSIO249PB6 G10 GPIO21PB2
H35 BLO1 Bi-Level Detector output 1 F8 MSIO249NB6 F10 GPIO21NB2
K23 SCP SCP input via J38 link header C16 MSIO282NB5 AB1 GPIO176NB4

LX7720 Daughter Board User's Manual
FMC-HPC Connector J10
© 2023 Microchip Technology Inc. LX7720 Daughter Board User Guide rev 3.1 - page 20
Table 18. Mapping of HPC1-FMC Pins, LX7720 Functionality, and RT-Polarfire FPGA Pins
FMC
Pin
LX7720 Signal
Name LX7720 Signal Type and Function RT-Polarfire FMC Net Name
RT-Polarfire
Pin Number
RT-Polarfire
Pin Name
C11 ADC1_C ADC2 bit stream output HPC1_LA06_N_B2 J17 GPIO16NB2
C27 UD_IN_A_C UD_IN_A FET drive input HPC1_LA27_P_B2 M3 GPIO279PB5
D27 LD_IN_C_C LD_IN_C FET drive input HPC1_LA26_N_B2 N9 GPIO281NB5
E10 UD_IN_B_C UD_IN_B FET drive input HPC1_HA09_N_B5 J15 GPIO14NB2/DQS
F7 UD_IN_C_C UD_IN_C FET drive input HPC1_HA04_P_B2 H20 GPIO30PB2
F8 LD_IN_B_C LD_IN_B FET drive input HPC1_HA04_N_B2 H19 GPIO30NB2
F11 LD_IN_A_C LD_IN_A FET drive input HPC1_HA08_N_B5 E12 GPIO3NB2
F13 SNS_OUT_A_C SNS_OUT_A bit stream output HPC1_HA12_P_B5 E16 GPIO13PB2
F14 SNS_OUT_B_C SNS_OUT_B bit stream output HPC1_HA12_N_B5 E17 GPIO13NB2
F19 BLO4 Bi-Level Detector output 4 HPC1_HA19_P_B5 P11 GPIO285PB5
G9 ADC3_C ADC3 bit stream output HPC1_LA03_P_B2 D11 GPIO8PB2/DQS
G16 RESET RESET logic input HPC1_LA12_N_B2 C15 GPIO23NB2
G18 OTW_FAULT OTW_FAULT output HPC1_LA16_P_B2 H13 GPIO4PB2
G21 CP_CLK_C 150kHz ±50kHz CP_CLK charge
pump clock input HPC1_LA20_P_B2 J2 GPIO286PB5
G24 DMOD_IN_P_C DMOD_IN_P drive input HPC1_LA22_P_B2 E9 GPIO312PB2/DQS
G25 UD_IN_D_C UD_IN_D FET drive input HPC1_LA22_N_B2 F9 GPIO312NB2/DQS
G28 BLO6 Bi-Level Detector output 6 HPC1_LA25_N_B2 T11 GPIO263NB5
G30 BLO5 Bi-Level Detector output 5 HPC1_LA29_P_B2 D4 GPIO311PB2
G31 BLO3 Bi-Level Detector output 3 HPC1_LA29_N_B2 D5 GPIO311NB2
H7 CLK_OUT_C CLK_OUT Σ-Δ mod clock output HPC1_LA02_P_B2 F20 GPIO31PB2
H8 MOD_CLK_C 24MHz to 32MHz MOD_CLK Σ-Δ
modulator clock input HPC1_LA02_N_B2 G20 GPIO31NB2
H10 ADC2_C ADC2 bit stream output HPC1_LA04_P_B2 E13 GPIO1PB2
H13 SNS_OUT_D_C SNS_OUT_D bit stream output HPC1_LA07_P_B2 F15 GPIO15PB2
H14 SNS_OUT_C_C SNS_OUT_C bit stream output HPC1_LA07_N_B2 F16 GPIO15NB2
H17 SM_EN SM_EN logic input HPC1_LA11_N_B2 A15 GPIO19NB2
H19 OC_FAULT OC_FAULT output HPC1_LA15_P_B2 D14 GPIO22PB2
H20 PR_FAULT PR_FAULT output HPC1_LA15_N_B2 D15 GPIO22NB2
H23 DMOD_IN_N_C DMOD_IN_N drive input HPC1_LA19_N_B2 K2 GPIO290NB5
H25 LD_IN_D_C LD_IN_D FET drive input HPC1_LA21_P_B2 E7 GPIO310PB2
H34 BLO2 Bi-Level Detector output 2 HPC1_LA30_P_B2 T10 GPIO267PB5
H35 BLO1 Bi-Level Detector output 1 HPC1_LA30_N_B2 U11 GPIO267NB5
K23 SCP SCP logic input HPC1_HA23_N_B5 G13 GPIO2NB2/DQS