Microchip Technology VSC8211 User manual

 2022 Microchip Technology Inc. and its subsidiaries DS00004531A-page 1
1.0 INTRODUCTION
This document provides a hardware design checklist for the Microchip VSC8211 product family. It is meant to help cus-
tomers achieve first-pass design success. These checklist items should be followed when utilizing the VSC8211 in a
new design. A summary of these items is provided in Section 11.0, "Hardware Checklist Summary". Detailed information
on these subjects can be found in the corresponding sections:
•Section 2.0, "General Considerations"
•Section 3.0, "Power"
•Section 4.0, "Twisted Pair Media Interface (CAT5)"
•Section 5.0, "SGMII/SerDes MAC Interface"
•Section 6.0, "Parallel MAC Interface"
•Section 7.0, "Device Clocks"
•Section 8.0, "Hardware Configuration Using CMODE Pins"
•Section 9.0, "Digital Interface"
•Section 10.0, "Miscellaneous"
2.0 GENERAL CONSIDERATIONS
2.1 Required References
The VSC8211 implementor should have the following documents on hand:
•VSC8211 Single-Port 10/100/1000BASE-T, 1000BASE-X, and 100BASE-FX PHY Data Sheet
• Device documents on the VSC8211 product page at www.microchip.com
• VSC8211EV EVB schematics and PCB information in the VSC8211 Evaluation Board User Guide as well as
VSC8211 PCB design and layout guidelines at www.microchip.com.
2.2 Pin Check
• Check the pinout of the part against the data sheet. Ensure that all pins match the data sheet and are configured
as inputs, outputs, or bidirectional for error checking.
2.3 Ground
• A single ground reference as a system ground is used for all ground pins. Use one continuous ground plane to
ensure a low-impedance ground path and a continuous ground reference for all signals.
• A chassis ground is necessary between the magnetics and RJ45 connector at line side for better EMI and ESD.
VSC8211
Hardware Design Checklist

VSC8211
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3.0 POWER
Table 3-1 shows the power supply pins for the VSC8211.
TABLE 3-1: POWER SUPPLY PINS
Pin Name 117 LBGA
Ball
Voltage
(V) Descriptions Associated Functional Pins
Digital I/O Power Pins
VDDIOMAC C6, C3, D3 3.3V or
2.5V
Power for the parallel
MAC interface
RXLOS/SIGDET, RXD7:0], RXDV, RXER,
RXCLK, COL, CRS, TXCLK, TXER, GTX-
CLK, TXEN, TXD [7:0], MODDEF0/CLK-
OUTMAC
VDDIOMICRO G7 3.3V or
2.5V
3.3V or 2.5V,
Power for SMI,
EEPROM interface and
CLKOUTMICRO clock
EECLK/PLLMODE, EEDAT, TXDIS/,
SRESET, MDINT, MODDEF1/MDC, MODD-
EF2/MDIO, CLKOUTMICRO/OSCDIS
VDDIOCTRL D10 3.3V or
2.5V
Power for JTAG I/O RESET, TDO, TDI, TMS, TCK, TRST,
Digital Core Power Pins
VDD12 C10, C11, F3,
F4, G3
1.2V Power for internal digi-
tal logic, and SerDes/
SGMII I/O power
RDP, RDN, TDP, TDN, SCLKP, SCLKN,
SDIN, SDIP, SDOP, SDON
Analog Power Pins
VDD33A F10, G10, G9,
G8
3.3V Power for MDI,
CMODE, PLL, and LED
blocks. For analog core
power, use ferrite bead.
LED [4:0], CMODE7:0], TXVND, TXVPD,
TXVNC, TXVPC, TXVNB, TXVPB, TXVNA,
TXVPAXTAL2, XTAL1/REFCLK, REF-
FILT, REFREXT
VDD12A H7 1.2V Power of PLL and ADC
blocks. For analog core
power, use ferrite bead.
—
Ground Pins
VSS C5, D4, D5,
D6, D7, D8,
D9, E4, E5,
E6, E7, E8,
E9, E10, F5,
F6, F7, F8,
F9, J7, H9,
J9, H11, J11
0V Ground for all blocks —

 2022 Microchip Technology Inc. and its subsidiaries DS00004531A-page 3
VSC8211
3.1 Current and Power Requirements
• Ensure that the voltage regulators and power distribution are designed to adequately support these current
requirements for each power rail. Refer to Table 3-2 for different system configurations. Note that the power dissi-
pation values in the table need 25% to 30% based on the maximum current for the power supply designs of 3.3V,
1.2V, and 2.5V. Designs with 100Base-FX need an additional margin of 35% to 50% based on the typical current
for the power supply designs of 3.3V and 1.2V. See Table 3-3 for details.
TABLE 3-2: MAXIMUM RAIL CURRENT
Power Rail Voltage (V) Maximum Current (mA) Power Dissipation (mW)
VDDIO at 3.3V, RGMII-CAT5, 1000BASE-T, FD, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode Off
VDD33A 3.3 110 363
VDDIOMAC, VDDIOMI-
CRO,
VDDIOCTRL
3.3 53 175
VDD12 1.2 324 389
VDD12A 1.2 38 46
VDDIO at 2.5V, RGMII-CAT5, 1000BASE-T, FD, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode Off
VDD33A 3.3 110 363
VDDIOMAC,
VDDIOMICRO,
VDDIOCTRL
2.5 41 103
VDD12 1.2 324 389
VDD12A 1.2 38 46
VDDIO at 3.3 V, RGMII-CAT5, 100BASE-TX, FD, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode Off
VDD33A 3.3 91.5 303
VDDIOMAC, VDDIOMI-
CRO,
VDDIOCTRL
3.3 19 63
VDD12 1.2 103 124
VDD12A 1.2 26.5 32
VDDIO at 2.5 V, RGMII-CAT5, 100BASE-TX, FD, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode Off
VDD33A 3.3 91.5 303
VDDIOMAC,
VDDIOMICRO,
VDDIOCTRL
2.5 15 38
VDD12 1.2 103 124
VDD12A 1.2 26.5 32
VDDIO at 3.3 V, RGMII-CAT5, 10BASE-T, FD, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode Off
VDD33A 3.3 152 502
VDDIOMAC,
VDDIOMICRO,
VDDIOCTRL
3.3 14 46
VDD12 1.2 31 37
VDD12A 1.2 27 32
VDDIO at 2.5 V, RGMII-CAT5, 10BASE-T, FD, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode Off
VDD33A 3.3 152 502
VDDIOMAC,
VDDIOMICRO,
VDDIOCTRL
2.5 11 28

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DS00004531A-page 4  2022 Microchip Technology Inc.and its subsidiaries
VDD12 1.2 31 37
VDD12A 1.2 27 32
VDDIO at 3.3 V, RGMII-Fiber, 1000BASE-X, FD, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode Off
VDD33A 3.3 20 66
VDDIOMAC,
VDDIOMICRO,
VDDIOCTRL
3.3 53 175
VDD12 1.2 56.5 68
VDD12A 1.2 23 28
VDDIO at 2.5 V, RGMII-Fiber, 1000BASE-X, FD, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode Off
VDD33A 3.3 20 66
VDDIOMAC,
VDDIOMICRO,
VDDIOCTRL
2.5 42 105
VDD12 1.2 56.5 68
VDD12A 1.2 23 28
VDDIO at 3.3 V, SerDes-CAT5, 1000BASE-T, FD, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode Off
VDD33A 3.3 112 370
VDDIOMAC,
VDDIOMICRO,
VDDIOCTRL
3.3 14 46
VDD12 1.2 343 412
VDD12A 1.2 37 44
VDDIO at 2.5 V, SerDes-CAT5, 1000BASE-T, FD, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode Off
VDD33A 3.3 112 370
VDDIOMAC,
VDDIOMICRO,
VDDIOCTRL
2.5 10 33
VDD12 1.2 343 412
VDD12A 1.2 37 44
VDDIO at 3.3 V, SerDes-CAT5, 1000BASE-T, FD, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode On
VDD33A 3.3 112 370
VDDIOMAC,
VDDIOMICRO,
VDDIOCTRL
3.3 14 46
VDD12 1.2 283 340
VDD12A 1.2 37 44
TABLE 3-2: MAXIMUM RAIL CURRENT
Power Rail Voltage (V) Maximum Current (mA) Power Dissipation (mW)

 2022 Microchip Technology Inc. and its subsidiaries DS00004531A-page 5
VSC8211
3.2 Power Supply Planes
• The VSC8211 requires two power rails of 3.3V and 1.2V or three power rails of VDDIO 2.5V, 3.3V, and 1.2V. The fil-
tered analog 1.2V and 3.3V supplies should not be shorted to any other digital supply at the package or PCB level.
See Section 3.3, "Power Circuit Connection and Analog Power Plane Filtering".
• The most important PCB design and layout considerations are as follows:
- Ensure that the return plane is adjacent to the power plane (without a signal layer in between).
- Ensure that a single plane is used for voltage reference with splits for individual voltage rails within that plane.
Try to maximize the area of each power split on the power plane based on corresponding via coordinates for
each rail to maximize coupling between each voltage rail and the return plane.
- Minimize resistive drop while efficiently conducting away heat from the device using 1 oz copper cladding.
• Four-layer PCBs with only one designated power plane must adhere to proper design techniques to prevent ran-
dom system events, such as CRC errors. Each power supply requires the lowest resistive drop possible to power
the pins of the device with correctly positioned local decoupling. For more information, see Section 3.4, "Bulk
Decoupling Capacitors".
• Ferrite beads should be used over a series inductor filter whenever possible, particularly for high-density or high-
power devices.
3.3 Power Circuit Connection and Analog Power Plane Filtering
• The analog power supplies are:
- VDD33A
- VDD12A
• A ferrite bead should be used to isolate each analog supply from the rest of the board. The bead should be placed
in series between the bulk decoupling capacitors and local decoupling capacitors.
• Because all PCB designs yield unique noise coupling behavior, not all ferrite beads or decoupling capacitors may
be needed for every design. It is recommended that system designers provide an option to replace the ferrite
beads with 0Ω resistors once a thorough evaluation of system performance is completed.
• Ferrite beads are not recommended for digital supplies VDDIOMAC, VDDIOMICRO, VDDIOCTRL, and VDD12.
The power and ground connections are shown in Figure 3-1.
TABLE 3-3: TYPICAL RAIL CURRENTS FOR DESIGN WITH 100BASE-FX
Power Rail Voltage (V) Typical Current (mA) Power Dissipation (mW)
VDDIO at 3.3V, RGMII-100BASE-FX, FDX, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode Off
VDD33A 3.3 96 317
VDDIOMAC,
VDDIOMICRO,
VDDIOCTRL
3.3 19 63
VDD12 + VDD12A 1.2 145 174

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DS00004531A-page 6  2022 Microchip Technology Inc.and its subsidiaries
3.4 Bulk Decoupling Capacitors
• Bulk decoupling capacitors can be placed at any convenient position on the board. Local decoupling capacitors
should be X5R or X7R ceramic and placed as close as possible to the VSC8211's power pins.
• Make sure that enough bulk capacitors (1 µF to 22 µF) are incorporated in each power rail of the power supply.
• If the VSC8211 device is on the top layer of the printed circuit board (PCB), the best location for local decoupling
capacitors is on the bottom or underside of the PCB, directly under the device.
FIGURE 3-1: POWER SUPPLY CONNECTIONS AND LOCAL FILTERING
VSC8211
VDD33A
VSS
VDD12A
Ferrite
Bead
1.2V
0.1µF
1µF
10µF
Ferrite
Bead
3.3V
VDDMAC
4 pins
1µF 1µF
F10,G10,G9, G8 H7
C5, D4, D5, D6, D7,
D8, D9, E4, E5, E6,
E7, E8, E9, E10, F5,
F6, F7, F8, F9, J7,
H9, J9, H11, J11
VDD12
5 X 0.1µF
1.2V
5 pins
C10, C11,
F3, F4, G3
24 pins
4 X 0.1µF
3.3V or 2.5V
3 X 0.1µF
VDDIOMICRO
VDDIOCTRL
0.1µF
0.1µF
C6, C3, D3
G7
D10
1µF
3 pins

 2022 Microchip Technology Inc. and its subsidiaries DS00004531A-page 7
VSC8211
4.0 TWISTED PAIR MEDIA INTERFACE (CAT5)
4.1 10/100/1000 Mbps Interface Connection
The VSC8211 has one GPHY that supports 10/100/1000Base-T Ethernet Gigabit port. Details on the pin numbers for
this GPHY are described as follows:
•TXVNA (J12): This pin is the transmit/receive negative connection from Pair A of the internal GPHY. This pin con-
nects to the 10/100/1000 magnetics. No external terminator and bias are needed.
•TXVPA (J13): This pin is the transmit/receive positive connection from Pair A of the internal GPHY. This pin con-
nects to the 10/100/1000 magnetics. No external terminator and bias are needed.
•TXVNB (H12): This pin is the transmit/receive negative connection from Pair B of the internal GPHY. This pin con-
nects to the 10/100/1000 magnetics. No external terminator and bias are needed.
•TXVPB (H13): This pin is the transmit/receive positive connection from Pair B of the internal GPHY. This pin con-
nects to the 10/100/1000 magnetics. No external terminator and bias are needed.
•TXVNC (G12): This pin is the transmit/receive negative connection from Pair C of the internal GPHY. This pin con-
nects to the 10/100/1000 magnetics. No external terminator and bias are needed.
•TXVPC (G13): This pin is the transmit/receive positive connection from Pair C of the internal GPHY. This pin con-
nects to the 10/100/1000 magnetics. No external terminator and bias are needed.
•TXVND (F12): This pin is the transmit/receive negative connection from Pair D of the internal GPHY. This pin con-
nects to the 10/100/1000 magnetics. No external terminator and bias are needed.
•TXVPD (F13): This pin is the transmit/receive positive connection from Pair D of the internal GPHY. This pin con-
nects to the 10/100/1000 magnetics. No external terminator and bias are needed.
There are two types of 10/100/1000 Mbps channel connection solutions. As shown in Figure 4-1, the first solution is for
cases wherein no electrical noise external environment and ESD are taken into consideration. The second solution, on
the other hand, is for instances wherein electrical noise external environment and ESD are considered. See Figure 4-2.
FIGURE 4-1: FIRST SOLUTION FOR 10/100/1000 MBPS CHANNEL CONNECTION
VSC8211
TXVNA
4 x 0.1µF
RJ45
CONNECTOR
4 x 75Ω
System GND
8
7
6
5
4
2
1
J12
MAGNETICS
J13
H12
H13
G12
G13
F12
F13
Channel A
Channel B
Channel C
Channel D
TXVPA
Chassis GND
Metal Case
1000pF 2KV
3TXVNB
TXVPB
TXVNC
TXVPC
TXVND
TXVPD
RJ45
Chassis GND

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DS00004531A-page 8  2022 Microchip Technology Inc.and its subsidiaries
4.2 10/100/1000 Magnetics and RJ45 Connector Connection
• The center tap connection on the VSC8211 side for Pair A channel only connects a 0.1 µF capacitor to GND. No
bias is needed.
• The center tap connection on the VSC8211 side for Pair B channel only connects a 0.1 µF capacitor to GND. No
bias is needed.
• The center tap connection on the VSC8211 side for Pair C channel only connects a 0.1 µF capacitor to GND. No
bias is needed.
• The center tap connection on the VSC8211 side for Pair D channel only connects a 0.1 µF capacitor to GND. No
bias is needed.
• The center taps from all four pairs of the magnetics should not be connected together without the 0.1 µF capaci-
tors to ground. The reason is the common-mode voltage can be different between pairs, especially for 10/100
operation. (Pairs A and B are active, while Pairs C and D are inactive.)
• It is recommended that the center tap connection for each pair (A, B, C, and D) on the cable side (RJ45 side) be
terminated with a 75Ω resistor through a common 1000 pF, 2 kV capacitor to chassis ground.
• Only one 1000 pF, 2 kV capacitor to chassis ground is required. It is shared by Pair A, Pair B, Pair C, and Pair D
center taps.
• Only one 1000 pF, 2 kV capacitor or a ferrite bead should connect between the chassis ground and the system
ground.
• The RJ45 shield should connect to the chassis ground. This includes RJ45 connectors with or without integrated
magnetics. See Section 4.3, "PCB Layout Considerations" for guidance on how the chassis ground should be cre-
ated from system ground.
• For the magnetics selection, please refer to magnetics suggested guidelines (ENT-AN0098 Magnetics Guide on
Microchip Technology product page) for reference.
FIGURE 4-2: SECOND SOLUTION FOR 10/100/1000 MBPS CHANNEL CONNECTION
1000pF 2KV
System GND Chassis GND
Ferrite bead
VSC8211
TXVNA
4 x 0.1µF
RJ45
CONNECTOR
4 x 75Ω
System GND
8
7
6
5
4
2
1
J12
MAGNETICS
J13
H12
H13
G12
G13
F12
F13
Channel A
Channel B
Channel C
Channel D
TXVPA
Chassis GND
Metal Case
1000pF 2KV
3TXVNB
TXVPB
TXVNC
TXVPC
TXVND
TXVPD
RJ45
Chassis GND

 2022 Microchip Technology Inc. and its subsidiaries DS00004531A-page 9
VSC8211
4.3 PCB Layout Considerations
• All differential pairs of the MDI interface traces should have a characteristic impedance of 100Ω to the GND plane.
This is a strict requirement to minimize return loss that requires a PCB designer and FAB house.
• Each MDI pair should be placed as close as possible in parallel to minimize EMI and crosstalk. Each member of a
pair should be matched in length to prevent mismatch in delay that would cause common-mode noise.
• Ideally, there should be no crossover or via on the signal paths.
• Incorporate a 1000 pF 2 kV capacitor or a ferrite bead to connect between the chassis ground and the system
ground. This allows some flexibility at EMI testing for different grounding options if leaving the footprint open
keeps the two grounds separated. For best performance, short the grounds together with a ferrite bead or a
capacitor. Users are required to place the capacitor or ferrite bead far away from the VSC8211 device or other
sensitive devices in the PCB layout placement for better ESD.
4.4 100 MBPS Fiber Support Over Copper Media Interface
• The VSC8211 supports 100BASE-FX over its copper media interface by using pairs A and B, which provide TX
and RX differential connections, respectively. If the fiber module does not have internal AC coupling capacitors,
then they are required between the PHY and fiber module. The value should be 0.1 µF.
• The RXLOS/SIGDET signal is not used in this mode.
• The PHY can be brought into the 100BASE-FX Operation mode using the following configuring sequence:
1. Initialize the PHY into the specific MAC-to-Copper Operating mode for the MAC interface type required
(register23).
2. Disable Auto-Negotiation and force the 100BASE-T FDX mode (register 0).
3. Run the 100BASE-FX initialization script. For more details, see Section 33.4 of the data sheet.
•Figure 4-3 shows the copper media interface connections to 100Base-FX SFP.
FIGURE 4-3: COPPER MEDIA INTERFACE CONNECTIONS FOR 100BASE-FX
100BASE-FX
SFP Modules
TD+
TD-
RD+
RD-
RX_LOS
SFP Module
TX_FAULT
MOD_DEF0
/PRESENT
RATE_SELECT
TX_DISABLE
MOD_DEF1/SCL
MOD_DEF2/SDA
VSC8211
Copper Media Interface
100 Ω
100 Ω
TXVPA
TXVNA
TXVPB
TXVNB H12
H13
J12
J13
Note:
 SFP module has AC coupling capacitors and termination resistors
internally for TD+/- pair and RD+/- pair.
 SFP MOD_DEF0 pin can connect to a LED. The LED can be turned on
to indicate SFP present when SFP module is plugged in, because this
MOD_DEF0 pin has an internal about 100Ω pull-down resistor.
3.3V

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5.0 SGMII/SERDES MAC INTERFACE
5.1 SGMII/SerDes MAC Pins and Connection
• The VSC8211 device supports one SGMII (Serial Gigabit Media Independent Interface) MAC or one SerDes
MACs.
• Refer to Table 5-1 for pin number details. For SGMII/SerDes interface connections, see Figure 5-1 and Figure 5-2.
5.2 SGMII/SerDes MAC
• SGMII (Serial Gigabit Media Independent Interface) serializes a gigabit interface (such as GMII) into a high-speed,
two-pin differential interface. Using SGMII/SerDes can reduce the pin count to four pins per Ethernet port.
TABLE 5-1: SGMII/SERDES MAC INTERFACE PINS
Pin Name Pin Number Type Description
RDN H1 Output DIFF Receiver Data Differential Output Pair (used in SerDes/SGMII to CAT5
and Parallel MAC to SerDes/AMS PHY operating modes)
RDP H2 Output DIFF
TDN J4 Input DIFF Transmitter Data Differential Input Pair (used in SerDes/SGMII to CAT5
and Parallel MAC to SerDes/AMS PHY operating modes)
TDP J3 Input DIFF
SCLKN J2 Output DIFF SGMII Clock Differential Output Pair (used in SGMII to CAT5/SerDes/
AMS PHY operating modes).
SCLKP J1 Output DIFF
SDIP G2 Input DIFF Fiber Transceiver Differential Input Pair (used in SGMII to SerDes)
SDIN G1 Input DIFF Fiber 1000Base-X SFP operation mode
SDOP F2 Output DIFF Fiber Transceiver Differential Output Pair (used in SGMII to SerDes)
SDON F1 Output DIFF Fiber 1000Base-X SFP operation mode
FIGURE 5-1: SGMII/SERDES MAC INTERFACE CONNECTIONS
VSC8211
SGMII/SerDes MAC Interface
SGMII/SerDes MAC
100 Ω
100 Ω
TDP
TDN
RDP
RDN
TDP
TDN
RDP
RDN
0.01µF
0.01µF
0.01µF
0.01µF
H1
H2
J4
J3
SGMII/SerDes Controller
SGMII/SerDes MAC side termination
depends on SGMII/SerDes MAC request
100 Ω
SCLKP
SCLKN
SCLKP
SCLKN
0.01µF
0.01µF
J2
J1
Optional- May not be
required by the MAC
3.3V
SIGDET
C7
4.7K Ω

 2022 Microchip Technology Inc. and its subsidiaries DS00004531A-page 11
VSC8211
5.3 SerDes MAC Interface to SFP
• When connected to a SerDes MAC-compliant to 1000BASE-X, the VSC8211 device provides data throughput at a
rate of 1000 Mbps only. 10 Mbps and 100 Mbps rates are not supported.
• For additional pin in SerDes MAC interface to SFP fiber transceiver module, see Table 5-2. Figure 5-2 shows the
SerDes MAC interface connection to 1000Base-X SFP.
TABLE 5-2: ADDITIONAL PIN RXLOS FOR SERDES TO SFP
Pin Name Pin Number Type Description
RXLOS/SIGDET C7
I/O
The customer can connect the SIGDET pin from a Fiber module (or the
RXLOS from an SFP). See Table 8-4 for information on using CMODE
configuration pin CMODE1[3] to set either RXLOS or SIGDET.
RXLOS – Receiver Loss of Signal Output (valid in SFP mode, when
MII Register 21E.15 = 1)
RXLOS pin is input, the receiving loss signal comes from the output of
SFP LOS pin. This active-high signal is asserted when receiving signal
loss.
SIGDET – SerDes Signal Detect (I/O) (valid in IEEE Mode, when MII
Register 21E.15= 0)
SIGDET can be configured as an input or output and can be configured
to function as active-low or active-high by using CMODE1[1] and
CMODE1[3] at startup. See Table 8-3 and Table 8-4 for details.
SIGDET as Input:
When used as an input, the SIGDET signal is meant to be connected to
the signal detect output of the fiber optic transceiver. If SIGDET is high,
this indicates received activity on the fiber optic transceiver. If SIGDET
is not used as an input, the PHY internally generates the signal detect
function from the incoming data on the TDP and TDN signal pins.
SIGDET as Output:
For Serial MAC to CAT5 Media PHY Operating modes, SIGDET is
asserted if a valid CAT5 link has been established.

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DS00004531A-page 12  2022 Microchip Technology Inc.and its subsidiaries
5.4 SGMII/SerDes MAC Interface Design Rules
• Use AC coupling with 0.01 µF capacitors for chip-to-chip applications. Place the capacitors at the receiving end of
the signals.
• Traces should be routed as 50Ω (100Ω differential) controlled impedance transmission lines (microstrip or strip-
line).
• Traces should be of equal length (within 10 mils) on each differential pair to minimize skew.
• Traces should be run adjacent to a single ground plane to match impedance and minimize noise.
• Spacing equal to five times the ground plane gap is recommended between adjacent tracks to reduce cross-talk
between differential pairs. Minimum spacing of three times the ground plane gap is required.
• Traces should avoid vias and layer changes. If layer changes cannot be avoided, mode-suppression vias should
be included next to the signal vias to reduce the strength of any radiating spurious fields.
• Guard vias should be placed no greater than one-quarter wavelength apart around the differential pair tracks.
• If the SGMII/SerDes port is unused, both the RDx pair and TDx pair pins can be left floating (no-connect).
FIGURE 5-2: SERDES MAC INTERFACE TO 1000BASE-X SFP OR 1000BASE-T SFP
CONNECTIONS
1000BASE-X SFP
TD+
TD-
RD+
RD-
RX_LOS
SFP Module
TX_FAULT
MOD_DEF0
/PRESENT
RATE_SELECT
TX_DISABLE
MOD_DEF1/SCL
MOD_DEF2/SDA
VSC8211
SGMII/SerDec MAC Interface
100 Ω
100 Ω
TDP
TDN
RDP
RDN H1
H2
J4
J3
Note:
 SFP module has AC coupling capacitors and termination resistors
internally for TD+/- pair and RD+/- pair.
 SFP MOD_DEF0 pin can connect to a LED. The LED can be turned on
to indicate SFP present when SFP module is plugged in, because this
MOD_DEF0 pin has an internal about 100Ω pull-down resistor.
3.3V
RXLOS/SIGDET
C7
3.3V

 2022 Microchip Technology Inc. and its subsidiaries DS00004531A-page 13
VSC8211
6.0 PARALLEL MAC INTERFACE
The VSC8211 parallel MAC interface supports GMII, RGMII, MII as well as TBI and RTBI interfaces. For detailed GMII/
RGMII/MII pin descriptions and system design connections, refer to Section 6.1, "GMII/RGMII/MII Interface Pins". For
detailed TBI/RTBI pin descriptions and system design connections, refer to Section 6.2, "TBI/RTBI Interface Pins".
6.1 GMII/RGMII/MII Interface Pins
The VSC8211 supports GMII, RGMII, and MII interfaces. The GMII and RGMII support all three speeds—10 Mbps,
100 Mbps, and 1000 Mbps—and can be used to interface to other end devices with GMII and RGMII interfaces. The MII
interface supports all two speeds of 10 Mbps and 100 Mbps. It can also be used to interface to other end devices with
MII interface. See Table 6-1 for pin details.
TABLE 6-1: GMII/RGMII/MII INTERFACE PINS
Pin Name Pin Number Type Description
RXCLK, RXC B5 O Receive Clock Output (GMII, RGMII, and MII modes)
Receive data is sourced from the PHY synchronous to the rising
edge of RXCLK in GMII/MII modes or RXC in RGMII mode. This
clock is recovered from the media.
RXER, RXCTL A4 O RXER – Receiver Error Output for GMII and MII
RXCTL – Multiplexed receive data valid for RGMII receive control
output
RD [7:4], RD [3:0],
RXD [3:0]
A7, B7, A6, B6 O RD [7:4] – RGMII data output. Use the falling edge of RXC.
RD [3:0] – RGMII data output. Use the rising edge of RXC.
RXD [3:0] – GMII/MII data output. Use the rising edge of RXCLK.
RXD [7:4] A9, B9, A8, B8 O Receive Data Code Group (GMII mode)
Receive data is driven out of the device synchronously to the rising
edge of RXCLK.
RXDV A5 O Receive Data Valid Output (GMII, MII modes)
RXDV is asserted by the PHY to indicate that the PHY is present-
ing recovered and decoded data on the RXD pins. RXDV is syn-
chronous with respect to RXDK.
CRS C4 O Carrier Sense Output (GMII, MII modes)
Valid only in GMII and MII Half-Duplex modes, CRS is asserted
high when a valid carrier is detected on the media.
COL B4 O Collision Detect Output (GMII, MII modes)
This output is asserted high when a collision is detected on the
media. For Full-Duplex modes, this output is always low.
TXCLK A3 O Transmit Clock (MII mode)
25 MHz (100 Mb mode) or 2.5 MHz (10 Mb mode) MII clock output
The MAC uses the rising edge of this clock to synchronize TXD
data.

VSC8211
DS00004531A-page 14  2022 Microchip Technology Inc.and its subsidiaries
6.1.1 GMII INTERFACE
• The VSC8211 GMII interface supports 1000 Mbps only. GMII is used as an interface to a GMII-compatible MAC.
The devices are compliant with the GMII interface specification when VDDIOMAC is operating at 3.3 V. The
devices can also support the GMII interface at 2.5V.
• The GMII interface contains two distinct groups of signals—one is for transmission, and the other is for receiving.
The VSC8211 GMII and MCU GMII connections are shown in Figure 6-1. Refer to Table 6-1 for the pin details.
GTXCLK, TXC A2 I Transmit Clock Input (GMII mode)
The transmit clock GTXCLK is a 125 MHz, +/–100 ppm reference
clock used to synchronize the TXD data code group, TXD [7:0],
into the PHY.
Transmit Clock Input (RGMII mode)
The transmit clock TXC shall be either a 125 MHz or 25 MHz (for
1000 Mb or 100 Mb modes, respectively), with a +/–50 ppm toler-
ance.
TXER, TXCTL B3 I TXER – Transmit Error Input for GMII and MII
TXCTL – Multiplexed transmit data valid for RGMII transmit con-
trol Input
TD [7:4], TD [3:0],
TXD [3:0]
C1, C2, B1, B2 I TD [7:4] – RGMII data input. Use the falling edge of TXC.
TD [3:0] – RGMII data input. Use the rising edge of TXC.
TXD [3:0] – GMII/MII data input. Use the rising edge of GTXCLK.
TXD [7:4] E1, E2, D1, D2 I Transmit Data Inputs (GMII mode)
Transmit code-group data is input on these pins synchronously to
the rising edge of GTXCLK in GMII mode.
TXEN A1 I Transmit Enable Input (GMII, MII modes)
Synchronized to the rising edge of GTXCLK (1000 Mb mode) or
TXCLK (100 Mb mode), this input indicates valid data is present
on the TXD bus.
TABLE 6-1: GMII/RGMII/MII INTERFACE PINS
Pin Name Pin Number Type Description

 2022 Microchip Technology Inc. and its subsidiaries DS00004531A-page 15
VSC8211
• VSC8211 GMII drive pins do not require external series termination resistors because they include internal 50Ω
series termination resistors.
• Other-end GMII interface drive pins need external series termination resistor RT if there are not enough internal
50Ω series termination resistors in GMAC GMII. It is recommended to use 22Ω to 33Ω for RT or use the resistor
value by using its IBIS model simulation result.
6.1.2 MII INTERFACE
• The MII interface supports all two speeds—10 Mbps and 100 Mbps. MII is used as an interface to an MII-compat-
ible MAC. The devices are compliant with the MII interface specification. The devices can also support the MII
interface at 3.3V or 2.5 V.
• The MII interface contains two distinct groups of signals—one for transmission and one for receiving. The
VSC8211 MII and MCU MII connections are shown in Figure 6-2. Refer to Table 6-1 for the pin details.
FIGURE 6-1: CONNECTIONS BETWEEN VSC8211 GMII AND MCU GMII INTERFACE
MCU GMAC
GMII Interface
RXDV
RXD[7:0]
TXD[7:0]
COL
VSC8211
GMII Interface
TXD[7:0]
RX_CLK
GTX_CLK
GTXCLK
TX_ER
TXER
TX_EN
TXEN
CRS
RXER
E1,E2, D1, D2,
C1, C2, B1, B2
A2
B3
A1
B4
A2
A9, B9, A8, B8,
A7, B7, A6, B6
B5
A5
A4
RXD[7:0]
RXCLK
8 x 50Ω
50Ω
RXDV
50Ω
RXER
50Ω
CRS
50Ω
COL
50Ω
R T
8XR T
R T
R T

VSC8211
DS00004531A-page 16  2022 Microchip Technology Inc.and its subsidiaries
• The VSC8211 MII drive pins do not need external series termination resistors because they have internal 50Ω
series termination resistors.
• Other-end MII interface drive pins need external series termination resistor RT if there are not enough internal 50Ω
series termination resistors in MAC MII. It is recommended to use 22Ω to 33Ω for RT or use the resistor value by
using its IBIS model simulation result.
6.1.3 RGMII INTERFACE CONNECTIONS
• The VSC8211 provides RGMII. The RGMII interface supports all three speeds 10 Mbps, 100 Mbps, and
1000 Mbps. The RGMII interface contains two distinct groups of signals—one for transmission and one for receiv-
ing.
• The VSC8211 device supports RGMII that is used as an interface to an RGMII-compatible MAC. The devices are
compliant with the RGMII interface specification 2.0. The devices can also support the RGMII interface at 3.3V or
2.5 V.
• MCU GMAC RGMII should have the same speed and duplex as the VSC8211 RGMII interface. The VSC8211
RGMII interface connections with MCU RGMII are shown in Figure 6-3. Refer to Table 6-1 for the pin details.
FIGURE 6-2: CONNECTIONS BETWEEN VSC8211 MII AND MII MCU INTERFACE
MCU MAC
MII Interface
RXDV
RXD[3:0]
TXD[3:0]
COL
VSC8211
MII Interface
TXD[3:0]
RX_CLK
TX_CLK
TX_ERTXER
TX_EN
TXEN
CRS
RXER
C1, C2, B1, B2
A3
B3
A1
B4
A2
A7, B7, A6, B6
B5
A5
A4
If MAC MII interface does not have a TX_ER pin, then
VSC8211 TXER pin B3 should have a pull-down resistor to
ground.
RXD[3:0]
RXCLK
4 x 50Ω
50Ω
RXDV
50Ω
RXER
50Ω
CRS
50Ω
COL
50Ω
TXCLK
50Ω
R T
R T
4XR T

 2022 Microchip Technology Inc. and its subsidiaries DS00004531A-page 17
VSC8211
6.1.4 TIMING CONSIDERATIONS FOR DESIGN WITH RGMII INTERFACE
• The VSC8211 supports RGMII V2.0 specifications. The RGMII interfaces need to meet a minimum of 1.0 ns and a
maximum of 2.6 ns of data to input clock delay/skew in RGMII V2.0 specification by setting the Ingress Clock
Delay and the Egress Clock Delay. The recommended VSC8211 RGMII data to input/output clock delay/skew set-
ting principles are specified in Table 6-2.
• There are two ways to set RGMII data to input/output clock delay/skew. Designers may use either strap pin
CMODE5 or the register 23 (17h) bits [11:8]. For using CMODE5 strapping, refer to Table 8-2 and Table 8-3.
• The VSC8211 RGMII register setting is based on other end RGMII clock input/output clock delay/skew and RGMII
interface traces routing with equal length for two distinct groups of signals in the PCB layout.
FIGURE 6-3: CONNECTIONS BETWEEN VSC8211 MII AND RGMII MCU INTERFACE
TABLE 6-2: REFERENCE FOR RGMII STRAP PINS OR REGISTER CONFIGURATION
Case
Number
VSC8211
Strap Pins
CMODE5 Bits
VSC8211 RGMII
Data to
RXC and TXC
Output and Input
Delay/Skew
VSC8211 RGMII
Setting Control
Register 23 (17h)
VSC8211 RGMII
Clock Delay/Skew
Setting
Other End RGMII
Data to
RXC and TXC Out-
put and Input
Delay/Skew
1
CMODE5[1:0] =10
Receive 0.0 ns
Delay
Data to Ingress
Clock Input Skew
(RGMII_TXC)
Bits [11:10] = 00
0.0 ns Delay
No Delay 0.0 ns Data to Egress
Clock Output
Default is about
1.5 ns delay
CMODE5[3:2] =10
Transmit 0.0 ns
Delay
Data to Egress
Clock Output Skew
(RGMII_RXC)
Bits [9:8] = 00
0.0 ns Delay
No Delay 0.0 ns Data to Ingress
Clock Input Default
is about 1.5 ns
delay
Note 1: If other-end RGMII data to RXC output and data to TXC input delay is not 0.0 ns/0.2 ns (NO DELAY) as
default or the DELAY is not 1.5 ns/1.7 ns as default, then there is a need to set the strap pin CMODE5 or
the register 23 bits [11:8] to other values to meet the minimum 1.0 ns and maximum 2.6 ns specification in
RGMII V2.0 for both VSC8211 and other-end RGMII data to clock input/output delay/skew.
MCU GMAC RGMII
Interface
RXDV/RX_CTL
RXD[3:0]
TXC/GTXC
TXD[3:0]
TXEN/TX_CTL
VSC8211
RGMII Interface
RXCTL
TXC
RD[3:0]
RXC
TD[3:0]
TXCTL
RXC/GRXC
R T
4XR T
R T
4 x 50Ω
50Ω
50Ω
A7, B7, A6, B6
B5
A4
C1, C2, B1, B2
A2
B3

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DS00004531A-page 18  2022 Microchip Technology Inc.and its subsidiaries
6.2 TBI/RTBI Interface Pins
The VSC8211 supports TBI and RTBI interfaces. The TBI and RTBI support all three speeds—10 Mbps, 100 Mbps, and
1000 Mbps—and can be used to interface to other end devices with TBI and RTBI interfaces. See Table 6-3 for pin
details.
2
CMODE5[1:0] =11
Receive 1.5 ns
Delay
Data to Ingress
Clock Input
Skew
(RGMII_TXC)
Bits [11:10] = 01
1.5 ns Delay
Suggest set to
1.5 ns delay
(1 ns and 2.6 ns)
Data to Egress
Clock Output
Default is No delay
0.0 ns
CMODE5[3:2] =11
Transmit 1.5 ns
Delay
Data to Egress
Clock Output Skew
(RGMII_RXC)
Bits [9:8] = 01
1.5 ns Delay
Suggest set to
1.5 ns delay
(1 ns and 2.6 ns)
Data to Ingress
Clock Input Default
is No delay 0.0 ns
3
CMODE5[1:0] =10
Receive 0.0 ns
Delay
Data to Ingress
Clock Input
Skew
(RGMII_TXC)
Bits [11:10] = 00
0.0 ns Delay
No Delay 0.0 ns Data to Egress
Clock Output
Default is about
1.5 ns delay
CMODE5[3:2] =11
Transmit 1.5 ns
Delay
Data to Egress
Clock Output Skew
(RGMII_RXC)
Bits [9:8] = 01
1.5 ns Delay
Suggest set to
1.5 ns delay
(1 ns and 2.6 ns)
Data to Ingress
Clock Input Default
is No delay 0.0 ns
4
CMODE5[1:0] =11
Receive 1.5 ns
Delay
Data to Ingress
Clock Input
Skew
(RGMII_TXC)
Bits [11:10] = 01
1.5 ns Delay
Suggest set to
1.5 ns delay
(1 ns and 2.6 ns)
Data to Egress
Clock Output
Default is No delay
0.0 ns
CMODE5[3:2] =10
Transmit 0.0 ns
Delay
Data to Egress
Clock Output Skew
(RGMII_RXC)
Bits [9:8] = 00
0.0 ns Delay
No Delay 0.0 ns Data to Ingress
Clock Input Default
is about 1.5 ns
delay
TABLE 6-3: TBI/RTBI INTERFACE PINS
Pin Name Pin Number Type Description
PMARXCLK0, RXC B5 O PMA Receiver Clock 0 Output – PMARXCLK0 for TBI mode
Receive Clock Output – RXC for RTBI modes
Receive data is sourced from the PHY synchronous to the rising edge
of PMARXCLK0 in TBI modes or RXC in RTBI mode. This clock is
recovered from the media.
TABLE 6-2: REFERENCE FOR RGMII STRAP PINS OR REGISTER CONFIGURATION
Case
Number
VSC8211
Strap Pins
CMODE5 Bits
VSC8211 RGMII
Data to
RXC and TXC
Output and Input
Delay/Skew
VSC8211 RGMII
Setting Control
Register 23 (17h)
VSC8211 RGMII
Clock Delay/Skew
Setting
Other End RGMII
Data to
RXC and TXC Out-
put and Input
Delay/Skew
Note 1: If other-end RGMII data to RXC output and data to TXC input delay is not 0.0 ns/0.2 ns (NO DELAY) as
default or the DELAY is not 1.5 ns/1.7 ns as default, then there is a need to set the strap pin CMODE5 or
the register 23 bits [11:8] to other values to meet the minimum 1.0 ns and maximum 2.6 ns specification in
RGMII V2.0 for both VSC8211 and other-end RGMII data to clock input/output delay/skew.

 2022 Microchip Technology Inc. and its subsidiaries DS00004531A-page 19
VSC8211
RX [9],
RD [9],
RD [4]
A4 O Receive Data Code Group, bit [9] (TBI mode)
Bit [9] of 10-bit parallel receive code-group data. When code groups
are properly aligned, any received code group containing a comma is
clocked by the rising edge of PMARXCLK1.
Multiplexed Receive Data Nibbles (RTBI mode)
The MAC synchronously inputs Bit [4] on the rising edge of RXC, and
bit [9] (MSB) on the falling edge of RXC.
RD [8:5],
RD [3:0],
RX [3:0]
A7, B7, A6,
B6
ORD [8:5] – RTBI data output. Use the falling edge of RXC.
RD [3:0] – RTBI data output. Use the rising edge of RXC.
RX [3:0] – TBI data output. Use the rising edge of PMARXCLK1.
RX [7:4] A9, B9, A8,
B8
OReceive Data Code Group (TBI mode)
Receive data is driven out of the device synchronously to the rising
edge of PMARXCLK1.
RX [8] A5 O Receive Data Code Group, bit [8] (TBI modes)
Bit [8] of 10-bit parallel receive code-group data. When code groups
are properly aligned, any received code group containing a comma is
clocked by the rising edge of PMARXCLK1.
COMDET C4 O Comma Detect Output (TBI mode)
A high on this signal indicates that the code-group associated with
the current PMARXCLK1 contains a valid comma. In TBI mode, the
PHY detects and code-group-aligns to the comma+ bit sequence.
RXCLK125 B4 O Receiver Clock 125 MHz Output (TBI mode)
This signal behaves differently, depending on whether TBI Loopback
mode is enabled:
1) When TBI Loopback mode is enabled, RXCLK125 becomes one-
half the frequency of the GTXCLK input clock from the protocol
device (or MAC).
2) When no carrier is present on the media, this signal is the same as
the device’s free running output clock signal, CLKOUTMAC.
3) When a valid carrier is detected on the media, this output signal is
the recovered clock from the TBI’s data stream.
PMARXCLK1 A3 O PMA Receiver Clock 1 Output (TBI mode)
The protocol device (MAC) uses the rising edge of this 62.5 MHz
receive clock to latch even-numbered code groups on the received
PHY bit stream. PMARXCLK1 is 180o out-of-phase with PMARX-
CLK0. This clock may be stretched during code-group alignment and
is not shortened.
TABLE 6-3: TBI/RTBI INTERFACE PINS
Pin Name Pin Number Type Description

VSC8211
DS00004531A-page 20  2022 Microchip Technology Inc.and its subsidiaries
6.2.1 TBI INTERFACE
• The TBI interface supports the speeds of 1000 Mbps. TBI is used as an interface to a TBI-compatible MAC. The
devices are compliant with the TBI interface specification when VDDIOMAC is operating at 3.3 V. The devices
can also support the TBI interface at 2.5 V.
• The TBI interface contains two distinct groups of signals—one for transmission and one for receiving. The
VSC8211 TBI and GMAC TBI connections are shown in Figure 6-4. Refer to Table 6-3 with detailed pin descrip-
tions for the TBI interface.
PMATXCLK,
TXC
A2 I PMA Transmit Code Group Clock Input (TBI mode)
125 MHz transmit code-group clock PMATXCLK. This code-group
clock is used to latch data into the PMA (in this case, the PHY) for
transmission.
Transmit Clock Input (RTBI mode)
The transmit clock TXC shall be either a 125 MHz or 25 MHz (for
1000 Mb or 100 Mb modes, respectively), with a +/–50 ppm toler-
ance.
TX [9],
TD [9],
TD [4]
B3 I Transmit Data Input (TBI mode)
Transmit code-group data bit 9 TX [9] is input on this pin synchro-
nously to the rising edge of PMATXCLK in TBI mode.
Multiplexed Transmit Data Input (RTBI mode)
Bit [4] TD [4] is synchronously input on the rising edge of TXC, and bit
[9] TD [9] on the falling edge of TXC.
TX [3:0],
TD [8:5],
TD [3:0]
C1, C2, B1,
B2
ITransmit Data Inputs (TBI mode)
Transmit code-group data is input on these pins TX [3:0] synchro-
nously to the rising edge of PMATXCLK in TBI mode.
Multiplexed Transmit Data Nibbles (RTBI mode)
Bits [3:0] TD [3:0] are synchronously input on the rising edge of TXC,
and bits [8:5] TD [8:5] on the falling edge of TXC.
TX [7:4] E1, E2, D1,
D2
ITransmit Data Inputs (TBI mode)
Transmit code-group data is input on these pins TX [7:4] synchro-
nously to the rising edge of PMATXCLK in TBI mode.
TX [8] A1 I Transmit Data Input (TBI mode)
Transmit code-group data bit 8 is input on this pin TX [8] synchro-
nously to the rising edge of PMATXCLK in TBI mode.
TABLE 6-3: TBI/RTBI INTERFACE PINS
Pin Name Pin Number Type Description