Microchip Technology TB3287 Reference manual

TB3287
Getting Started with Multi-Voltage I/O (MVIO)
Introduction
Authors: Johan Vaarlid, Microchip Technology Inc.
The AVR® DB Family of microcontrollers is equipped with a configurable integrated level shifter. The Multi-Voltage I/O
(MVIO) feature allows a subset of the I/O pins to be powered by a different I/O voltage domain VDDIO2. The rest of
the I/O pins runs on VDD. Both VDD and VDDIO2 have the same voltage range. Consult the Electrical
Characteristics section of the data sheet for the exact voltage range. This eliminates the need of having external level
shifters for communication or control of external components running on a different voltage level. Eliminating external
logic level shifters will, in turn, reduce the BOM and free up PCB real estate.
Figure 1. Multi-Voltage I/O can Completely Replace External Logic Level Converters
VDD
1.8-5.5V
VDD VDD VDDIO2
GND GND GND
GNDGND
VDDIO2
1.8-5.5V
Microcontroller
Logic
Level
Converter
Sensor
MVIO
Sensor
Sensor
Sensor
This technical brief describes how the Multi-Voltage I/O feature works on the AVR DB Family of microcontrollers. It
covers the following use cases:
•Polling VDDIO2 Status:
Checking if the VDDIO2 voltage is within the acceptable range by reading the Status bit.
•Interrupt on VDDIO2 Status:
Make use of the interrupt that occurs when the Status bit changes state.
•Measuring VDDIO2:
© 2020 Microchip Technology Inc. Technical Brief DS90003287A-page 1

Use the internal ADC to measure the VDDIO2 voltage.
•Blink a 3V LED with VDD at 1.8V:
A basic example of MVIO blinking an LED with a forward voltage higher than VDD.
Note: The code examples were developed on AVR128DB48 Curiosity Nano (EV35L43A), and are available on
GitHub.
TB3287
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Table of Contents
Introduction.....................................................................................................................................................1
1. Relevant Devices.................................................................................................................................... 4
2. Overview................................................................................................................................................. 5
3. Hardware Configuration.......................................................................................................................... 7
3.1. Using the Curiosity Nano AVR128DB48...................................................................................... 7
3.2. Supplying Power To VDDIO2....................................................................................................... 7
4. Reading the Status Bit............................................................................................................................ 9
5. Interrupt on VDDIO2 Status ................................................................................................................. 10
6. Measuring VDDIO2............................................................................................................................... 11
7. Blinking a 3V LED with VDD at 1.8V.....................................................................................................15
8. References............................................................................................................................................17
9. Revision History.................................................................................................................................... 18
10. Appendix............................................................................................................................................... 19
The Microchip Website.................................................................................................................................22
Product Change Notification Service............................................................................................................22
Customer Support........................................................................................................................................ 22
Microchip Devices Code Protection Feature................................................................................................ 22
Legal Notice................................................................................................................................................. 23
Trademarks.................................................................................................................................................. 23
Quality Management System....................................................................................................................... 24
Worldwide Sales and Service.......................................................................................................................25
TB3287
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1. Relevant Devices
This section lists the relevant devices for this document. The following figures show the different family devices,
laying out pin count variants and memory sizes:
• Vertical migration upwards is possible without code modification, as these devices are pin-compatible and
provide the same or more features
• Horizontal migration to the left reduces the pin count and, therefore, the available features
• Devices with different Flash memory sizes typically also have different SRAM and EEPROM
Figure 1-1. AVR® DB Family Overview
Pins
Flash
AVR64DB28
AVR128DB28
AVR32DB28
AVR128DB32 AVR128DB48 AVR128DB64
AVR64DB32 AVR64DB48 AVR64DB64
AVR32DB32 AVR32DB48
28 48 64
32
32 KB
64 KB
128 KB
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Relevant Devices
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2. Overview
The MVIO pins, located on PORTC, are powered by a separate VDDIO2 pin while the rest are powered by VDD. This
allows for additional power domain at a different voltage level within the limits of the Electrical Characteristics of each
device.
Figure 2-1. 48-Pin VQFN/TQFP Pinout Diagram
1
2
3
4
44 43
42
41 40
39 38
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24 23
37
36
35
34
12
13 14
15 16
17 18
19
20 21
22
45
46
47 48
GND VDD
PA5
PA6
PA7
PD2 PD3
PD6
PD7
PB0
PD0 PD1
PA2 PA3
PB1
PB2
PB3
PE1
PE2
PE0
PE3
PF0 (XTAL32K1)
PF1 (XTAL32K2)
PA1 (XTALHF2)
PA0 (XTALHF1)
PD5
PA4
PF2
PC0
PC1
PC4 PC5
PC3
PC2
PC6 PC7
PF3
PF4
UPDI
PF5
PF6
VDDIO2
PB4
PB5
GND
GND
AVDD
PD4
Power
Power Supply
Ground
Pin on AVDD Power Domain
Functionality
Programming/Debug
Clock/Crystal
Analog Function
Digital Function OnlyPin on VDD Power Domain
Pin on VDDIO2 Power Domain
These pins are capable of the same digital behavior as regular I/O pins, for example GPIO, serial communication
(USART, SPI, I2C), or connected to PWM peripherals. The input Schmitt Trigger levels are scaled according to the
VDDIO2 voltage, as described in the Electrical Characteristics section of the data sheet.
A configuration fuse determines the MVIO supply mode. The loss or gain of power on VDDIO2 is signaled by a status
register bit. This status bit has corresponding interrupt and event functionality.
A divided-down VDDIO2 voltage is available as input to the ADC.
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Overview
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Figure 2-2. MVIO Block Diagram
VDDIO
VDDIO2
VDD
PORTx[7:0]
PORTy[7:0]
VDDIO2
PORT
VDDIO2S VDDIO2F
Enable
(Int Req.)
ADC Input
Edge Detector
Voltage Divider
Voltage
Monitor
Voltage
Monitor
VDDCORE
VDDCORE
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Overview
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3. Hardware Configuration
3.1 Using the Curiosity Nano AVR128DB48
To illustrate the capabilities of Multi-Voltage I/O an AVR128DB48 Curiosity Nano is used. Schematics of the Curiosity
Nano PCB can be found in the References section. To enable MVIO on this development board, perform the below
steps:
1. Remove the resistor right below the VDDIO2 label to disconnect VDDIO2 from VDD. This is resistor R204 in
Figure 3-2.
2. Connect VDDIO2 + to 3.3V of a second power voltage source.
3. Connect VDDIO2 - to GND of a second voltage source.
Refer to the AVR123DB48 Curiosity Nano User Guide for a guide on how to reverse this process.
Any voltage between 1.8V and 5.5V may be applied to VDDIO2, but for the following examples, we will run at 3.3V.
Figure 3-1. AVR128DB48 Curiosity Nano MVIO
123
Figure 3-2. Snippet From the AVR128DB48 Curiosity Nano Schematic
3.2 Supplying Power To VDDIO2
The Multi-Voltage I/O (MVIO) can be configured in one of two supply modes:
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Hardware Configuration
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• Single-Supply mode, where the MVIO-capable I/O pins are powered at the same voltage level as the non-MVIO
capable pins, i.e., VDD. The user must connect the VDDIO2 pin(s) to the VDD pin(s).
• Dual-Supply mode, where the MVIO-capable I/O pins are supplied by the VDDIO2 voltage, which may be
different from the voltage supplied to the VDD pin(s)
Figure 3-3. FUSE.SYSCFG1 - Enabling Dual Supply Mode
8.8.2.5 System Configuration 1
Name: SYSCFG1
Offset: 0x06
Default: 0x08
Property: -
The default value given in this fuse description is the factory-programmed value, and should not be mistaken for the
Reset value.
Bit 7 6 5 4 3 2 1 0
SUT[2:0]
Access R R R R R
Default 0 1 0 0 0
Bits 4:3 – MVSYSCFG[1:0]
This bit field controls the power supply mode.
Value Name Description
0x00 Reserved -
0x02 SINGLE Device used in a single supply configuration.
0x03 Reserved -
MVSYSCFG[1:0]
Device used in a dual supply configuration.DUAL
0x01
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Hardware Configuration
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4. Reading the Status Bit
Before using the MVIO feature, it is recommended to check the VDDIO2 Status (VDDIO2S) bit in the MVIO.STATUS
(Status) register, to make sure that the voltage level of VDDIO2 is within the acceptable range of operation. If this bit
is ‘1’, then VDDIO2 is within the acceptable range of operation.
Figure 4-1. MVIO.STATUS - Reading the Status bit
Bit 7 6 5 4 3 2 1 0
Access R
Reset 0
Bit 0 – VDDIO2S VDDIO2 Status
This bit shows the state of the VDDIO2 voltage level.
Writing to this bit has no effect.
Value Description
0The VDDIO2 supply voltage is below the acceptable range for operation. The MVIO pins are tri-stated.
VDDIO2S
The VDDIO2 supply voltage is within the acceptable range for operation. The MVIO pin configurations
are loaded from the corresponding PORT registers.
1
//Polling the VDDIO2S bit
if(MVIO.STATUS & MVIO_VDDIO2S_bm)
{
//Do something if VDDIO2 is within acceptable range.
}
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Reading the Status Bit
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5. Interrupt on VDDIO2 Status
When the state of the VDDIO2 Status bit changes, the VDDIO2 interrupt flag will be raised. To be able to catch this
interrupt immediately, it is necessary to enable both the VDDIO2 interrupt and global interrupts in general.
Figure 5-1. MVIO.INTCTRL - Enable the VDDIO2 Interrupt
Bit 7 6 5 4 3 2 1 0
Access R/W
Reset 0
Bit 0 – VDDIO2IE VDDIO2 Interrupt Enable
This bit controls whether the interrupt for a VDDIO2 state change is enabled or not.
Value Description
0The VDDIO2 interrupt is disabled
VDDIO2IE
The VDDIO2 interrupt is enabled
1
/*Enable the VDDIO2 interrupt*/
MVIO.INTCTRL |= MVIO_VDDIO2IE_bm;
/*Enable Global interrupts*/
sei();
The MVIO vector will be called when the interrupt is triggered. Before returning from the Interrupt Service Routine
(ISR), the VDDIO2 (VDDIO2IF) interrupt flag in the MVIO Interrupt Flags (MVIO.INTFLAGS) register must be cleared.
This is done by writing a ‘1’ to the flag.
Figure 5-2. MVIO.INTFLAGS - Clear VDDIO2 Interrupt Flag
Bit 7 6 5 4 3 2 1 0
Access R/W
Reset 0
Bit 0 – VDDIO2IF VDDIO2 Interrupt Flag
This flag is cleared by writing a ‘1’ to it.
This flag is set when the VDDIO2 Status (VDDIO2S) bit in MVIO.STATUS changes value.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the VDDIO2 Interrupt Flag.
VDDIO2IF
ISR(MVIO_MVIO_vect)
{
/* The VDDIO2 interrupt has been triggered */
LED0_toggle();
/* Clear the CFD interrupt flag */
MVIO.INTFLAGS |= MVIO_VDDIO2IF_bm;
}
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Interrupt on VDDIO2 Status
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