Microgate SyncLink GT2 Instructions for use

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SyncLinkGT2/GT4SerialAdapter
HardwareUser’sManual
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MicroGateSystems,Ltd
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http://www.microgate.com
MicroGate®andSyncLink®areregisteredtrademarksofMicroGateSystems,Ltd.
Copyright©2008‐2012MicroGateSystems,Ltd.AllRightsReserved
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Contents
Overview.......................................................................................................................................................3
Features....................................................................................................................................................3
Specifications............................................................................................................................................3
Y‐Cables.........................................................................................................................................................4
SignalSpecifications......................................................................................................................................5
SingleEndedSignals(RS‐232/V.28)..........................................................................................................5
DifferentialSignals(RS‐422/RS‐485/V.11)................................................................................................5
ClockPolarity............................................................................................................................................5
SerialInterfaceSelection..............................................................................................................................7
DifferentialInputTermination......................................................................................................................8
DifferentialFail‐SafeBiasing.........................................................................................................................9
SerialConnectorPinAssignments..............................................................................................................10
RS‐232.....................................................................................................................................................11
V.35.........................................................................................................................................................12
RS‐422/RS‐449/RS‐485/RS‐530...............................................................................................................13
X.21.........................................................................................................................................................15
GeneralPurposeI/OSignals.......................................................................................................................16
DCGPIOSpecifications............................................................................................................................16
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Overview
TheSyncLinkGT2andGT4SerialAdaptersareadd‐incardsforuseinsystemswithaPCIexpansionslot.
Thecardsprovidetwo(GT2)orfour(GT4)serialportsforusebythesystem.Avarietyofserialprotocols
andinterfacestandardsaresupported.Refertothesoftwaredocumentationincludedwiththecardfor
detailsonusingthecardforaspecificapplication.
Features
•MaximumSpeeds
10Mbpssynchronous
1.8432Mbpsasynchronouswithstandardoscillator(14.7456MHz)
4Mbpsasynchronouswithcustomoscillator(32MHz)
•SDLC,HDLC,BISYNC,MONOSYNC,ASYNC,rawbit‐synchronousprotocols
•SelectablehardwareCRC:CRC‐16,CRC‐32,None
•DPLLClockRecovery(x8andx16sampling)
•ClockGeneration
•Configurabletransmitpreambleandidlepatterns
•Encoding:NRZ,NRZB,NRZ‐L,NRZI,NRZ‐M,NRZ‐S,FM0,FM1,Manchester,differentialbiphaselevel
•SelectableinterfaceforRS‐232,V.35,RS‐422/485,RS‐530,RS‐449,X.21
•Optionalterminationfordifferentialinputs
•Optionalfailsafebiasingfordifferentialinputs
•Fullsetofcontrolandstatussignals(DTR,DSR,RTS,CTS,DCD,RI,LL,RL)
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Specifications
•MicroGateFPGAserialcontroller(2or4ports)
•PCI3.0(compatiblewith5V,3.3V,andPCI‐Xslots)
•BusMasterDMAdatatransfer
•OperatingTemperature:0Cto60Cstandard,‐40Cto+85Coptional
•StorageTemperature:‐55Cto+125C
•Environmental:humidity0to95%non‐condensing;alt.‐200to+20,000ft
•Mechanical:StandardPCIshortcard;length6.875",height4.2",Weight5.5Oz
•Powerusage:300mA5V,80mA+12V,80mA‐12V
•Regulatory:FCCClassB,CE,ANSIC63.4ClassB,VCCIClassB,EN55022ClassB,EN55024,RoHS
•Connectors:DB‐25(male)
•CableOptions:DB‐25(female)toDB‐25(male);DB‐25(female)to34‐pinV.35(male);DB‐25
(female)to37‐pinRS‐449(male);DB‐25(female)to15‐pinX.21(male)
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YCables
Thecardhastwo60‐pinconnectors,eachcarryingtwoports.Y‐cablesareincludedwiththecardto
converteach60‐pinconnectorintotwostandardDB‐25maleconnectors.TheGT2cardusesone60‐pin
connectorandincludesasingleY‐cableforatotalof2ports.TheGT4cardusesboth60‐pinconnectors
andincludestwoY‐cablesforatotalof4ports.EachbranchofaY‐cableislabeledwithaportnumber.
TheY‐cablelabeled1and2shouldbeinstalledonthe60‐pinconnectorclosesttothePCIedge
connector(goldfingers).TheY‐cablelabeled3and4shouldbeinstalledonthe60‐pinconnector
farthestfromthePCIedgeconnector.
includedwiththecardto
converteach60‐pinconnectorintotwostandardDB‐25maleconnectors.TheGT2cardusesone60‐pin
connectorandincludesasingleY‐cableforatotalof2ports.TheGT4cardusesboth60‐pinconnectors
andincludestwoY‐cablesforatotalof4ports.EachbranchofaY‐cableislabeledwithaportnumber.
TheY‐cablelabeled1and2shouldbeinstalledonthe60‐pinconnectorclosesttothePCIedge
connector(goldfingers).TheY‐cablelabeled3and4shouldbeinstalledonthe60‐pinconnector
farthestfromthePCIedgeconnector.
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Note:TheserialcontrollerontheGT2hasonlytwoports.AddingaY‐cabletothesecond60‐pin
connectorofaGT2cardwillnotaddports3and4.
Note:TheserialcontrollerontheGT2hasonlytwoports.AddingaY‐cabletothesecond60‐pin
connectorofaGT2cardwillnotaddports3and4.
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Figure1 Y‐CablesandPortNumbering
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SignalSpecifications
Eachserialsignal(control,status,data,orclock)iscompatiblewithanelectricalspecificationthatis
selectedbyplacementofjumpersonthecard.Thissectionbrieflydescribesthespecificationssupported
bythecard.
SingleEndedSignals(RS232/V.28)
SingleendedsignalssupportedbythecardarecompatiblewithbothRS‐232andITUV.28standards.
Eachsingleendedsignalusesoneconductorinacable,andallsingleendedsignalsshareacommon
groundconductor.
•MaximumVoltageRange:+15to‐15V(betweensignalandground)
•+3Vto+15V(+5Vtypical)=control/statussignalonordatavalueof0
•‐3Vto‐15V(‐5Vtypical)=control/statussignaloffordatavalueof1
•Voltagebetween‐3Vto+3V=invalid(indeterminate)state
•Maxcablelength50feet
•Maxdatarate20kbps
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Themaximumdatarateof20kbpsispartoftheRS‐232/V.28standards.TheSyncLinkcardcanoperate
atspeedsupto120kbpsdependingonthecablelengthandloading.Longercablesandincreased
loadingreducesthemaximumsupporteddatarate.
DifferentialSignals(RS422/RS485/V.11)
DifferentialsignalssupportedbythecardarecompatiblewithRS‐422,RS‐485andITUV.11standards.
Eachdifferentialsignalusestwoconductorsinacable(signalpair).Acommongroundconductoris
recommendedforusewithdifferentialsignalstoreducecommonmodevoltagesbetweencableends
whichmayresultinincorrectorimpairedoperation.
•MaximumVoltageRange:+5to‐5V(betweenconductorsinapair)
•+200mVto+5V(+2Vtypical)=control/statussignalonordatavalueof0
•‐200mVto‐5V(‐2Vtypical)=control/statussignaloffordatavalueof1
•Voltagebetween‐200mVto+200mVinvalid(indeterminate)state
•Maxcablelength4000feet
•Maxdatarate10Mbps
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Longercablesandincreasedloadingreducesthemaximumsupporteddatarate.
ClockPolarity
Synchronousserialcommunications(HDLC/Bisync/Monosync)mayuseseparateclocksignalstocontrol
thetimingofdatasignals.Oneclockcycleequalsonebit.Therearetwoclockedges(risingandfalling)
foreachclockcycle.Ononeedge,thetransmitdataoutputchanges.Ontheotheredge,thereceive
datainputissampled.Theassignmentofclockedgestotransmitdatatransitionandreceivedata
samplingisreferredtoasclockpolarity.

TheSyncLinkcardusestheclockpolarityintheRS‐232/RS‐422/V.24/V.28/V.11standardsasdescribed
below:
RS‐232/V.28SingleEndedSignals
•+3Vto+15V(+5Vtypical)=clockon
•‐3Vto‐15V(‐5Vtypical)=clockoff
•OntoOffedge(fallingedge)=receivedatasample(bitcenter)
•OfftoOnedge(risingedge)=transmitdatatransition(bitedge)
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RS‐422/RS‐485/V.11DifferentialSignals
•+200mVto+5V(+2Vtypical)=clockon
•‐200mVto‐5V(‐2Vtypical)=clockoff
•OntoOffedge(fallingedge)=receivedatasample(bitcenter)
•OfftoOnedge(risingedge)=transmitdatatransition(bitedge)
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Mostserialcommunicationsequipmentusestheaboveclockpolarity,butsomenon‐standard
equipmentmayusetheoppositepolarity.Fordifferentialsignals,thepolaritycanbealteredbyinverting
theconductorsofeachclocksignalpair.
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SerialInterfaceSelection
Theserialadaptersupportsdifferentinterfacetypeswhichareselectedbyplacementofjumpersonthe
card.Eachporthasthreerowsofheaders(pinsstickingupfromthecard).Eachrowislabeledwitha
portnumberandaninterfacetype(RS‐232,V.35,RS‐422/485).Placejumpersontheheaderrowlabeled
withthedesiredinterfacetype.Theinterfacetypemustmatchthatoftheconnectedcommunications
equipment.
Interfaceselectionispresetatthefactoryasspecifiedbytheorderingcode.Theselectionmaybe
changedbymovingthejumperstothedesiredheaderrowasdescribedabove.Useplierstoremovethe
jumpersfromthecurrentposition,carefullyworkingthejumpersloosefromtheheaders.Takecareto
notdamagethecardorcauseinjury.
Someinterfacetypesrequireaconversioncableinadditiontoaspecificjumpersettingtoprovidethe
necessaryconnectortype.RefertotheSerialPinAssignmentssectionformoredetails.
Figure2InterfaceSelectionJumpers
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DifferentialInputTermination
EachportonthecardhasoptionalterminationofRS‐422/485differentialinputs.Whenaresistorpackis
installedinthesocketlabeled‘TERM’,alldifferentialinputsforthatportareterminatedwith120ohms.
Bydefaulttheterminationresistorpackisinstalledforallports.Thepresenceoftheterminationresistor
packdoesnotaffectsingleended(RS‐232/V.28)inputs.
Terminationisusedtoincreasesignalreliabilityathighspeeds(generally1Mbpsormore).Athigh
speeds,receiversateachendofacableshouldbeterminated.Foramulti‐dropsetups(morethan2
devicesonacable),donotterminatereceiversconnectedtothemiddleofthecable.Atslowerspeeds,
theterminationcanusuallyremainwithoutproblem.Removingterminationatslowerspeedsmayallow
theuseoflongercables.
Toremoveaterminationresistorpack,identifythesocketlabeled‘TERM’.Thenremovetheyellow
resistorpackfromtheblacksocketusingaflatheadscrewdriverorequivalenttool.Terminationcanbe
reinstalledbypressingtheresistorpackbackintothesocket.Takecarethatthepinsontheresistorpack
arenotbentandarefirmlyseatedintothesocket.
Figure3TerminationSockets
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DifferentialFailSafeBiasing
Fail‐safebiasingisatechniquethatguaranteesdifferentialinputsignalsareinasteadystatewhennot
connectedtoanactivedifferentialoutput.Optionalfail‐safebiasingofalldifferentialinputs(RS‐422/RS‐
485/V.11)foraportisavailablebyinstallingaresistorpackinthesocketlabeled‘FAILSAFE’.Thisresistor
packisnotincludedbydefaultwiththehardware.ContactMicroGatesalestorequestfail‐saferesistor
packswhenorderingthehardware.
Fail‐safebiasingisonlyusedwhenaninputisnotconstantlydrivenbyanoutput,andthatinputis
terminated(seeprevioussectionondifferentialinputtermination).Whenaninputisnotterminated,
fail‐safebiasingintegraltoeachreceivercircuitmaintainstheinputinasteadystate.Whenaninputis
terminated,externalfail‐safebiasing(resistorpack)mayberequiredtoguaranteetheinputisina
steadystate.
Anexampleapplicationthatusesfail‐safebiasingisbusmodeconnectionswhereasinglecable
conductorpairisconnectedtoboththetransmitdataoutputandreceivedatainputformorethanone
station.Inthissetup,onlyoneoutputmaybeactiveatthesametimeandeachoutputisonlydriven
whensendingdata.Whennostationissending,theexternalfail‐safebiasingmaintainsavoltageonthe
cablepairthatkeepsinputsinasteadystate.
WARNING:Fail‐safebiasingmustbepresentononlyasinglestationconnectedtoacablepair.This
singlestationmaintainsthevoltageonthecabletokeepallconnectedinputsinasteadystate.Applying
fail‐safebiasingatmultiplepointsonacablemayresultinincorrectoperation.
Figure4FailSafeBiasingSockets
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SerialConnectorPinAssignments
TheserialconnectorsontheendofeachbanchoftheY‐cableareDB‐25(25pins)maleconnectors.The
assignmentofsignalstotheconnectorpinsiscontrolledbytheinterfaceselectionjumpersonthecard.
ForinterfacetypesthatuseaconnectordifferentthanDB‐25anadaptercablepurchasedfrom
MicroGateisrequired.Thefollowingsectionsdescribethejumpersettingsandcablesforeach
supportedstandard.
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