SDA 6000 PRELIMINARY DATA SHEET
Version 2.1
B-1 Micronas
Figure 1-1 M2 Tool Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 5
Figure 1-2 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 9
Figure 2-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 3
Figure 3-1 M2 Top Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 3
Figure 4-1 M2 Memory Path Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 6
Figure 4-2 Storage of Words, Byte and Bits in a Byte Organized Memory . . . . 4 - 7
Figure 4-3 Internal RAM Areas and SFR Areas . . . . . . . . . . . . . . . . . . . . . . . . 4 - 8
Figure 4-4 Location of the PEC Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 11
Figure 4-5 External Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 14
Figure 4-6 Interlocked Access Cycles to ROM and SDRAM. . . . . . . . . . . . . . 4 - 15
Figure 4-7 Interlocked Access Cycles to two SDRAM Banks . . . . . . . . . . . . . 4 - 16
Figure 4-8 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 17
Figure 4-9 Four-Phase Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 21
Figure 4-10 CPU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 25
Figure 4-11 Sequential Instruction Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 28
Figure 4-12 Standard Branch Instruction Pipelining . . . . . . . . . . . . . . . . . . . . . 4 - 28
Figure 4-13 Cache Jump Instruction Pipelining. . . . . . . . . . . . . . . . . . . . . . . . . 4 - 29
Figure 4-14 Addressing via the Code Segment Pointer . . . . . . . . . . . . . . . . . . 4 - 42
Figure 4-15 Addressing via the Data Page Pointers . . . . . . . . . . . . . . . . . . . . . 4 - 44
Figure 4-16 Register Bank Selection via Register CP. . . . . . . . . . . . . . . . . . . . 4 - 45
Figure 4-17 Implicit CP Use by Short GPR Addressing Modes . . . . . . . . . . . . 4 - 46
Figure 5-1 Priority Levels and PEC Channels. . . . . . . . . . . . . . . . . . . . . . . . . 5 - 10
Figure 5-2 Mapping of PEC Offset Pointers into the Internal RAM . . . . . . . . . 5 - 19
Figure 5-3 Task Status Saved on the System Stack . . . . . . . . . . . . . . . . . . . . 5 - 22
Figure 5-4 Pipeline Diagram for Interrupt Response Time . . . . . . . . . . . . . . . 5 - 23
Figure 5-5 Pipeline Diagram for PEC Response Time . . . . . . . . . . . . . . . . . . 5 - 26
Figure 6-1 State Machine for Security Level Switching . . . . . . . . . . . . . . . . . . 6 - 11
Figure 6-2 Transitions between Idle Mode and Active Mode . . . . . . . . . . . . . 6 - 14
Figure 6-3 WDT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 18
Figure 6-4 Bootstrap Loader Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 22
Figure 6-5 Portlogic Register Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 27
Figure 7-1 Structure of Timer Block 1 Core Timer T3 . . . . . . . . . . . . . . . . . . . . 7 - 4
Figure 7-2 Block Diagram of Core Timer T3 in Timer Mode . . . . . . . . . . . . . . . 7 - 7
Figure 7-3 Block Diagram of Core Timer T3 in Gated Timer Mode. . . . . . . . . . 7 - 7
Figure 7-4 Block Diagram of Core Timer T3 in Counter Mode . . . . . . . . . . . . . 7 - 8
Figure 7-5 Block Diagram of Core Timer T3 in Incremental Interface Mode. . . 7 - 9
Figure 7-6 Interfacing the Encoder to the Microcontroller . . . . . . . . . . . . . . . . 7 - 10
Figure 7-7 Evaluation of the Incremental Encoder Signals . . . . . . . . . . . . . . . 7 - 11
Figure 7-8 Evaluation of the Incremental Encoder Signals . . . . . . . . . . . . . . . 7 - 12
Figure 7-9 Block Diagram of an Auxiliary Timer in Counter Mode . . . . . . . . . 7 - 13
Figure 7-10 Concatenation of Core Timer T3 and an Auxiliary Timer. . . . . . . . 7 - 15
Figure 7-11 GPT1 Auxiliary Timer in Reload Mode. . . . . . . . . . . . . . . . . . . . . . 7 - 16
Figure 7-12 GPT1 Timer Reload Configuration for PWM Generation . . . . . . . . 7 - 17
