Microsemi VSC8502 User manual

VSC8502
User Guide
VSC8502 Evaluation Board
January 2019

VSC8502 Evaluation Board
VPPD-03741 VSC8502 User Guide Revision 1.1
Contents
1 Revision History ............................................................................................................................. 1
1.1 Revision 1.1 ........................................................................................................................................ 1
1.2 Revision 1.0 ........................................................................................................................................ 1
2 Introduction ................................................................................................................................... 2
3 General Description ....................................................................................................................... 4
3.1 Key Features ....................................................................................................................................... 4
3.1.1 Copper Port RJ45 Connections ................................................................................................................ 4
3.1.2 External RefClk Option ............................................................................................................................ 6
3.1.3 Recovered Clocks .................................................................................................................................... 6
3.1.4 GMII loopback card ................................................................................................................................. 7
3.2 Key Features ....................................................................................................................................... 7
3.2.1 Single 3.3 V Input for Both DUT and Other Components ........................................................................ 8
3.2.2 DUT On-chip Regulator Power ................................................................................................................ 8
4 Quick Start ..................................................................................................................................... 9
4.1 Connecting the Power Supply ............................................................................................................ 9
4.2 PC Software Installation ..................................................................................................................... 9
4.3 Connecting to the Board to the PC ..................................................................................................... 9
4.3.1 Board Initialization ................................................................................................................................ 10
4.3.2 Copper Media Operation (Auto-negotiation Enabled) .......................................................................... 10
4.3.3 Driving Recovered Clock Output ........................................................................................................... 11
4.4 Useful Test Features ......................................................................................................................... 11
4.4.1 Ethernet Packet Generator ................................................................................................................... 11
4.4.2 Copper PHY Error Counters ................................................................................................................... 11
4.4.3 Near-End Loopback ............................................................................................................................... 11
4.4.4 Far-End Loopback .................................................................................................................................. 12

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1 Revision History
The revision history describes the changes that were implemented in this document. The changes are
listed by revision, starting with the most current publication.
1.1 Revision 1.1
Revision 1.1 of this datasheet was published in January 2019. The new Microchip template was added to
the document.
1.2 Revision 1.0
Revision 1.0 of this datasheet was published in May 2014. This was the first publication of the
document.

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2 Introduction
The VSC8502 device is a low-power, cost-optimized, dual-port gigabit Ethernet PHY. It features
integrated, line-side termination to conserve board space, lower EMI, and improved system
performance. To further reduce system complexity, component count, and system cost, the VSC8502
device can operate from a single 3.3 V supply using integrated voltage regulators. Additionally,
integrated RGMII timing compensation eliminates the need for on-board delay lines. The device also
optimizes power consumption in all link operating speeds and features Wake-on-LAN (WOL) power
management using magic packets.
This document describes the architecture and usage of the VSC8502 Evaluation Board (VSC8502EV). The
Quick Start section describes how to install and run the graphical user interface (GUI) to fully control the
evaluation board.
Figure 1 • VSC8514 Evaluation Board (Top View)
The following illustration shows the bottom view of the VSC8502 evaluation board.

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Figure 2 • VSC8514 Evaluation Board (Bottom View)
Additional VSC8502 collateral for both the VSC8502 device and VSC8502EV, including schematics,
layout, GUI, and application notes can be found on the VSC8502 product
web page at: .https://www.vitesse.com/products/product.php?number=VSC8502

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3 General Description
The evaluation board, shown in Figure 1, provides the user a way to evaluate the VSC8502 device in
multiple configurations. Two RJ-45 connectors are provided for copper media interfaces. The MAC
interface is exposed via SAMTEC connector (J1) that allows for the complete eval board to be mated
with a motherboard having the necessary signals for operating the device.
For standalone access to all of the features of the device, an external microcontroller is used to
configure the VSC8502 via the MDIO bus. The GUI enables the user to read and write device registers.
3.1 Key Features
This section shows the key features for VSC8502.
3.1.1 Copper Port RJ45 Connections
PHY ports 0 and 1 use generic RJ45 connectors with discrete pulse H5008NL magnetics.
GMII MAC Connector
The parallel MAC interface is available through a Samtec connector J1. As described in section 2.1.7, it
can be configured with the companion daughtercard installed at J1 as
either single-port loopback or port-port traffic passing modes.
Switch Block Control
See Figure 3 for definition of SW1 controls.
See Figure 4 for the default settings.
Table 1 • DIP Switch 1 Options
DUT Control Signal DIP SW1 pos ’1’ = pull up to VDDMAC; pos ‘0’ = pull down to GND
REFCLK_SEL SW1.1 0=125 MHz (default); 1 =25 MHz
REGEN_10 SW1.2 0=OFF (default); 1= ON
REGEN_25 SW1.3 0=OFF (default); 1= ON
RESERVED3/CLK_SQUELCH_IN SW1.4 1=enabled(default); 0 = disabled
NRESET SW1.5 1=operational (default); 0=held in reset
COMA_MODE SW1.6 0=disabled (default); 1=enabled
The following image shows the SW1 switch control for the VSC8502EV.

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Figure 3 • SW1 Switch Control
The following table shows the DIP switch options for the VSC8502 evaluation board.
Table 2 • DIP Switch 2 Options
DUT Control Signal DIP SW1 pos ’1’ = pull up to VDDMAC; pos ‘0’ = pull down to GND
RCVRDCLK1/PHYADD1 SW1.1 0=default
RCVRDCLK2/PHYADD2 SW1.2 0=default
PHYADD3 SW1.3 0=default
PHYADD4 SW1.4 0=default
Note: R17 and R18 0 ohm options must be installed for PHYADD1 and PHYADD2 to be affected by SW2,
otherwise they are internally pulled to GND. Also, PHYADD3-4 pins
are internal PD on the VSC8502 IC, and are weakly pulled to GND when their corresponding SW2 pins
are kept in ‘0’ position.
Figure 4 • SW2 Switch Control

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3.1.2 External RefClk Option
The user may choose to provide an external PHY REFCLK via SMA connection to J8 (as shown in Figure
1). To route the SMA signal to the device the user must reorient the
zero ohm resistor R25, as shown from the PCB layout view in Figure 7.
Note: external PHY REFCLK must be connected via SMA to J8 if 3.3 V VDDIO/VDDMAC is used, since the
on-board crystal oscillator (U5) is a 2.5 V CMOS driver.
R25 can also be connected across pins 1 and 2 if a user wants to provide DUT REFCLK input from the
Samtec connector J1.
Figure 5 • REFCLK Input Options - R25 3-Way Orientation
3.1.3 Recovered Clocks
There are two recovered clocks available from the VSC8502, through SMA connections J5 (RCVRDCLK1)
and J6 (RCVRDCLK2). In the default configuration, CLK_SQUELCH_IN
is pulled down, which disables the clock squelching and RCVRDCLK1/RCVRDCLK2 are connected to the
Samtech header J1. To route RCVRDCLK1 and RCVRDCLK2 to SMAs
J5 and J6, reorient zero ohm resistors R21 and R23, respectively.
Software Interface Microcontroller Card
A Silabs F340 microcontroller is included to facilitate a software interface to the registers on the
VSC8502 through a USB port.
Note: Alternatively, a Rabbit card is available for an IP-based manager of the PHY register space,
installed in the keep-out area (U6) of the board’s top-side. Or, MDC
and MDIO can be accessed on stake header J10 if desired for another microcontroller to host the PHY
register space.

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3.1.4 GMII loopback card
The VSC8502EV ships with a daughter card that mounts to J1 to loop-back the GMII/RGMII interface.
As shown in Figure 8 and Figure 9 below, one orientation of the loopback card will loop each port back
to itself (IN-CHANNEL LOOPBACK in Figure 8). The other orientation
forwards bidirectional traffic from one port to the other (CHANNEL TO CHANNEL LOOPBACK).
Figure 6 • Loopback Card (Side A)
Figure 7 • Loopback Card (Side B)
Note: this daughter card loopback only supports 1000 BASE-T in GMII mode and 10/100/1000 in RGMII
mode. It will not support 10/100 in MII mode.
However, there are other internal loopback modes that will support BER testing of MII mode such as far-
end loopback (MII Register 23.3).
3.2 Key Features
This section shows the power supply options for VSC8502.

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3.2.1 Single 3.3 V Input for Both DUT and Other Components
This option allows for one external 3.3 V supply connected to J11 to power everything on the board. Use
the following steps:
SW1 REGEN1V0 = REGEN2V5 = 0: disable on-chip regulators
Insert a 3.3 V DC supply (rated for 1 Amp) into J11
Unplug banana connectors J16(+): J17(GND)
Unplug banana connectors J19(+): J20(GND)
Populate J23: 3V3_DUT = 3V3_MAIN
Populate J15: 2V5_DUT = 2V5
Populate J26: VDD25A = 2V5_DUT
Remove J18: on-board 3.3 V to 2.5 V regulator enabled
Populate J25: VDD1 = 1V0
Remove J12: on-board 3.3 V to 1.0 V regulator enabled
Populate J24: VDDMAC = 3V3_DUT or 2V5_DUT (VDDMAC is tied to VDDIO. The DUT’s VDDIO can
operate at either 2.5 V or 3.3 V)
Populate J9: VDDMDIO = VDDIO (1.2 V option is not available at this time, due to inability to drive
1.2 V from on-board microcontroller options)
DUT Power Rails Isolated from non-DUT Power
This option allows for the DUT power supplies to be isolated from the rest of the board power. Use the
following steps:
SW1 REGEN1V0 = REGEN2V5 = 0: disable on-chip regulators
Insert a 3.3 V DC supply (rated for 1 Amp) into J11
Populate banana jacks J13(+): J14(GND) with 3.3 V supply
Populate banana jacks J16(+): J17(GND) with 2.5 V supply
Populate banana jacks J19(+): J20(GND) with 1.0 V supply
Remove J23: 3V3_DUT = J13 (3.3 V)
Remove J15: 2V5_DUT = J16 (2.5 V)
Populate J26: VDD25A = 2V5_DUT
Remove J18: on-board 3.3 V to 2.5 V regulator enabled
Populate J25: VDD1 = 1V0 (note: 1V0 = J19)
Populate J12: on-board 3.3 V to 1.0 V regulator disabled
Populate J24: VDDMAC = 3V3_DUT or 2V5_DUT (VDDMAC is tied to VDDIO. The DUT’s VDDIO can
operate at either 2.5 V or 3.3 V)
Populate J9: VDDMDIO = VDDIO (1.2 V option is not available at this time, due to inability to drive
1.2 V from on-board microcontroller options)
3.2.2 DUT On-chip Regulator Power
The on-chip regulator option for this board is for engineering purposes only. There are performance
issues associated with using the on-chip regulator on this board, so it is
an unsupported board feature.