Midas RTE-V852-PC User manual

RTE-V852-PC
User’s Manual (Rev. 1.10)
Midas lab

RTE-V852-PC USER’S MANUAL (Rev. 1.10)
1
REVISION HISTORY
Date of
enforcement Revision Chapter Description
August 15, 1996 1.00 First issue
December 4, 1996 1.10 3.5
8
xx
Correction JPORT2 Pin Arrangement (P21,P21)
Correction INT- of JEXT Connector Signals
Correction INTP0(P24/INTP03) to INTP0(P22/INTP01)

RTE-V852-PC USER’S MANUAL (Rev. 1.10)
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CONTENTS
1. INTRODUCTION................................................................................................5
1.1. NUMERIC NOTATION................................................................................................. 5
2. FEATURES AND FUNCTIONS..........................................................................6
3. BOARD CONFIGURATION................................................................................7
3.1. RESET SWITCH [SOCKET BOARD] (RESET_SW).................................................... 7
3.2. RESET SWITCH [BASE BOARD] (SW_RESET)......................................................... 7
3.3. NMI SWITCH [SOCKET BOARD] (NMI_SW) .............................................................. 7
3.4. POWER SUPPLY CONNECTOR [SCOKET/BASE BOARD] (JPOWER)..................... 8
3.5. PROCESSOR PIN CONNECTORS [SOCKET BOARD] .............................................. 9
(JPORT0, JPORT1, JPORT2, JPORT3, JPORT10)............................................................... 9
3.6. PROCESSOR PIN CONNECTORS [SOCKET BOARD/BASE BOARD] (J1, J2/J5, J6)10
3.7. SERIAL CONNECTOR [SOCKET BOARD] (J3)..........................................................11
3.8. SWITCH 1 [SOCKET BOARD] (SW1) ....................................................................... 12
3.9. SWITCH 2 [SOCKET BOARD] (SW2) ....................................................................... 12
3.10. CRYSTAL SOCKET [SOCKET BOARD] (JP1)......................................................... 12
3.11. 7-SEGMENT LED [SOCKET BOARD] (LED_P1) ..................................................... 13
3.12. LEDS [SOCKET BOARD] ........................................................................................ 13
3.13. SWITCH 1 [BASE BOARD] (SW1) .......................................................................... 13
3.14. SWITCH 2 [BASE BOARD] (SW2) .......................................................................... 13
3.15. SWITCH 3 [BASE BOARD] (SW3) .......................................................................... 14
3.16. ROM CAPACITY SWITCHING JUMPER [BASE BOARD] (JP1).............................. 14
3.17. ISA BUS INTERFACE SWITCHING JUMPER [BASE BOARD] (JP2)...................... 14
3.18. LEDS [BASE BOARD] ............................................................................................. 14
3.19. TEST PINS FOR ROM EMULATION [BASE BOARD] (JROMEM)........................... 15
3.20. SERIAL CONNECTORS [BASE BOARD] (JSIO1, JSIO2)........................................ 16
3.21. PARALLEL CONNECTOR [BASE BOARD] (JPRT).................................................. 17
3.22. EXTENSION BUS CONNECTOR [BASE BOARD] (JEXT)....................................... 17
3.23. CLOCK SOCKET [BASE BOARD] (OSC1) .............................................................. 17
3.24. DRAM-SIMM SOCKETS.......................................................................................... 18
3.25. ROM SOCKETS ...................................................................................................... 18
4. INSTALLATION AND USE...............................................................................19
4.1. BOARD SETTING ..................................................................................................... 19
4.2. INSTALLATION ON THE ISA BUS............................................................................. 22
4.3. STANDALONE USE OF THE BOARD ....................................................................... 22

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5. HARDWARE REFERENCES ...........................................................................23
5.1 MEMORY MAP........................................................................................................... 23
6. SYSTEM-I/O.....................................................................................................25
6.1. SYSTEM-I/O LIST ..................................................................................................... 25
6.2. UART/PRINTER (TL16C552A) (3F-F000H TO 3F-F026H)......................................... 26
6.3. TIC (µPD71054) (3F-F030H TO 3F-F038H) ............................................................... 28
6.4. 7-SEGMENT LED DISPLAY DATA OUTPUT PORT (3F-F040H [Write Only]) ............ 29
6.5. DIPSW1 READ PORT (3F-F050H [READ ONLY]) ..................................................... 29
6.6. STATUS READ PORT (3F-F060H [READ ONLY])...................................................... 30
6.7. BIC (BUS INTERFACE CONTROL) (3F-F080H TO 3F-F0F0H) ................................. 31
6.8. NMI SELECT PORT (3F-F140H TO 3F-F150H)......................................................... 32
6.9. NMI STATUS PORT (3F-F160H TO 3F-F170H [READ ONLY]) .................................. 34
6.10. NMI/INT0/INT1 MASK PORT (3F-F180H)................................................................ 34
6.11. NMI/INT1 REQUEST CLEAR PORTS (3F-F190H, 3F-F1A0H [WRITE ONLY])........ 34
6.12. INT0(P22/INTP01) SELECT PORT (3F-F200H)....................................................... 35
6.13. INT1 (P24/INTP03) SELECT PORT (3F-F210H)...................................................... 35
6.14. INT0(P22/INTP01) STATUS PORT (3F-F220H [READ ONLY]) ................................ 35
6.15. INT1 (P24/INTP03) STATUS PORT (3F-F230H [READ ONLY]) ............................... 36
7. RECOMMENDED SETTINGS..........................................................................37
7.1. CPU SETTING........................................................................................................... 37
7.2. SRAM/ROM............................................................................................................... 37
7.3. DRAM........................................................................................................................ 37
7.4. SYSTEM-I/O WAIT COUNT....................................................................................... 37
7.5. SYSTEM-I/O COMMAND RECOVERY TIME............................................................. 37
8. JEXT BUS SPECIFICATION............................................................................39
9. OTHER CPU RESOURCES.............................................................................41
9.1. RESET- ..................................................................................................................... 41
9.2. NMI-........................................................................................................................... 41
9.3. MASKABLE INTERRUPTS (INT0(P22/INTP01), INT1 (P24/INTP03))........................ 43
9.4. PORT ........................................................................................................................ 44
10. Multi MONITOR .............................................................................................45
10.1. MONITOR WORK RAM........................................................................................... 45
10.2. INTERRUPTS.......................................................................................................... 45
10.3. _INIT_SP SETTING................................................................................................. 45
10.4. REMOTE CONNECTION......................................................................................... 45
10.5. TIMER INTERRUPT ................................................................................................ 45

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11. RTE COMMANDS..........................................................................................46
11.1. HELP (?).................................................................................................................. 46
11.2. INIT.......................................................................................................................... 46
11.3. VER ......................................................................................................................... 46
11.4. SFR ......................................................................................................................... 46
12. APPENDIX BUS CYCLE..............................................................................47
12.1. TIME-OVER READY................................................................................................ 47
12.2. DRAM INTERFACE ................................................................................................. 47
12.2.1. Outline........................................................................................................47
12.2.2. Signal Description......................................................................................47
12.2.3. Single Read (Normal Mode) ...................................................................... 48
12.2.4. Single Write (Normal Mode) ......................................................................49
12.2.5. Page Access (Page Mode, Same Row Address) ...................................... 50
12.2.6. Page Access (Page Mode, Different Row Addresses)..............................51
13. APPENDIX CPU PORT CONNECTIONS ....................................................52
13.1. P00 TO P07............................................................................................................. 52
13.2. P10 TO P17............................................................................................................. 52
13.3. P20 TO P27............................................................................................................. 52
13.4. P30 TO P37............................................................................................................. 53
13.5. P100 TO P103 ......................................................................................................... 53

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1. INTRODUCTION
This manual describes the RTE-V852-PC, which is an evaluation board for the V852, NEC’s CPU.
With the RTE-V852-PC, it is possible to develop and debug programs, and evaluate the CPU
performance, using the GreenHills Multi debugger. Communication with this debugger is carried out
using the IBM-PC/AT ISA bus or RS-232C serial interface. It is also possible to expand memory and
I/O units using local bus connectors provided on the evaluation board.
1.1. NUMERIC NOTATION
This manual represents numbers according to the notation described in the following table.
Hexadecimal and binary numbers are hyphenated at every four digits, if they are difficult to read
because of many digits being in each number.
Number Notation rule Example
Decimal number Only numerals are indicated. “10”represents number 10 in decimal.
Hexadecimal number A number is suffixed with letter H. “10H”represents number 16 in
decimal.
Binary number A number is suffixed with letter B. “10B”represents number 2 in decimal.
Number Notation Rules

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2. FEATURES AND FUNCTIONS
The overview of each function block of the RTE-V852-PC is shown below. The RTE-V852-PC
consists of the Socket board (smaller board) on which the CPU is mounted, and the Base board on
which other components and the Socket board are mounted.
V852
ISA Bus
Base Board
Local Bus
Socket Board
ISA BUS I/F
JEXT
CONNECTOR
OR
D-RAM
S-RAM
ROM
SIO/PRT
RS-232C
CONNECTOR
OR
TIMER
USER
HW
PARALLEL
CONNECTOR
OR
Internal
Control
OR
FPGA
RS-232C
CONNECTOR
OR
RTE-V852-PC Block Diagram
Features
•ROM: Standard 128 Kbytes (64K ×16-bit EPROM ×1)
Maximum 512 Kbytes (128K ×16-bit EPROM ×1)
•SRAM: 512 Kbytes (64K ×16-bit SRAM ×4)
•DRAM: 4, 8 or 16 Mbytes (standard 4 Mbytes) installed in one 72-pin SIMM socket
The EDO-type DRAM-SIMM can be used as well as the ordinary type DRAM-SIMM.
•RS-232C port (9-pin D-SUB connector ×1, 10-pin 2.54 mm pin header ×2)
•Parallel port (26-pin 2.54-mm pin header ×1)
•Communication function supported using the ISA bus of a PC/AT or compatible
•Local bus connector for user-installed expansion equipment
•Releases CPU ports for the connector.
•External reset switch provided on the rear panel
•Connection pins for ROM in-circuit debugger

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3. BOARD CONFIGURATION
The physical layout of the major components on the RTE-V852-PC board is shown below. This
chapter explains each component. To use the board with the Multi debugger, first read Chapter 4
before reading this chapter.
SW2
SIO/PRT SW_RESET
JPOWER
JEXT
JSIO1
PLD
PLD
SW1
ROM
RAM
NMI-
GND
TIMER
RESET-
JPRT
JSIO2
J5
J6
JROMEM
OSC1
1pin
JP1
SIM-72pin
POWER
ISAIO
ISAMEM
ROM
SRAM
DRAM
TOVER
NMI_SW
P3MODE
PLLSEL
CKSEL
P07
P05
P04
P03
P02
P01
P00
P06
MODE1
RESET_SW
NMI_SW
POWER
JPORT3
SW2
SW1
RESET_SW
WAIT
PLD
Base Board
Socket Board
Socket Board
RAM
RAM
RAM
PLD
JP2
J3
J1
J2
JPOWER
JP1
Xtal
V852
JPORT10
JPORT1
JPORT0
JPORT2
RTE-V852-PC Board Top View
3.1. RESET SWITCH [SOCKET BOARD] (RESET_SW)
RESET_SW on the Socket board is the reset switch. Pressing this switch resets the CPU, and
causes the reset signal to be supplied to the Base board. This switch has the same function as the
reset switch on the Base board.
3.2. RESET SWITCH [BASE BOARD] (SW_RESET)
SW_RESET on the Base board is the reset switch. Pressing this switch resets the CPU. This
switch has the same function as the reset switch on the Socket board.
3.3. NMI SWITCH [SOCKET BOARD] (NMI_SW)
NMI_SW on the Base board is the NMI switch. Pressing this switch causes the level of the NMI pin
of the CPU to go Low. As the NMI signal is also provided by the Base board, the NMI signal from this
switch is ORed with the NMI signal from the Base board (see Section 9.2).

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3.4. POWER SUPPLY CONNECTOR [SCOKET/BASE BOARD] (JPOWER)
When this board is to be used as a standalone, that is, without being inserted in an ISA bus slot, the
board should be supplied with power from an external power supply by connecting it to the JPOWER
connector.
JPOWER connectors are provided both on the Socket board and on the Base board, but it is
recommended that the JPOWER connector on the Base board be used.
The external power should be one rated as listed below.
Voltage: 5 V
Current: Maximum of 2 A (excluding the current supplied to the JEXT connector)
Mating connector: Type A (5.5 mm in diameter)
Polarity:
GND
GND
+5 V
+5 V
[Caution] When attaching an external power supply to the board, be careful about its connector
polarity. When inserting the board into the ISA bus slot, do not attach the JPOWER
connector to an external power supply.

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3.5. PROCESSOR PIN CONNECTORS [SOCKET BOARD]
(JPORT0, JPORT1, JPORT2, JPORT3, JPORT10)
The pins of the CPU are inserted into these connectors. For details of the connections within the
board, see Chapter 13.
JPORT0
pin No. Signal name JPORT0 pin No. Signal name
1GND 2GND
3P07/INTP13 4P06/INTP12
5P05/INTP11 6P04/INTP10
7P03/TI1 8P02/TCLR1
9P01/TO11 10 P00/TO10
JPORT0 Pin Arrangement
JPORT1
pin No. Signal name JPORT1 pin No. Signal name
1GND 2GND
3P17 4P16
5P15 6P14
7P13 8P12
9P11 10 P10
JPORT1 Pin Arrangement
JPORT2
pin No. Signal name JPORT2 pin No. Signal name
1GND 2GND
3P27/SCK2- 4P26/SI2
5P25/SO2 6P24/INTP03Note
7P23/INTP02Note 8P22/INTP03Note
9P21/INTP03Note 10 NC.
JPORT2 Pin Arrangement
JPORT3
pin No. Signal name JPORT3 pin No. Signal name
1GND 2GND
3P37/SCK1 4P36/SI1
5P35/SO1 6P34/RXD
7P33/TXD 8P32/SCK0-
9P31/SI0 10 P30/SO0
JPORT3 Pin Arrangement
JPORT10
pin No. Signal name JPORT10 pin No. Signal name
1GND 2GND
3NC. 4NC.
5NC. 6NC.
7P103 8P102
9P101/HLDRQ- 10 P100/HLDAK-
JPORT10 Pin Arrangement
Note See Section 3.15.

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3.6. PROCESSOR PIN CONNECTORS [SOCKET BOARD/BASE BOARD] (J1, J2/J5, J6)
These connectors are used to connect the Socket board to the Base board.
J1/J5 pin No. Signal name J1/J5 pin No. Signal name
1GND 2GND
3P57/AD15 4P56/AD14
5P55/AD13 6P54/AD12
7P53/AD11 8P52/AD10
9P51/AD9 10 P50/AD8
11 GND 12 GND
13 P47/AD7 14 P46/AD6
15 P45/AD5 16 P44/AD4
17 P43/AD3 18 P42/AD2
19 P41/AD1 20 P40/AD0
21 P22/INTP01 22 P21/INTP00
23 RTE_CON-(IN) 24 1M/16M-(OUT)
25 +5V(IN) 26 +5V(IN)
J1/J5 Pin Arrangement
J2/J6 pin No. Signal name J2/J6 pin No. Signal name
1GND 2GND
3GND(A23) 4GND(A22)
5GND(A21) 6GND(A20)
7P63(A19) 8P62(A18)
9P61(A17) 10 P60(A16)
11 GND 12 GND
13 CLKOUT 14 X1(IN)
15 RESET-(IN/OUT) 16 WAIT-
17 NMI 18 P96/HLDRQ-
19 P95/HLDAK- 20 P94/ASTB
21 P93/DSTB- 22 P92/R_W-
23 P91/UBEN- 24 P90/LBEN-
25 P24/INTP03 26 P23/INTP02
J2/J6 Pin Arrangement

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3.7. SERIAL CONNECTOR [SOCKET BOARD] (J3)
The J3 connector is used for the RS-232C interface, controlled by the UART built into the CPU. The
pins of this connector have a pitch of 2.54 mm, and the pin arrangement is identical to that of the 9-
pin D-SUB RS-232C connector normally provided on the PC/AT when using a push-fit connector with
a ribbon cable. All signals at this connector are converted to the RS-232C level.
The pin arrangement of the J3 connector is shown below, after which the signal assignment is listed.
For details of the wiring of the connection signals when the board is connected to a PC (or host), see
the table in Section 3.20.
1
10
9
8
7
6
5
4
3
2
J3 Pin Arrangement
J3 pin No. Signal name Input/output Corresponding port
1NC Input
3RxD(RD) Input P34
5TxD(SD) Output P33
7DTR(DR)Note Output --
9GND
2DSR(ER) Input P37
4RTS(RS) Output P35
6CTS(CS) Input P36
8NC
10 NC
J3 Connector Signals
Note The DTR signal outputs the active level at power-on.

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3.8. SWITCH 1 [SOCKET BOARD] (SW1)
SW1 on the Socket board is the switch used for setting the mode.
SW1 contact 1 2 3 4
Port MODE CKSEL PLLSEL P3MODE
SW1-to-Port Correspondence
MODE1: Switch for specifying the operation mode of the V852.
OFF: Single chip mode
ON: ROM-less mode (factory-set)
CKSEL: Switch for specifying the CKSEL level of the V852.
OFF: Direct mode
ON: PLL mode (factory-set)
PLLSEL: Switch for specifying the PLLSEL level of the V852.
OFF: ×5 (factory-set)
ON: ×1
P3MODE: Switch for specifying the mode used by P3 of the V852.
OFF: Connects P34, P36, and P37 to JPORT3. (factory-set)
ON: Connects P34, P36, and P37 to J3 (RS-232C).
3.9. SWITCH 2 [SOCKET BOARD] (SW2)
SW2 on the Socket board is connected to CPU Port 0 and can be used freely by the user. When a
switch contact is OFF, it represents 1. When it is ON, it represents 0.
[Caution] Set all of the switch contacts to OFF when the P0 terminal is to be used for other
purposes.
SW2 contact 12345678
Port P00 P01 P02 P03 P04 P05 P06 P07
SW2-to-Port Correspondence
3.10. CRYSTAL SOCKET [SOCKET BOARD] (JP1)
JP1 has two roles. Namely, it is used to select the clock supplied to the CPU and also acts as the
connector for the crystal oscillator.
When an oscillator is connected to the OSC1 socket on the Base board:
Jumper pins 1 and 2 of JP1. Do not connect a crystal oscillator to JP1 in this case.
When a crystal oscillator is connected to JP1:
Connect the crystal oscillator across pins 1 and 3. Do not jumper pins 1 and 2.

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3.11. 7-SEGMENT LED [SOCKET BOARD] (LED_P1)
LED_P1 is a 7-segment LED, to which the P1 ports of the CPU are connected as shown in the table
below. When a bit is set to 1, the corresponding segment lights.
Segment A B C D EFGD.P.
Port P10 P11 P12 P13 P14 P15 P16 P17
LED_P1 Correspondence
A
B
C
D
E
F
G
DP
3.12. LEDS [SOCKET BOARD]
The table below explains the LEDs on the Socket board.
Name Description
LED_POWER Lights when power is supplied to the board.
LED Status
3.13. SWITCH 1 [BASE BOARD] (SW1)
SW1 is the switch connected to the general-purpose input ports and read by software. When a switch
contact is OFF, it represents 1. When it is ON, it represents 0. See Sections 4.1 and 6.5 for details.
3.14. SWITCH 2 [BASE BOARD] (SW2)
SW2 is the switch used for selecting the I/O address of the ISA bus. Switch contacts 1 to 8
correspond to A4 to A11 of the ISA bus address (A12 to A15 are fixed at 0). Therefore, this switch
can be used to select an I/O address in the range of 000xH to 0FFxH. When a switch contact is OFF,
it represents 1. When it is ON, it represents 0 (see Section 4.1).
SW2 contact 12345678
Address A4 A5 A6 A7 A8 A9 A10 A11
SW2-to-Address Correspondence

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3.15. SWITCH 3 [BASE BOARD] (SW3)
SW3 is the switch used for selecting whether the interrupt factors on the Base board are to be
connected to the CPU. The relationship between the switch contact numbers, CPU interrupt pins
and interrupt factors is given in the table below. When a switch contact is OFF, it represents no
connection. When it is ON, it represents connection to the CPU.
When a signal having the same pin name as one of the CPU pin names listed below is transmitted
through the JPORT2 connector, set the corresponding contact of SW3 to OFF.
Usually, set all of the switch contacts to OFF. For INT0SEL and INT1SEL, see Section 9.3.
SW3
contact CPU pin name J5/J6 pin No. Interrupt factor
1P21/INTP00 J5-Pin 22 Interrupt request of UART2(SCC2) of TL16C552A
on Base board. Interrupt is High level.
2P22/INTP01 J5-Pin 21 Interrupt request on Base board that is selected
with INT0SEL. Interrupt is High level.
3P23/INTP02 J6-Pin 26 Inverted signal of JEXT bus interrupt request
signal (INT-). Interrupt is High level.
4P24/INTP03 J6-Pin 25 Interrupt request on Base board that is selected
with INT1SEL. Interrupt is High level.
SW3-to-Interrupt Correspondence
3.16. ROM CAPACITY SWITCHING JUMPER [BASE BOARD] (JP1)
JP1 is the jumper to be set according to the capacity of the mounted ROM. Leave it open when
mounting 128 Kbytes (64K ×16-bit) or 256 Kbytes (128K ×16-bit) of ROM. Close the jumper when
mounting 512 Kbytes (256K ×16-bit) of ROM.
3.17. ISA BUS INTERFACE SWITCHING JUMPER [BASE BOARD] (JP2)
JP2 is the jumper for switching the mode of the interface with the ISA bus. This jumper should
normally be left open.
3.18. LEDS [BASE BOARD]
These LEDs are used for status indication. The LEDs are explained in detail in the table below.
Name Description
POWER Lights when power is supplied to the board.
ROM Lights when the ROM area is selected.
SRAM Lights when the SRAM area is selected.
DRAM Lights when the DRAM area is selected.
TOVER Lights when a time-over ready interrupt occurs and remains lit until the
time-over ready interrupt is cleared by software. (See Section 12.1.)
WAIT Lights when a wait cycle occurs as a result of a cycle being generated in
the external extension bus. The brightness of the LED corresponds to
the wait cycle frequency.
ISAMEM Lights when the ISA memory area is selected.
ISAIO Lights when the ISA I/O area is selected.
LED Status

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3.19. TEST PINS FOR ROM EMULATION [BASE BOARD] (JROMEM)
JROMEM are the test pins used to connect a ROM in-circuit type debugger. These test pins accept
control signals from the ROM in-circuit debugger. The signal names and functions are listed in the
table below.
Signal name Input/output Function
RESET- Input Connects the reset request signal from the ROM in-circuit
debugger. The CPU is reset when a Low level signal is input.
The input is pulled up by a 1 kΩresistor on the board.
NMI- Input Connects the NMI request signal (break request) from the ROM
in-circuit debugger. The NMI is input to the CPU when a Low
level signal is input. The input is pulled up by a 1 kΩresistor on
the board. (See Section 9.2.)
GND Ground pin to ground the ROM in-circuit debugger.
Test Pin Functions

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3.20. SERIAL CONNECTORS [BASE BOARD] (JSIO1, JSIO2)
The JSIO1 and JSIO2 connectors are used for the RS-232C interface controlled by the serial
controller (TL16C552A). Regarding the connector shapes, JSIO1 is a 9-pin D-SUB RS-232C
connector like that normally provided on the PC/AT, while JSIO2 is a pin header type connector with a
pitch of 2.54 mm. All signals at both of these connectors are converted to RS-232C level. The pin
arrangements of these connectors are shown below, after which the signal assignments are listed.
For the connection signals when the connectors are connected to the host, the table lists the wiring for
both the D-SUB 9 pins and D-SUB 25 pins on the host side. (Regular cross-cable wiring is used for
these connections.)
The pin arrangement of JSIO2 is identical to that of JSIO1 when a push-fit connector with a ribbon
cable is connected to JSIO2.
1
9
8
7
6
5
4
3
2
JSIO1 Pin Arrangement
1
10
9
8
7
6
5
4
3
2
JSIO2 Pin Arrangement
Connector pin No. on the host sideJSIO1
pin No. JSIO2 pin No. Signal name Input/output D-SUB9 D-SUB25
1 1 DCD Input
2 3 RxD(RD) Input 3 2
3 5 TxD(SD) Output 2 3
4 7 DTR(DR) Output 1, 6 6, 8
5 9 GND 5 7
6 2 DSR(ER) Input 4 20
7 4 RTS(RS) Output 8 5
8 6 CTS(CS) Input 7 4
9 8 RI Input
-- 10 NC
JSIO1/2 Connector Signals

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3.21. PARALLEL CONNECTOR [BASE BOARD] (JPRT)
The JPRT connector is used for the parallel interface controlled by the parallel (printer) controller
(TL16C552A). It is a pin header type connector with a pitch of 2.54 mm. All signals at this
connector are at the RS-232C level. Its pin arrangement and signal assignment are shown and
listed below.
The pin arrangement of JPRT is identical to the 25-pin D-SUB connector like that normally provided
on the PC/AT when a push-fit connector with a ribbon cable is used.
1
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
JPRT Pin Arrangement
JPRT
pin No. Signal name JPRT pin No. Signal name
1STB- 2AUTO_FD-
3D0 4ERROR-
5D1 6INIT-
7D2 8SELECT_IN-
9D3 10 GND
11 D4 12 GND
13 D5 14 GND
15 D6 16 GND
17 D7 18 GND
19 ACK- 20 GND
21 BUSY 22 GND
23 PE 24 GND
25 SELECT 26 NC
JPRT Connector Signals
3.22. EXTENSION BUS CONNECTOR [BASE BOARD] (JEXT)
The JEXT connector is provided to enable the extension of memory or I/O. This connector is
internally connected to the local bus of the Base board. For details of this connector, see Chapter 8.
3.23. CLOCK SOCKET [BASE BOARD] (OSC1)
The OSC1 socket is connected to an oscillator used to supply clock pulses to the CPU. At the
factory setting, the V852 uses a PLL for generating the system clock, and the CPU clock frequency is
five times that of the oscillator connected to the OSCI socket.
The clock supplied to the CPU can also be obtained from a crystal oscillator connected to JP1 on the
Socket board. (See Section 3.10).
The oscillator connected to the OSC1 socket must be of an 8-pin DIP type (half type).
[Caution] When the OSC1 socket is used, short pins 1 and 2 of JP1 on the socket board.

RTE-V852-PC USER’S MANUAL (Rev. 1.10)
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3.24. DRAM-SIMM SOCKETS
A 4-Mbyte SIMM is mounted in the DRAM-SIMM socket as standard. This socket can hold a 72-pin
SIMM (known as a module in the case of DOS/V machines) with a capacity of 4 or 8 Mbytes, and can
also accept an EDO type DRAM-SIMM in addition to normal DRAM-SIMMs. Select a DRAM that
satisfies the access timing requirements by referring to Section 7.3. The capacity of the connected
SIMM can be read through the PIO port. (See Section 6.6.)
3.25. ROM SOCKETS
The RTE-V852-PC has ROM sockets to hold 40-pin ROM chips to provide standard 128 Kbytes (64K
×16 bits). When the standard ROM is replaced to enable the use of a Multi debugger, connect ROM
having an access time of no more than 150 ns. When mounting RAM of a different capacity, it may
sometimes be necessary to switch JP1 on the Base board. (See Section 3.16.)

RTE-V852-PC USER’S MANUAL (Rev. 1.10)
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4. INSTALLATION AND USE
The RTE-V852-PC board is designed to be installed in the ISA bus slot of a PC/AT or compatible
(hereafter called the PC). However, it can also be used as a standalone, if it is powered from an
external power supply. When the board is used for testing purposes or with the Multi debugger,
communication software called RTE for Windows must be installed in the PC. Refer to the RTE for
Windows Installation Manual for installation and test methods.
4.1. BOARD SETTING
The RTE-V852-PC board has DIP switches. The DIP switches can be used to set up the evaluation
board. The switch layout is shown below.
Switches on the RTE-V852-PC Board
SW1 on the Base board is a switch for general-purpose input ports. For the Multi monitor in the
factory-installed ROM, SW1 is used to set the RS-232C baud rate and profiler timer period.
SW1 contact 1 2 Baud rate
Setting ON
OFF
ON
OFF
ON
ON
OFF
OFF
Not used
38400 baud
19200 baud
9600 baud (factory-set)
Baud Rate Setting
SW2
SIO/PRT SW_RESET
JPOWER
JEXT
JSIO1
PLD
PLD
SW1
ROM
RAM
NMI-
GND
TIMER
RESET-
JPRT
JSIO2
J5
J6
JROMEM
OSC1
1pin
JP1
SIM-72pin
POWER
ISAIO
ISAMEM
ROM
SRAM
DRAM
TOVER
WAIT
PLD
Base Board
Socket Board
RAM
RAM
RAM
PLD
JP2
NMI_SW
P3MODE
PLLSEL
CKSEL
P07
P05
P04
P03
P02
P01
P00
P06
MODE1
RESET_SW
NMI_SW
POWER
JPORT3
SW2
SW1
RESET_SW
Socket Board
J3
J1
J2
JPOWER
JP1
Xtal
V852
JPORT10
JPORT1
JPORT0
JPORT2