MPD Technologies PDM-IR User manual

MICRO PHOTON DEVICES
PDM-IR
900 nm – 1700 nm Infrared Photon
Detection Module
ã Micro Photon Devices S.r.l.
Via Stradivari, 4
39100 Bolzano (BZ), Italy
email info@micro-photon-devices.com
Phone +39 0471 051212 • Fax +39 0471 501524
PDM-IR User Manual Version 3.0.3 - September 2018

PDM-IR user manual v3.0.3
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Table of Contents
1!INTRODUCTION 4!
2!THE INGAAS/INP SINGLE-PHOTON AVALANCHE DIODE 5!
2.1!Gated)Mode)Operation) 5!
2.2!Free)Running)Operation) 8!
2.3!Further)readings) 9!
3!PDM-IR HARDWARE CHARACTERISTICS 10!
3.1!Rear)Panel)10!
3.2!Mechanical)Dimension)11!
4!PDM-IR SPECIFICATIONS 13!
4.1!PDM-IR)Trigger)Section)14!
4.1.1!Internal Trigger 15!
4.1.2!Trigger In 16!
4.1.3!Aux In 16!
4.1.4!Logic Function 17!
4.2!PDM-IR)Gate)Section)18!
4.2.1!Gated mode with fixed gate width operation 19!
4.2.2!Gated mode with Free-gate operation 20!
4.2.3!Free running mode 20!
4.3!PDM-IR)SPAD)Section)21!
4.3.1!Temperature 22!
4.3.2!Excess Bias 22!
4.3.3!Hold Off 22!
4.4!PDM-IR)Counters)Section)23!
4.5!PDM-IR)Output)Section)23!
4.5.1!PHOTON OUT 24!
4.5.2!TTL AUX OUT 25!
4.5.3!NIM AUX OUT 25!
4.6!PDM-IR)LED)Status)25!
4.7!PDM-IR)propagation)delays)26!
5!PDM-IR SOFTWARE INTERFACE 28!

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5.1!Installation)28!
5.2!Software)Interface)28!
5.2.1!Main Window: Trigger and Gate Section 28!
5.2.2!Main Window: SPAD Section 30!
5.2.3!Main Window: Output Section 31!
5.2.4!Main Window: Status Section 32!
5.2.5!Main Window: Counter Section 33!
5.2.6!Counter Window 34!
5.2.7!Module Selection Window 34!
5.2.8!Module Info Window 35!
5.2.9!Configurations Window 35!
5.2.10!Save configuration Window 36!
5.2.11!RunTime Menu 37!
6!SETUPS 38!
6.1!Basic)setups)38!
6.1.1!Photon Counting setup 38!
6.1.2!Photon Timing setup 40!
6.2!Advanced)setups)41!
6.2.1!Cross correlation setup with external sync 41!
6.2.2!Cross correlation setup without sync 43!
6.2.3!Long Decay Measurement 44!
7!SYSTEM REQUIREMENTS 47!
COPYRIGHT AND DISCLAIMER 47!

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1 Introduction
The MPD PDM-IR, is built around a Peltier cooled InGaAs/InP Single-Photon Avalanche Diode (SPAD) for the
detection of near-infrared single photons from 900 nm up to 1700 nm.
The module includes a programmable frequency and pulse generator for gating the detector, a front-end
circuit for photodetector’s avalanche sensing, a fast circuit for detector’s avalanche current quenching and
operative bias voltage resetting and some sub-circuits for signal conditioning. All the main parameters and
delay paths are adjustable by the user through the software interface, in order to match the requirements of
different applications. The system can be conveniently used both for counting and timing measurements,
since the high-performance electronics guarantees a clean temporal response even with fast gate transitions.
PDM-IR can work either in free-runnging or in gated mode (see paragraph 2) and the optical interface can be
chosen between a free space and a pigtailed version as shown by Figure 1 and Figure 2.
Figure 1. PDM-IR free space version.
Figure 2. PDM-IR fiber pigtailed version.

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2 The InGaAs/InP Single-Photon Avalanche Diode
The core of this module is a Single-Photon Avalanche Diode (SPAD), housed into the Detection Head. The
detector has a 25 μm diameter active area in case of the free space version or a 10 µm diameter SPAD when
pigtailed with a single-mode fiber. The diode is mounted on the top of a three-stage Peltier cooler. A SPAD is
a p-n junction, biased well above the breakdown voltage (VB), that stays in a meta-stable state with no
current flowing. At this bias, the electric field is so high that a single charge carrier injected in the depletion
layer can trigger a self-sustaining avalanche. The current rises swiftly (nanoseconds or sub nanosecond rise-
time) to a macroscopic steady level, in the milliAmpere range. If the primary carrier is photo-generated, the
leading edge of the avalanche pulse precisely marks the photon arrival time. The current continues to flow
until the avalanche is quenched by lowering the bias voltage down to or below VB. Then the bias voltage
must be restored, in order to detect another photon. These operations are usually performed by a suitable
circuit named Active Quenching Circuit (AQC).
The device primary source of internal noise consists in a random dark-counting rate (DCR) arising from free
carriers thermally generated. These events compete with photons in triggering the detector and thus impair
the signal to noise ratio. The Peltier cooler is therefore useful to lower the temperature of the detector in
order to diminish this effect.
2.1 Gated Mode Operation
Normally single photon detectors are operated in the so-called free-running mode, where the devices are
enabled immediately after the quenching of each avalanche current. This is true for Silicon SPADs but for
InGaAs SPADs, due to higher DCR, gated regime is also used, for further reducing these unwanted counts:
the detector is periodically enabled for a short time window called Gate, of duration
!"#
(Gate Width),
whereas it is usually held off at a bias slightly below the breakdown voltage.
The counting rate (CR) of a detector operated in free running, and not in gated mode, is simply the number
of counts generated by the module output (PHOTON OUT) divided by the integration time:
$% &'()*+,-./-$.(012
301+4,516.0-!6)+
When the detector is operated in gated mode, the photon-out count rate (CR) must be corrected considering
both the Gate Frequency, i.e. the frequency at which the SPAD is periodically enabled, and the Gate Width
(
!"#
), i.e. the time length during which the SPAD is turned on during each duty cycle. The correction is due
to the fact that photons (or dark-counts) may be absorbed during the times the SPAD is kept turned off and

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so are not counted. The correction considers how many photons have been counted and for how long, during
the integration time, the SPAD has been kept really turned on. In order to calculate the true counting rate,
thus, the following formula must be used:
$%789: & ; <
!"# =>?-
@
<;$% A!
B
where T is the Gate Period, i.e. the reciprocal of the Gate Frequency.
In most of the applications, this formula can usually be approximated to:
$%789: C$% A!
!"# -----/.,------$% D! E <
that is the raw counts divided by the duty-cycle applied to the detector.
However, a secondary source of noise exists in SPADs: the afterpulsing. During the avalanche some carriers
are captured by deep levels in the junction depletion layer and subsequently released with a statistically
fluctuating delay. Released carriers can retrigger the avalanche, generating after-pulses correlated with a
previous avalanche pulse which sum up with the DCR. In order to mitigate these avalanche re-triggerings,
after each avalanche, during the subsequent gating occurrences, the detector is kept off for a user
programmable time, named hold-off time,
!F"
. In this way the trapped carriers can be released without
triggering further avalanches. The hold-off time is particularly useful when cooling the detector since the
afterpulsing effect worsens at low temperatures because the decay times of the trapped carriers increase.
The hold-off time is usually longer than the gate period T.
An example of a photon counter module, operated in gated mode and employing the hold-off feature, is
shown in Figure 3. The reference signal is TRIGGER GATE which sets the gate repetition rate (frequency). The
signal actually applied to the SPAD is GATE, it is synchronized with TRIGGER GATE and has a width that
corresponds to the TON of the SPAD. Initially GATE and TRIGGER GATE are synchronized and their pulses
correspond 1-to-1. When a photon is absorbed, it triggers the avalanche current which is marked, in this
example, by the falling edge of Photon Output pulse. Once the avalanche is detected it is immediately
quenched; the system does not wait for the end of the Gate window to bias below breakdown the SPAD.
Now GATE and TRIGGER GATE begin to differ. During the hold-off time, the TRIGGER GATE pulses are ignored,
and GATE remains low, keeping the photodetector OFF. The SPAD is enabled again when the hold off time is
over. Of course, if a photon arrives at the detector after the end of a previous hold-off but during the gate-
off time, it is not detected as shown in Figure 3. Finally, in case the hold-off ends inside a GATE pulse, the
latter is either skipped (as shown in Figure 3) or applied with a reduced width, i.e. only the remaining part of
TON following the end of the hold-off. For a complete description of what happens see paragraph 4.2.

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Figure 3. Main waveform in the module in case of the gated mode operation: output of pulse generator (TRIGGER
GATE), pulses at the SPAD detector (GATE), hold off time keeping the detector off for the amount of time
(HOLD OFF) and photon output signal (PHOTON OUTPUT).
Now, because of the hold-off time, the measured counting rate CR is not equivalent to the actual rate of
photons but can be estimated by:
$%F" &$%
<; $% A!F"
In counting applications, the maximum count rate should be then limited at about
<G@H!F"B
, because for
higher values the correction factor becomes so high that even small errors in the equation’s parameters will
result in high errors in the CRHO counting-rate.
Since the MPD PDM-IR biases the SPAD in gated mode and applies the hold-off every time an avalanche is
detected, the two effects must be applied at the same time in order to obtain the correct photon counting
rate CRphoton from the measured counting rate CR. From simple mathematics, it turns out that the final
equation is the following:
$%IJKLKM & ; <
!"# =>?-
N
<; $%
<;$% D !F" A!
O
which can then be simplified to :
$%IJKLKM C$%
<;$% D !F" A!
!"# -----/.,----- $% D!
<;$% D!F" E <
Please note that the previous equations do not consider the Photon Detection Efficiency of the InGaAs SPAD.
These formulas also strictly apply when the photon rate is uniformly distributed over time while particular
care must be used when applied to specific cases like the one discussed in paragraph 6.1.2.
Figure 3 is, in addition, very helpful in explaining the VALID GATE output. This signal is generated in order to
properly trace which TRIGGER GATE pulse effectively enabled the SPAD, i.e., which are the pulses that were

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not blanked during the hold-off time (VALID GATE is a digital signal with the same pattern of Gate). This
information is particularly useful when looking for the percentage of counts over the total number of
available valid gates. In fact, in timing measurements one must be careful not to exceed the single-photon
statistics, in order not to distort the TCSPC histogram (see paragraph 6.1.2).
2.2 Free Running Operation
As already discussed, normally single photon detectors are operated in the so-called free-running mode,
where the devices are enabled immediately after the quenching of each avalanche current. PDM-IR allows
the user the possibility to choose which type of module operation, and thus not only the gated mode but
also the free running mode is possible with PDM-IR. In this mode of operation, as shown in Figure 4, TRIGGER
GATE signal is no more useful because the SPAD is always enabled until an avalanche is triggered. After each
of them, the SPAD is disabled for the hold off time and then immediately and swiftly re-enabled.
Overall, as a suggestion, the gated mode is used to achieve the best Signal-to-Noise (SNR) ratios and timing
resolutions whenever the signal to be detected is synchronous with a reference signal (for example the laser
clock used to stimulate the signal emission) that can be used to synchronize the PDM-IR. Indeed, better S/N
ratio or dynamic range, in case of TCSPC measurements, are achieved by enabling the detector only for the
short windows where the signal is present and keeping the detector off whenever the signal is not present.
The free running mode is typically used instead whenever the signal to be detected is not synchronous with
a reference signal (like the stimulated emission of photons from a nonlinear crystal by a CW laser). Of course,
free-running mode can also be used whenever a synchronous signal has to be detected but the S/N ratio (or
the dynamic range) is, in this case, lower compared to the gated mode module since the detector is always
enabled and InGaAs/InP diodes have much higher noise and after pulsing, compared to the silicon diodes.
Figure 4. Main waveforms for PDM-IR module in case of the free running operation: TRIGGER GATE is not significative
and ignored, the SPAD detector enabling time (GATE), the off time in case of avalanche (HOLD OFF) and
photon output signal (PHOTON OUTPUT).

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2.3 Further readings
Cova, S., Ghioni, M., Lacaita, A. L., Samori, C., and Zappa, F. “Avalanche photodiodes and quenching circuits
for single-photon detection”, Applied Optics, 35(12), 1956—1976 (1996).
http://dx.doi.org/10.1364/AO.35.001956
Cova, S., Ghioni, M., Zappa, F., Rech, I., and Gulinatti, A., “A view on progress of silicon single-photon
avalanche diodes and quenching circuits”, Proceedings of SPIE , 6372, pp. 63720I-1 - 63720I-12 (2006).
http://dx.doi.org/10.1117/12.685963
Alberto Tosi, Alberto Dalla Mora, Franco Zappa and Sergio Cova, “Single-photon avalanche diodes for the
near-infrared range: detector and circuit issues,” Journal of Modern Optics, 56:2-3, 299-308 (2008) -
http://dx.doi.org/10.1080/09500340802263075
Alberto Tosi, Alberto Dalla Mora, Simone Tisa, Fabio Acerbi, Franco Zappa and Sergio Cova , “InGaAs/InP
SPADs for near-infrared applications: device operating conditions and dedicated electronics,” Proc. SPIE
7681, Advanced Photon Counting Techniques IV, 76810R (April 28, 2010);
http://dx.doi.org/10.1117/12.850696
Alberto Tosi, Adriano Della Frera, Andrea Bahgat Shehata, and Carmelo Scarcella, “Fully programmable
single-photon detection module for InGaAs/InP single-photon avalanche diodes with clean and sub-
nanosecond gating transitions,” Rev. Sci. Instrum. 83, 013104 (2012)
http://dx.doi.org/10.1063/1.3675579

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3 PDM-IR hardware characteristics
3.1 Rear Panel
The PDM-IR has USB, power, IOs connectors and LED lens on rear side as shown in Figure 5. A description of
each component can be found in Table 1.
Table 1. PDM-IR rear panel components
PHOTON OUT
RF output, requires 50 Ohm DC terminated transmission lines. The output is a NIM pulse,
which means that the low logic level is 0 V and the high logic level is -800 mV. The falling
edge of the pulse marks, with very low jitter, the photon detection time. See paragraph 4.5
for a complete electrical description of this signal.
NIM AUX OUT
RF output, requires 50 Ohm DC terminated transmission lines. The output is a NIM pulse,
which means that the low logic level is 0 V and the high logic level is -800 mV. Output signal
is user selectable. See paragraph 4.5 for the available possibilities and for a complete
electrical description of this signal.
TTL AUX OUT
RF output, requires 50 Ohm DC terminated transmission lines. Electric pulses of 3.3V LVTTL
are generated at this output. Output signal is user selectable. See paragraph 4.5 for the
available possibilities and for a complete electrical description of this signal.
AUX IN
RF input, 50 Ohm with fixed DC impedance. The trigger signal can be positive or negative and
the input internal threshold is fully programmable. See Table 4 for a complete electrical
description of this input.
TRIGGER IN
RF input, 50 Ohm with fixed DC impedance. The trigger signal can be positive or negative and
the input internal threshold is fully programmable. See Table 3 for a complete electrical
description of this input.
USB ❶
Connector for a USB type-B cable. Used for PC connection
POWER SUPPLY ❸
Jack for connecting the provided +12V power supply. It requires at least 15 W output power.
Use only power supply provided by MPD to avoid electronics damage.
STATUS LED ❷
This LED indicates the PDM-IR status. It can be Green, Orange, Red and Off. See paragraph
4.6 for a complete description of the possible statuses
Figure 5. PDM-IR rear panel with highlighted connectors.

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3.2 PDM-IR Mechanical Dimension
Figure 6. Mechanical dimensions of the PDM-IR fiber pigtailed version.

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Figure 7. Mechanical dimensions of the PDM-IR free space version.

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4 PDM-IR Specifications
The PDM-IR module is a complete system for photon counting in the NIR range (Figure 1, Figure 2) and it can
be used either in gated or in free-running mode. Both modes of operations can be optimized through the use
of several user selectable parameters, all controllable from a computer using either the delivered SDK library
or the provided Windows® PC software.
When used in gated mode (see Figure 3 and paragraph 2 for details), the TRIGGER GATE signal, for GATE
frequency generation, can be provided either using an INTERNAL TRIGGER or through an external signal fed
into the TRIGGER IN input. In the former case, for synchronizing the GATE with other instruments, it is
possible to replicate the INTERNAL TRIGGER at one of the two available outputs, depending on the desired
pulse polarity, i.e. the TTL AUX OUT or the NIM AUX OUT. Complex external trigger patterns can be also fed
to the TRIGGER IN input, since it accepts not only periodic but also aperiodic signals as shown in Figure 12.
Additionally, it is possible to create even more complex TRIGGER GATE patterns for GATE generation, by
combining the auxiliary input AUX IN signal with the INTERNAL TRIGGER or the TRIGGER IN, and by using the
provided user-selectable logic functions (see paragraph 4.1 for more details). An example of such
combination is shown in Figure 10. Finally, GATE signal can be generated either by exactly replicating
TRIGGER GATE (Figure 13) or by creating a new signal, synchronized with the rising edge of TRIGGER GATE
and with a fixed gated-ON width equal to the user set TON value (Figure 12). See paragraph 4.2 for more
details. Of course, as discussed in paragraph 2, independently of the chosen trigger pattern, GATE signal is
disabled for the duration of the HOLD OFF time, following each avalanche triggering. At the end of the Hold
off time, two types of reset are possible depending on how the gate electronics handles what happens when
the hold-off terminates inside a gate-ON time window. See paragraph 4.2 for a detailed description.
When used in free running mode (see also Figure 4 and paragraph 2), the INTERNAL TRIGGER, TRIGGER IN
and AUX IN signals are meaningless and the SPAD is always on until a SPAD avalanche is initiated. In this case,
the avalanche current is first quenched and then, after a well-defined hold-off, the detector is immediately
enabled (see paragraph 4.2.3). Of course, in free running mode only one type of hold off reset is possible
since GATE signal is always immediately enabled at the end of the hold-off time, as shown in Figure 14.
Concerning the SPAD parameters Hold-OFF time, excess bias voltage and SPAD temperature, they are all user
selectable to get the best results from the measurement (see paragraph 4.3 for in-depth description).
Concerning the outputs: PHOTON OUT is the low timing jitter output signal, precisely marking the photon
detection time; NIM AUX OUT and TTL AUX OUT, shouldn’t be used for low jitter timing measurements and

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Figure 8. PDM-IR Block diagram.
the output signal can be chosen independently, on each out channel, among TRIGGER GATE, INTERNAL
TRIGGER, VALID GATE, PHOTON OUT, HOLD OFF and MODULE STATUS signals (paragraph 4.5).
Independently on the chosen PDM-IR mode of operation, the module has also internal counters that
continuously monitor the following signals: TRIGGER IN, AUX IN, INTERNAL TRIGGER, PHOTON OUT and
VALID GATE. Specially in case of the PHOTON OUT, these counters are useful for counting applications
whenever an external counter is not available (paragraph 4.4).
Finally, in the PDM-IR, all the main signal paths have a programmable delay, designed to help the user in
synchronizing the various signals between them and with the external instruments. This feature is very
helpful in many applications as it allows to avoid the hassle of continuously changing the cable length.
In Figure 8 the full PDM-IR block diagram is shown, while in the next paragraphs we will describe the functions
and the characteristics of each subsection of it.
4.1 PDM-IR Trigger Section
This section is designed for generating the TRIGGER GATE signal that in turn is used for shaping the GATE
signal actually applied to the detector. As discussed in paragraph 2, by controlling the detector in gated mode
it is possible to enable the SPAD only when the signal is impinging the detector and thus increasing the SNR.

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The PDM-IR offers an advanced Trigger section in order to generate trigger events only when required by the
application (Figure 9). It accepts 3 signals: TRIGGER IN and AUX IN, provided by the user and INTERNAL
TRIGGER, which is internally generated. The external inputs accept positive or negative signals and the
threshold can be user selected with tens of mV resolution. TRIGGER IN and INTERNAL TRIGGER are mutually
exclusive and can be combined with AUX IN with a user selectable logic operation in order to generate the
final TRIGGER GATE. In the next paragraphs the performance of each sub-block of the Trigger section, shown
in Figure 9, is illustrated.
4.1.1 Internal Trigger
The INTERNAL TRIGGER is an internally created waveform with a periodic pattern with fixed frequency
(selectable by the user) and a duty cycle equal to 50%. In order to be able to synchronize the PDM-IR module
with other instrumentations, set the TTL AUX OUT and/or the NIM AUX OUT to output the INTERNAL
TRIGGER. In Table 2 the Electrical characteristics of the INTERNAL TRIGGER are illustrated.
Figure 9. PDM-IR Trigger Section Block diagram.
Table 2. Internal trigger specifications
Parameter
Symbol
Description
Min.
Typ.
Max.
Unit
Internal Trigger Frequency
freqIN
100
100 M
Hz
Internal Trigger Frequency Step
ΔfreqIN
1
Hz
Frequency Total Stability
-100
100
ppm
Internal Trigger Duty Cycle
40
50
60
%
Internal Trigger Delay
δINT_TRIGGER
0
100
ns
Internal Trigger Delay step
1
ns

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4.1.2 Trigger In
The TRIGGER IN, provided by the user, can be periodic or aperiodic, positive and/or negative. It’s normally
used to synchronize the GATE signal of the PDM-IR with a LASER source that cannot be triggered. The user
can set the threshold voltage and the significative edge. In Table 3 the Electrical characteristics of the
TRIGGER IN input are illustrated.
Table 3. Trigger In specifications
Parameter
Symbol
Description
Min.
Typ.
Max.
Unit
Trigger In Max Frequency
100 M
Hz
Trigger In Delay
δTRIGGER_IN
0
100
ns
Trigger In Delay step
1
ns
Trigger In high voltage
VIH_IN
3
V
Trigger In low voltage
VIL_IN
-2
V
Trigger In differential range
VID_IN
-2
2
V
Trigger In termination
RIN_IN
50
Ω
Trigger In voltage overdrive
VOV_IN
100
mV
Trigger In pulse width
tIN_PULSEmin
800
ps
Trigger In Slew Rate
SRIN
10
V/µs
Trigger In Edge
Neg/pos
Trigger In Threshold
VTH_IN
-2
2
V
Trigger In Threshold resolution
ΔVTH_IN
10
mV
4.1.3 Aux In
The AUX IN input is provided by the user, can be periodic or aperiodic, positive and/or negative. It’s an
auxiliary signal, useful to enable or disable the SPAD in certain conditions. Threshold voltage and significative
edge can be set by the user. The logic function between AUX IN and TRIGGER (see Figure 9) can be for
example very useful in some measurements, like cross-correlation ones (see paragraph 6.2.1). Figure 10
shows an example of what happens in case of an aperiodic and complex TRIGGER IN is combined with the
shown AUX IN signal by means of a OR logic port which generates the TRIGGER GATE. The same figure shows
the case where the TRIGGER GATE is generated combining TRIGGER IN and AUX IN with an AND logic. In
Table 4 the Electrical characteristics of the AUX IN input are illustrated.

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Table 4. Aux In electrical specifications.
Parameter
Symbol
Description
Min.
Typ.
Max.
Unit
Aux In Max Frequency
100 M
Hz
Aux In Delay
δAUX_IN
0
100
ns
Aux In Delay step
1
ns
Aux In high voltage
VIH_AUX
3
V
Aux In low voltage
VIL_AUX
-2
V
Aux In differential range
VID_AUX
-2
2
V
Aux In termination
RIN_AUX
50
Ω
Aux In voltage overdrive
VOV_AUX
100
mV
Aux In pulse width
tIN_AUX
800
ps
Aux In Slew Rate
SRAUX
10
V/µs
Aux In Edge
Neg/pos
Aux In Threshold
VTH_AUX
-2
2
V
Aux in Threshold resolution
ΔVTH_AUX
10
mV
Figure 10. Advance trigger section using AUX IN signal in logic function with TRIGGER IN signal. TRIGGER GATE is shown
in case of use the OR port and the AND port between the two signals.
4.1.4 Logic Function
The Logic Function Block allows advanced gate triggering using TRIGGER (selected between TRIGGER IN and
INTERNAL TRIGGER) and AUX IN as inputs. The Logic Function can be AND, OR or XOR. The two inputs and
the output can also be inverted if needed. Figure 10 shows an example of combination between TRIGGER IN
and AUX IN signals in case OR or AND logic is used.

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Figure 11. PDM-IR Gate Section Block diagram.
4.2 PDM-IR Gate Section
The TRIGGER GATE signal (see Figure 11), coming from the PDM-IR Trigger Section (4.1), is shaped in order
to generate the desiderated gate width and frequency, i.e. the EFFECTIVE GATE. The PDM-IR offers also three
possible mode of generating the EFFECTIVE GATE signal and thus of operation:
1. For each TRIGGER GATE rising edge, a fixed gate width, set by the TON parameter, is generated
(described in 4.2.1);
2. EFFECTIVE GATE replicates the TRIGGER GATE waveform (see paragraph 4.2.2);
3. The module works in free running mode and thus becomes TRIGGER GATE independent (see 4.2.3).
The EFFECTIVE GATE, whose electrical characteristics are shown in Table 5, can also be delayed before being
applied to the SPAD. The GATE signal is thus the EFFECTIVE GATE after a user controllable delay and with the
HOLD-OFF, also user controllable, applied after every avalanche triggering. As GATE depends on the actual
photon flux, it can only be monitored through the VALID GATE signal. Finally, as HOLD-OFF plays an important
role in GATE generation, it is also here discussed, while its possible selectable values are shown in paragraph
4.3.3.
Table 5. Gate electrical specifications.
Parameter
Symbol
Description
Min.
Typ.
Max.
Unit
Effective Gate
Max Frequency
100M
Hz
Effective Gate
Delay
δEFFECTIVE_GATE
0
100
ns
Effective Gate
Delay step
1
ns
Gate Window
tON
1 n
1.5 m
s
Gate Window
Step
ΔTON
1
ns

PDM-IR user manual v3.0.3
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19
!
Figure 12. Typical signals in Gated mode with fixed gate width operation and hold-off set to HOLD OFF EDGE (i.e. gate
pulses that even partially overlap with the hold off are skipped).
4.2.1 Gated mode with fixed gate width operation
In this operating mode, shown in Figure 12, the PDM-IR generates a gate window, with a fixed width equal
to TON, for each TRIGGER GATE rising edge. In case of a photon detection (or in general an avalanche
triggering), while at PHOTON OUT a pulse is generated for marking the photon arrival time, the GATE signal
is swiftly disabled for a period equals to the set HOLD-OFF time and all trigger events during this time are
masked. At the end of the Hold off time, two types of reset are possible depending on how the gate
electronics handles what happens when the hold-off terminates inside a gate-ON time window.
More precisely, the Hold Off can be synchronized with the EFFECTIVE GATE signal (HOLD OFF EDGE) or can
be set asynchronous (HOLD OFF LEVEL). With the HOLD OFF EDGE modality, the first gate window to be
applied to the SPAD, following the end of a HOLD-OFF, is the first one to have its rising edge positioned in
time after the end of the hold-off, as shown in Figure 12. In this case, as shown in Figure 12, the gate window,
that happens across the time instant that the HOLD-OFF ends, is skipped. The use of HOLD OFF EDGE is thus
a safe condition because it ensures that all the applied gate pulses have the same width, i.e. the set TON. It
follows that the equations discussed in paragraph 2 can be applied seamlessly and that the user does not
incur in any measurement distortion, especially in case of high photon fluxes and in correlation
measurements.
With the HOLD OFF LEVEL modality the SPAD can be immediately enabled at the end of the hold-off, if the
status of GATE is high, as shown in Figure 13. For example, if the hold-off ends in the middle of a GATE
window, the latter is not skipped as before, but the SPAD is enabled starting from the end of the HOLD OFF
and stopping, as usual, with the end of this particular GATE window. In a simpler way, GATE will always follow
the EFFECTIVE GATE pattern, immediately as the hold off ends.

PDM-IR user manual v3.0.3
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20
!
Figure 13. Typical signals in Gated mode with Free-gate operation and hold-off set to HOLD OFF LEVEL.
In this case non-standard gates are generated which may lead to measurement errors at high photon fluxes
and in other cases. For this reason, this modality is normally more useful if used in conjunction with the free-
gate mode of operation (see paragraph 4.2.2).
Finally, it is worth noting that, in gated-mode with fixed gate width, after an avalanche triggering, GATE signal
is left disabled until the next GATE pulse, even if TON is longer than the hold-off time. In other words, in this
gate modality, only the first event inside a gate-on window is recorded.
4.2.2 Gated mode with Free-gate operation
In gated mode with Free-gate operation (Figure 13), the PDM-IR works like the previous mode, generating a
gate window for each trigger event, but GATE pulses replicate exactly those of TRIGGER GATE, apart of course
when the HOLD OFF is applied. In fact, in this mode of operation TRIGGER GATE and EFFECTIVE GATE are
identical. Even in gate-mode with Free-gate operation, in case of photon detection, all GATE windows that
occur during a HOLD OFF are masked. Finally, even with this mode of operation HOLD OFF LEVEL and HOLD
OFF EDGE can be chosen. In Free-gate operation, opposite to the gated mode with fixed width, it is possible
to have multiple triggers inside a TON window when TON is longer than the set HOLD OFF (normally TON >>
HOLD OFF). Of course, in order to unlock this possibility, the HOLD OFF LEVEL should be set as, only in this
case, when the HOLD OFF ends the GATE is immediately applied if the TRIGGER GATE is high. In this way it is
possible thus to count more than 1 photon per gate, useful in some particular applications.
4.2.3 Free running mode
In free running mode, as shown in Figure 14, the SPAD is always enabled and it is TRIGGER GATE independent.
In case of photon detection, the SPAD is disabled during the hold off time, but at the end of it is swiftly is re-
enabled. Of course, in this case only the HOLD OFF LEVEL setting is allowed.
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