Multitech MultiConnect MTPCIE-EV3 Instruction Manual

MultiConnect®PCIe
MTPCIE-EV3 Developer Guide

MULTICONNECT PCIE MTPCIE-EV3 DEVELOPER GUIDE
2 MultiConnect®PCIe MTPCIE-EV3 Developer Guide
MultiConnect PCIe MTPCIE-EV3 Developer Guide
Models: MTPCIE-EV3-xx,
Part Number: S000549, Version 1.2.6
Copyright
This publication may not be reproduced, in whole or in part, without the specific and express prior written permission signed by an executive officer of
Multi-Tech Systems, Inc. All rights reserved. Copyright © 2014 by Multi-Tech Systems, Inc.
Multi-Tech Systems, Inc. makes no representations or warranties, whether express, implied or by estoppels, with respect to the content, information,
material and recommendations herein and specifically disclaims any implied warranties of merchantability, fitness for any particular purpose and non-
infringement.
Multi-Tech Systems, Inc. reserves the right to revise this publication and to make changes from time to time in the content hereof without obligation of
Multi-Tech Systems, Inc. to notify any person or organization of such revisions or changes.
Trademarks
Multi-Tech, MultiConnect, and the Multi-Tech logo are registered trademarks of Multi-Tech Systems, Inc. All other brand and product names are
trademarks or registered trademarks of their respective companies.
Legal Notices
The MultiTech products are not designed, manufactured or intended for use, and should not be used, or sold or re-sold for use, in connection with
applications requiring fail-safe performance or in applications where the failure of the products would reasonably be expected to result in personal injury or
death, significant property damage, or serious physical or environmental damage. Examples of such use include life support machines or other life
preserving medical devices or systems, air traffic control or aircraft navigation or communications systems, control equipment for nuclear facilities, or
missile, nuclear, biological or chemical weapons or other military applications (“Restricted Applications”). Use of the products in such Restricted
Applications is at the user’s sole risk and liability.
MULTITECH DOES NOT WARRANT THAT THE TRANSMISSION OF DATA BY A PRODUCT OVER A CELLULAR COMMUNICATIONS NETWORK WILL BE
UNINTERRUPTED, TIMELY, SECURE OR ERROR FREE, NOR DOES MULTITECH WARRANT ANY CONNECTION OR ACCESSIBILITY TO ANY CELLULAR
COMMUNICATIONS NETWORK. MULTITECH WILL HAVE NO LIABILITY FOR ANY LOSSES, DAMAGES, OBLIGATIONS, PENALTIES, DEFICIENCIES, LIABILITIES,
COSTS OR EXPENSES (INCLUDING WITHOUT LIMITATION REASONABLE ATTORNEYS FEES) RELATED TO TEMPORARY INABILITY TO ACCESS A CELLULAR
COMMUNICATIONS NETWORK USING THE PRODUCTS.
The MultiTech products and the final application of the MultiTech products should be thoroughly tested to ensure the functionality of the MultiTech
products as used in the final application. The designer, manufacturer and reseller has the sole responsibility of ensuring that any end user product into
which the MultiTech product is integrated operates as intended and meets its requirements or the requirements of its direct or indirect customers.
MultiTech has no responsibility whatsoever for the integration, configuration, testing, validation, verification, installation, upgrade, support or maintenance
of such end user product, or for any liabilities, damages, costs or expenses associated therewith, except to the extent agreed upon in a signed written
document. To the extent MultiTech provides any comments or suggested changes related to the application of its products, such comments or suggested
changes is performed only as a courtesy and without any representation or warranty whatsoever.
Contacting MultiTech
Knowledge Base
The Knowledge Base provides immediate access to support information and resolutions for all MultiTech products. Visit http://www.multitech.com/kb.go.
Support Portal
To create an account and submit a support case directly to our technical support team, visit: https://support.multitech.com.
Support
Business Hours: M-F, 8am to 5pm CT
Country By Email By Phone
Europe, Middle East, Africa: [email protected] +(44) 118 959 7774
U.S., Canada, all others: [email protected] [phone] or [phone]
Warranty
To read the warranty statement for your product, visit www.multitech.com/warranty.go. For other warranty options, visit www.multitech.com/es.go.
World Headquarters
Multi-Tech Systems, Inc.
2205 Woodale Drive, Mounds View, MN 55112
Phone: [phone] or [phone]
Fax [phone]

CONTENTS
MultiConnect®PCIe MTPCIE-EV3 Developer Guide 3
Contents
Chapter 1 – Product Overview ................................................................................................................................. 6
About MultiConnect PCIe.............................................................................................................................................. 6
Documentation ........................................................................................................................................................... 6
Product Build Options ................................................................................................................................................... 6
Developer Kit Contents ................................................................................................................................................ 7
Chapter 2 – Pinout ................................................................................................................................................... 8
Multi-Tech Mini PCIe Pinout ......................................................................................................................................... 8
Standard Mini-PCI Express Pinout ............................................................................................................................ 10
Chapter 3 – Design Considerations......................................................................................................................... 12
Design Consideration .................................................................................................................................................. 12
Noise Suppression Design........................................................................................................................................... 12
PC Board Layout Guideline ......................................................................................................................................... 12
Electromagnetic Interference .................................................................................................................................... 12
Electrostatic Discharge Control................................................................................................................................... 13
USB Design ................................................................................................................................................................. 13
Chapter 4 – Developer Board ................................................................................................................................. 14
Chapter 5 – Assembly Diagram .............................................................................................................................. 16
Top .............................................................................................................................................................................. 16
Bottom ........................................................................................................................................................................ 17
Chapter 6 – Developer Board Block Diagram.......................................................................................................... 18
Chapter 7 – Developer Board Schematics............................................................................................................... 19
Chapter 8 – Board Components ............................................................................................................................. 28
Chapter 9 – Installing the Device and Antennas ..................................................................................................... 30
Chapter 10 – Attaching Power Supply Blades......................................................................................................... 31
Power Supply and Blades............................................................................................................................................ 31
Attaching the Blades ................................................................................................................................................... 31
Chapter 11 – Safety Notices and Warnings............................................................................................................. 32
Radio Frequency (RF) Safety ....................................................................................................................................... 32
Sécurité relative aux appareils à radiofréquence (RF).............................................................................................. 32
Vehicle Safety.............................................................................................................................................................. 32
User Responsibility...................................................................................................................................................... 33
Device Maintenance ................................................................................................................................................... 33
Notice regarding Compliance with FCC, EU, and Industry Canada Requirements for RF Exposure........................... 33
Chapter 12 – Labeling Requirements...................................................................................................................... 35
Approvals and Certification......................................................................................................................................... 35
Example EV-DO EV3 Label......................................................................................................................................... 35

CONTENTS
4 MultiConnect®PCIe MTPCIE-EV3 Developer Guide
Host Labeling............................................................................................................................................................. 35
Chapter 13 – Regulatory Statements...................................................................................................................... 36
47 CFR Part 15 Regulation Class B Devices ................................................................................................................. 36
Industry Canada Class B Notice................................................................................................................................... 36
Requirements for Cellular Antennas with regard to FCC/IC Compliance ................................................................. 36
Chapter 14 – Environmental Notices ...................................................................................................................... 37
Waste Electrical and Electronic Equipment Statement .............................................................................................. 37
WEEE Directive.......................................................................................................................................................... 37
Instructions for Disposal of WEEE by Users in the European Union ........................................................................ 37
Restriction of the Use of Hazardous Substances (RoHS) ............................................................................................ 37
Information on HS/TS Substances According to Chinese Standards ......................................................................... 39
Information on HS/TS Substances According to Chinese Standards (in Chinese) ...................................................... 40
Chapter 15 – Antennas, Cables, GPS ...................................................................................................................... 41
Antenna System Cellular Devices................................................................................................................................ 41
Notice regarding Compliance with FCC, EU, and Industry Canada Requirements for RF Exposure......................... 41
EV-DO and CDMA Antenna Information................................................................................................................... 41
Antenna Cable Information ...................................................................................................................................... 42
GPS Antenna Specifications ...................................................................................................................................... 42
OEM Integration ....................................................................................................................................................... 43
Chapter 16 – Activation and Carrier Specific Information....................................................................................... 45
Account Activation for Cellular Devices ..................................................................................................................... 45
Notice for Devices that Use Aeris Radios.................................................................................................................... 45
Chapter 17 – Mechanical Drawing MTPCIE-EV3-xx ................................................................................................. 46
Chapter 18 – Specifications .................................................................................................................................... 47
MTPCIE-EV3 Specifications.......................................................................................................................................... 47
MTPCIE DC Electrical Characteristics .......................................................................................................................... 49
Absolute Maximum Rating........................................................................................................................................ 49
PCIE Connector Leads ................................................................................................................................................. 49
MTPCIE-EV3 Power Draw............................................................................................................................................ 53
Powering Down Your Device ...................................................................................................................................... 53
RF Performances ........................................................................................................................................................ 53
Chapter 19 – Using Linux with EV3 Devices ............................................................................................................ 55
Shell Commands.......................................................................................................................................................... 55
Testing Serial Ports.................................................................................................................................................... 55
Create a PPP Connection ............................................................................................................................................ 55
H5 Example ............................................................................................................................................................... 55
EV3 Example.............................................................................................................................................................. 56
MAT1 (MVW1) Example............................................................................................................................................ 56
C Programming............................................................................................................................................................ 57
open()........................................................................................................................................................................ 57

CONTENTS
MultiConnect®PCIe MTPCIE-EV3 Developer Guide 5
read()......................................................................................................................................................................... 58
write()........................................................................................................................................................................ 58
close()........................................................................................................................................................................ 59
Test Program() .......................................................................................................................................................... 60
Index...................................................................................................................................................................... 62

PRODUCT OVERVIEW
6 MultiConnect®PCIe MTPCIE-EV3 Developer Guide
Chapter 1 – Product Overview
About MultiConnect PCIe
Documentation
Download the following documentation at www.multitech.com/setup/product.go.
Document Description
MultiConnect PCIe Developer
Guide
This document. Provides an overview, safety and regulatory information,
developer board schematics and pinouts, and device.
USB Driver Installation Guide Provides instructions for installing USB drivers on Linux and Windows systems
(part number S000569).
EV-DO and CDMA AT Commands
Reference Guide
Configure the MTPCIE-EV3 with EV-DO AT Commands (part number S000546).
Product Build Options
Product Description
MTPCIE-EV3-N2 EV-DO Rev A Embedded Cellular Modem with GPS (DE910-DUAL) Sprint
MTPCIE-EV3-N16 EV-DO Rev A Embedded Cellular Modem with GPS (DE910-DUAL) Aeris
Developer Kit
MTPCIE-DK1 Developer Kit
Note:
These units ship without network activation.
To connect them to the cellular network, you need a cellular account. For more information, refer to
Account Activation.
The complete product code may end in .Rx. For example, MTPCIE-EV3.Rx, where R is revision and x is
the revision number.
All builds can be ordered individually or in 50-packs.

PRODUCT OVERVIEW
MultiConnect®PCIe MTPCIE-EV3 Developer Guide 7
Developer Kit Contents
Your Developer Kit (MTPCIE-DK1) includes the following:
Developer Board 1 - MTPCIE-DK1 Developer Board
Power Supply 1 - 100-240V 9V-1.7A power supply with removable blades, 1 - US blade/plug, 1 - EURO
blade/plug, 1 - UK blade/plug
Cables 1 - RS-232 DE9F-DE9M serial cable, 1 - RJ-45 Ethernet cable, 2 -USB cable 2 - SMA-to-UFL
antenna cables (1 - for cellular, 1 - for GPS) 1 - RSMA-to-UFL antenna cable for
Bluetooth/Wi-Fi.
Note: For MTPCIE-EV3 models, your final product design needs to have approved
Exceltek antenna. For details, refer to Antennas, Cables, and GPS. Also note that
the Bluetooth/WiFi antenna is included in the Developer Kit for use other models;
MTPCIE-EV3 does not include Bluetooth/WiFi.
Antennas 1 - 3.3V magnetic GPS antenna , 1 - HEPTA band SMA antenna, 1 - 2.4GHz, dipole Wi-Fi
antenna
Customer Notices Legal and Support information
Additional One promotional screwdriver

PINOUT
8 MultiConnect®PCIe MTPCIE-EV3 Developer Guide
Chapter 2 – Pinout
Multi-Tech Mini PCIe Pinout
Note:
SDIO can operate up to 25Mhz. Treat the SDIO traces to Host like a bus and keep the bus length as short as
possible. Multi-Tech recommends adding series termination resistors on all the SDIO traces.
Pin # Name I/O Function
1 SDIO_D0 I/O Unused
2 3.3Vaux I 3.3Vaux
3 SDIO_D1 I/O Unused
4 GND Ground
5 SDIO_D2 I/O Unused
6 BT_TXD I Unused
7 SDIO_D3 I/O Unused
8 BT_RTS I Unused
9 GND Ground
10 BT_CTS O Unused
11 SDIO_CMD I/O Unused
12 BT_RXD O Unused
13 SDIO_CLK I Unused
14 BT_EN I Unused
15 GND Ground
16 GPIO_2 I/O Unused
17 WLAN_EN I Unused
18 GND Ground
19 WLAN_IRQ O Unused
20 3G_ONOFF I 3G Cellular On/Off (low active)
21 GND Ground
22 3G_RST I 3G Cellular Reset line (low active)
23 1.8V O Unused
24 3.3Vaux I 3.3Vaux
25 GPIO_1 I/O Unused
26 GND Ground
27 GND Ground

PINOUT
MultiConnect®PCIe MTPCIE-EV3 Developer Guide 9
Pin # Name I/O Function
28 3G_DVI_WA0 I/O Unused
29 GND Ground
30 3G_DVI_CLK I/O Unused
31 3G_DVI_RX I Unused
32 RI O Unused
33 3G_DVI_TX O Unused
34 GND Ground
35 GND Ground
36 USB_D- I/O 3G USB Negative Data
37 GND Ground
38 USB_D+ I/O 3G USB Positive Data
39 3.3Vaux I 3.3Vaux
40 GND Ground
41 3.3Vaux I 3.3Vaux
42 LED_WWAN# O 3G Cellular STAT LED Output
43 GND Ground
44 DCD O Unused
45 CTS O Unused
46 GPIO_3 I/O Unused
47 RTS I Unused
48 DTR I Unused
49 RXD O Unused
50 GND Ground
51 TXD I Unused
52 3.3Vaux I 3.3Vaux

PINOUT
10 MultiConnect®PCIe MTPCIE-EV3 Developer Guide
Standard Mini-PCI Express Pinout
For reference only.
Pin # Function I/O Description
1 WAKE# O WAKE
2 3.3Vaux I 3.3Vaux
3 COEX1 I Co-existence pin, not defined
4 GND GND
5 COEX2 I Co-existence pin, not defined
6 1.5V I 1.5V
7 CLKREQ# O CLKREQ#
8 UIM_PWR I UIM_PWR
9 GND GND
10 UIM_DATA I/O UIM_DATA
11 REFCLK+ I PCI Express reference clock
12 UIM_CLK I UIM_CLK
13 REFCLK- I PCI Express reference clock
14 UIM_RESET I UIM_RESET
15 GND GND
16 UIM_VPP 0 UIM_VPP
17 Reserved Reserved
18 GND GND
19 Reserved Reserved
20 W_DISABLE# I W_DISABLE#
21 GND GND
22 PERST# I PERST#
23 PERn0 O PCI Express receiver differential pair signal
24 3.3Vaux I 3.3Vaux
25 PERp0 O PCI Express receiver differential pair signal
26 GND GND
27 GND GND
28 1.5V I 1.5V
29 GND GND
30 SMB_CLK I SMB_CLK
31 PETn0 I PCI Express transmitter differential pair signal

PINOUT
MultiConnect®PCIe MTPCIE-EV3 Developer Guide 11
Pin # Function I/O Description
32 SMB_DATA I/O SMB_DATA
33 PETp0 I PCI Express transmitter differential pair signal
34 GND GND
35 GND GND
36 USB_D- I/O USB Negative Data
37 GND GND
38 USB_D+ I/O USB Positive Data
39 3.3Vaux I 3.3Vaux
40 GND GND
41 3.3Vaux I 3.3Vaux
42 LED_WWAN# O LED Output
43 GND GND
44 LED_WLAN# O LED Output
45 Reserved Reserved
46 LED_WPAN# O LED Output
47 Reserved Reserved
48 1.5V I 1.5V
49 Reserved Reserved
50 GND GND
51 Reserved Reserved
52 3.3Vaux I 3.3Vaux

DESIGN CONSIDERATIONS
12 MultiConnect®PCIe MTPCIE-EV3 Developer Guide
Chapter 3 – Design Considerations
Design Consideration
When using the Multi-Tech MiniPCIe form factor:
Consult your modem’s device guide for device dimensions. With the modem, the Multi-Tech Mini PCIe form
factor exceeds the standard Mini PCIe maximum component height for top and bottom.
If you need to install components under the module, use taller connectors to avoid conflict. Multi-Tech
recommends not installing components under the module.
Check the Pinout table for pins that differ from the MiniPCIe spec.
Noise Suppression Design
Adhere to engineering noise-suppression practices when designing a printed circuit board (PCB). Noise suppression
is essential to the proper operation and performance of the modem and surrounding equipment.
Any OEM board design must consider both on-board and off-board generated noise that can affect digital signal
processing. Both on-board and off-board generated noise that is coupled on-board can affect interface signal levels
and quality. Noise in frequency ranges that affect modem performance is of particular concern.
On-board generated electromagnetic interference (EMI) noise that can be radiated or conducted off-board is
equally important. This type of noise can affect the operation of surrounding equipment. Most local government
agencies have certification requirements that must be met for use in specific environments.
Proper PC board layout (component placement, signal routing, trace thickness and geometry, and so on)
component selection (composition, value, and tolerance), interface connections, and shielding are required for the
board design to achieve desired modem performance and to attain EMI certification.
Other aspects of proper noise-suppression engineering practices are beyond the scope of this guide. Consult noise
suppression techniques described in technical publications and journals, electronics and electrical engineering text
books, and component supplier application notes.
PC Board Layout Guideline
In a 4-layer design, provide adequate ground plane covering the entire board. In 4-layer designs, power and ground
are typically on the inner layers. Ensure that all power and ground traces are 0.05 inches wide.
Electromagnetic Interference
The following guidelines are offered specifically to help minimize EMI generation. Some of these guidelines are the
same as, or similar to, the general guidelines. To minimize the contribution of device-based design to EMI, you
must understand the major sources of EMI and how to reduce them to acceptable levels.
Keep traces carrying high frequency signals as short as possible.
Provide a good ground plane or grid. In some cases, a multilayer board may be required with full layers for
ground and power distribution.
Decouple power from ground with decoupling capacitors as close to the device's power pins as possible.
Eliminate ground loops, which are unexpected current return paths to the power source and ground.

DESIGN CONSIDERATIONS
MultiConnect®PCIe MTPCIE-EV3 Developer Guide 13
Decouple the power cord at the power cord interface with decoupling capacitors. Methods to decouple
power lines are similar to decoupling telephone lines.
Locate high frequency circuits in a separate area to minimize capacitive coupling to other circuits.
Locate cables and connectors to avoid coupling from high frequency circuits.
Lay out the highest frequency signal traces next to the ground grid.
If using a multilayer board design, make no cuts in the ground or power planes and be sure the ground
plane covers all traces.
Minimize the number of through-hole connections on traces carrying high frequency signals.
Avoid right angle turns on high frequency traces. Forty-five degree corners are good; however, radius turns
are better.
On 2-layer boards with no ground grid, provide a shadow ground trace on the opposite side of the board to
traces carrying high frequency signals. This will be effective as a high frequency ground return if it is three
times the width of the signal traces.
Distribute high frequency signals continuously on a single trace rather than several traces radiating from
one point.
Electrostatic Discharge Control
Handle all electronic devices with precautions to avoid damage due to the static charge accumulation.
See the ANSI/ESD Association Standard (ANSI/ESD S20.20-1999) – a document “for the Development of an
Electrostatic Discharge Control for Protection of Electrical and Electronic Parts, Assemblies and Equipment.” This
document covers ESD Control Program Administrative Requirements, ESD Training, ESD Control Program Plan
Technical Requirements (grounding/bonding systems, personnel grooming, protected areas, packaging, marking,
equipment, and handling), and Sensitivity Testing.
MultiTech strives to follow these recommendations. Input protection circuitry is incorporated in MultiTech devices
to minimize the effect of static buildup. Take precautions to avoid exposure to electrostatic discharge during
handling.
MultiTech uses and recommends that others use anti-static boxes that create a faraday cage (packaging designed
to exclude electromagnetic fields). MultiTech recommends that you use our packaging when returning a product
and when you ship your products to your customers.
USB Design
MultiTech recommends that you review Intel's High Speed USB Platform Design Guidelines for information about
USB signal routing, impedance, and layer stacking. Also:
Shield USB cables with twisted pairs (especially those containing D+/D-).
Use a single 5V power supply for USB devices. See Power Draw for current (ampere) requirements.
Route D+/D- together in parallel with the trace spacing needed to achieve 90 ohms differential impedance
for the USB pair and to maintain a 20 mil space from the USB pair and all other signals.
If power is provided externally, use a common ground between the carrier board and the device.

DEVELOPER BOARD
14 MultiConnect®PCIe MTPCIE-EV3 Developer Guide
Chapter 4 – Developer Board
This developer board drawing shows the major board components.

DEVELOPER BOARD
MultiConnect®PCIe MTPCIE-EV3 Developer Guide 15

ASSEMBLY DIAGRAM
16 MultiConnect®PCIe MTPCIE-EV3 Developer Guide
Chapter 5 – Assembly Diagram
Top

ASSEMBLY DIAGRAM
MultiConnect®PCIe MTPCIE-EV3 Developer Guide 17
Bottom

DEVELOPER BOARD BLOCK DIAGRAM
18 MultiConnect®PCIe MTPCIE-EV3 Developer Guide
Chapter 6 – Developer Board Block Diagram

DEVELOPER BOARD SCHEMATICS
MultiConnect®PCIe MTPCIE-EV3 Developer Guide 19
Chapter 7 – Developer Board Schematics

DEVELOPER BOARD SCHEMATICS
20 MultiConnect®PCIe MTPCIE-EV3 Developer Guide