NAD C 510 User manual

NAD
SERVICE MANUAL
C510
C510
Direct Digital DAC
Direct Digital DAC

TABLE OF CONTENTS
DESCRIPTION P A G E
SPECIFICATIONS…………………………….…………………………..........3
BLOCK DIAGRAM…………………………………………………………....4-6
PCB LAYOUT…………..................……………………..……….……....18-21
EXPLODED VIEW PARTS LIST
ASSY EXPLODED VIEW
ELECTRICAL VIEW PARTS LIST…………………………..……...…...22-32
....……………………………………………........34
…………………………………….. .......35
CIRCUIT DIAGRAMS…………………………………………………….....9-17
TROUBLE SHOOTING A………………………………………………..........7
TROUBLE SHOOTING B………………………………………………..........8
PACKING DIAGRAM……................……………………..……….……......33

SPECIFICATIONS
KA РУССКИЙ
3
C 510
<0.0005% (0dBFS)
<0.002% (-60dBFS)
IMD Distortion 0.0001%
Signal/Noise Ratio <-123dB (ref. 0dBFS 2V out)
Channel Separation >-115dB (ref. 0dBFS Volume -1dB)
Sample Rate 32kHz to 192kHz (USB and digital S/PDIF)
Frequency Response ±0.5dB (ref. 20Hz - 96kHz @ 192kHz sample rate)
Output Level 2V (ref. input 0dBFS)
INPUT
AES/EBU XLR
SPDIF Coaxial x 1
Optical x 1
HDMI x 2 (2-channel PCM)
USB Class 2 Audio: asynchronous 24/192 support
IR In
Trigger In 12V ±20%
OUTPUT
HDMI Video Out (3D video pass through)
Analogue Unbalanced
Balanced 47 ohms
110 ohms
Trigger Out 12V ±20%
GENERAL
AC Supply 100-240V AC ~ 50/60Hz
Standby Power <0.5W
Idle Power 16W
Unit Dimension (WxHxD) - Gross* 435 x 99 x 309mm
17 1/8 x 3 15/16 x 12 3/16 inches**
Net Weight 4.7kg (10.4lb)
Shipping Weight 5.6kg (12.3lb)
* Gross dimensions include feet, extended buttons and rear panel terminals.
** Non-metric measurements are approximate. NAD Electronics will not assume any liability for errors being made by retailers, custom installers,
cabinet makers, or other end users based on information contained in this document.
Note: Installers should allow a minimum clearance of 55mm for wire/cable management.

COAX1
OPTO1
AES/EBU
SPDIF INPUT
INPUTFORMAT
VOLUME
TREBLE,BASS,EQ
SAMPLERATE
CONVERTER
ZTA FILTER
4thORDER
NOISESHAPER
PWM
OUTPUT
PWM
OUTPUT
REF
MCLK 108M
FS 2450
FS
SAMPLER
(ADC)
NOISE
SHAPER
3rd
ZETEX FPGA
DDFA
CONTROL
INTERFACE
D
1
G
2
V
3
GP1UV701QS
Key&IR&ECONDEfrontpanel
SPI INT
GPIO/INT
5V
STANDBY PSU
5V 0.5A standby mode( <0.2W dissipation )
5VS
5VS
5VS
POWERSWITCH
LN
6.3AT/250V
GPIO
5VS
standby
Signal
Pow er
control
Preout
Main MCU
PIC32MX460F256L
LDO
R3V3
LDO
Type A
USB FOR UPGRADE
NAD C510 BLOCK DIAGRAM
VERSION: V1.0
AMS1117-3.3
3V3S
LDO
3V3 1V8
5V
AK4118AEQ
LOW JITTER SPDIF interface
ADV7623
HDMI Transceiver
HDMIIN1
HDMIIN2
HDMIOUT
Type B XMOS
USB audio Device
IIS0
IIS1
IIS2
TRIGIN
IRIN
LOGIC BUFFER
RS232
Pluginsenser
DISPLAY
mute
SPI
GPIO
SPI
FLIP FLOPS
FLIP FLOPS
CH0-3
CH4-7
CLASS A MOD
CLASS A MOD
mute
SMPS
12V 3A
LDO
+/-18V
+/-15V
+/-15V
12V
UNLOCK
3V3
USB FOR UPGRADE
3V3S
3V3S
LDO
3V3
1V8
8V
12V
5V
5V
DC/DC
LDO
3V3
1V2
5V
LDO
8V
8V
MOS-SWITCH 5V
USB GPIO
A
1
C
2
B
3
ENCODE
BLOCK DIAGRAM
4

ADV7623
CH0
CH1
CH2
VIDEO DATA
DE
VS
HS
AUDIO DATA
VIDEO DATA
DE
VS
HS
AUDIO DATA
VIDEO DATA
DE
VS
HS
AUDIO DATA
VIDEO DATA
DE
VS
HS
AUDIO DATA
08302-001
XTAL
XTAL1
RXA_C
RXB_C
RXC_C
RXD_C
RXA_0
RXA_1
RXA_2
VIDEO/AUDIO
CLOCK
GENERATION
RX
PLL
CEC
TXC
TX0
TX1
TX2
5V DETECT
COMPONENT
PROCESSOR
SCL
SDATA
ALSB
CS
I
2
C
CONTROLLER
PWRDN
RESET
GLOBAL
CONTROLS
DDCA_SDA
DDCA_SCL
DDCB_SDA
DDCB_SCL
DDCC_SDA
DDCC_SCL
DDCD_SDA
DDCD_SCL
AP0_IN
AP1_IN
AP2_IN
AP3_IN
AP4_IN
AP5_IN
SCLK_IN
MCLK_IN
AP0_OUT
AP1_OUT
AP2_OUT
AP3_OUT
AP4_OUT
AP5_OUT
SCLK_OUT
MCLK_OUT
ARC+
RX EDID/
REPEATER
CONTROLLER
RX HPD
CONTROLLER
EP_MISO
EP_MOSI
EP_CS
EP_SCK
SPI MASTER/
SLAVE
EQUALIZER
RXB_0
RXB_1
RXB_2 EQUALIZER
SAMPLER
SAMPLER
RXC_0
RXC_1
RXC_2 EQUALIZER SAMPLER
RXD_0
RXD_1
RXD_2 EQUALIZER
CEC
CONTROLLER
EDID
RAM
SAMPLER
HDMI RECEIVER
PROCESSOR
TRANSMITTER
PACKET BUILDER
HDCP
ENCRYPTION
ENGINE
HDMI
ENCODER
SERIALIZER
TMDS DRIVERS
INT1
INT2
INT_TX
INTERRUPT
CONTROLLER
TXDDC_SDA
TXDDC_SCL
TX
EDID/HDCP
CONTROLLER
EDID/HDCP
BUFFER
HPD_ARC–
TX HPD
CONTROLLER
HDCP
DECRYPTION
ENGINE
SYNC
MEASUREMENT PACKET PROCESSOR
INFOFRAME
PACKET
MEMORY
AUDIO
PROCESSOR
ARC
RECEIVER
AUDIO
CAPTURE
HDCP KEYS
TX
PLL
ADV7623
5V_DETA
5V_DETB
5V_DETC
5V_DETD
HP_CTRLA
HP_CTRLB
HP_CTRLC
HP_CTRLD
OSD
Figure1.
Block Diagram
5