Novametrix medical systems 515 User manual

Service

Manual

Pulse

Oximeter

Model

515

Aug

16,

1989

Part

Number

9593-9()-()()

This

manual

applies

only

to

Model

515

monitors

with

serial

numbers

starting

with

the

number

66.

(e.g.,

66-xxxx)

Novametrix

Medical

Systems

Inc.

Wallingford,

Connecticut,

U.S.A.

06492.

Copyright

All

rights

reserved.

No

part

of

this

manual

may

be

reproduced

without

the

written

permission

of

Novametrix

Medical

Systems

Inc.

MANUAL

REVISION

HISTORY

Guarantee

Equipment

manufactured

or

distributed

by

Novametrix

Medical

Systems

Inc.,

is

fully

guaranteed,

covering

materials

and

workmanship,

for

a

period

of

one

year

from

the

date

of

shipment,

except

for

certain

disposable

products

and

products

with

stated

guarantees

other

than

one

year.

Novametrix

reserves

the

right

to

perform

guarantee

service(s)

at

its

factory,

at

an

authorized

repair

sta¬

tion,

or

at

the

customer’s

installation.

Novametrix’

obligations

under

this

guarantee

are

limited

to

repairs,

or

at

Novametrix’

option,

replacement

of

any

defective

parts

of

our

equipment,

except

fuses,

batteries,

and

calibration

gasses,

without

charge,

if

said

defects

occur

during

nomial

service.

Claims

for

damages

during

shipment

must

be

filed

promptly

with

the

trans¬

portation

company.

All

correspondence

concerning

the

equipment

must

specify

both

the

model

name

and

number,

and

the

serial

number

as

it

appears

on

the

equipment.

Improper

use,

mishandling,

tampering

with,

or

operation

of

the

equipment

with¬

out

following

specific

operating

instructions

will

void

this

guarantee

and

release

Novametrix

from

any

further

guarantee

obligations.

Service

Department

For

factory

repair

service,

call

toll

free

1-800-243-3444

In

Connecticut,

call

Collect

(203)

265-7701

Telex

956-054

Facsimile

(203)

284-0753

Caution:

Federal

(U.S.A.)

law

restricts

this

device

to

sale,

distribution,

or

use

by

or

on

the

order

of

a

licensed

medical

practitioner.

This

document

contains

information

which

is

proprietary

and

the

property

of

Novametrix

Medical

Systems

Inc.,

and

may

not

be

reproduced,

stored

in

a

retrieval

system,

translated,

transcribed,

or

transmitted,

in

any

form,

or

by

any

means,

without

prior

explicit

written

permission

from

Novametrix

Medical

Systems

Inc.

Table

of

Contents

1.0

Theory

of

Operation.

1.1

Introduction.

1.2

Power

Supply

Board.

1.3

Digital

Board

#2283.

1.4

Analog

Botrrd

#2288.

2.0

Maintenance

Schedule..

2.1

General.

2.2

Battery

Maintenance.

2.3

Fuses

and

Line

Cord.

2.4

Operational

Tests.

2.5

Cleaning

the

Model

515.

2.6

Calibration

Verification

and

Adjustments

3.0

Operational

Tests.

3.1

Introduction.

3.2

Operational

Checks.

4.0

Calibration

and

Adjustments.

4.1

Calibration

Procedure.

4.2

Adjustment

Procedure.

4.3

Production

Test

Software.

4.4

Test

Fixtures.

4.5

Special

Functions.

5.0

Assembly

and

Disassembly.

5.1

Introduction.

5.2

Disassembly.

5.3

Assembly.

6.0

Specifications..

6.1

General.

6.2

Oxygen

Saturation

(Sa02

Section).

6.3

Pulse

Rate

(PR)

Section.

6.4

General

Specifications.

6.5

Additional

Features.

7.0

Connecting

External

Equipment.

7.1

RS232

Rear

Panel

Connector.

7.2

Model

315

Printer

Interface.

7.3

Think

Jet

Printer

Interface.

7.4

Analog

Output

Module.

8.0

Troubleshooting

Guide.

8.1

Monitor

Error

Messages.

9.0

Parts

Lists.

10.0

Schematics

and

Assembly

Drawings.

Service

Manual:

Model

515

Theory

of

Operation:lntroduc

1.0

Theory

of

Operation

1.1

Introduction

The

Novametrix

Model

515

Pulse

Oximeter

is

a

non-invasive

portable

(

meter

designed

to

provide

reliable

continuous

measurement,

display,

alerts

for,

oxygen

saturation

(Sa02)

and

pulse

rate.

The

monitor

can

be

p(

ered

by

AC

line

voltage

or

by

its

internal

battery.

The

Model

515

Pulse

Oximeter

utilizes

sensors

that

contain

two

li

emitting

diodes

(LEDs)

and

a

photodiode.

Each

LED

emits

a

specific

p

wavelength

of

light

(660

and

940

nanometers)

through

a

pulsating

vasci

bed

to

the

photodiode.

Because

oxygen

saturated

blood

absorbs

differ

amounts

of

light

at

each

wavelength

as

compared

to

unsaturated

blood,

amount

of

light

absorbed

by

the

blood

in

each

pulse

can

be

used

to

calcul

the

ratio

of

oxygenated

hemoglobin

to

total

hemoglobin.

This

is

displayed

Sa02.

Pulse

Rate

is

calculated

by

measuring

the

time

period

between

detec

peaks

of

the

waveform.

The

inverse

of

the

time

period,

the

frequency,

is

c

played

as

Pulse

Rate.

The

oxygen

saturation

measurement

and

the

pulse

i

(beats/minute

or

bpm)

are

displayed

on

the

monitor’s

Vacuum

Fluoresc

Displays

and

are

updated

once

a

second.

Presence

of

a

pulse

is

indicated

v

bly

by

a

bar

graph

and

audibly

(user

selectable)

by

a

tone.

The

Model

515

contains

four

main

assemblies.

These

assemblies

inch

the

Power

Supply

Unit

(PSU),

the

Digital

Board,

the

Analog

Board,

and

Bezel

Assembly

(which

includes

the

VFD

Display,

and

the

Membrane

K(

panel).

The

operation

of

each

is

discussed

in

detail

in

this

section,

referet

the

last

section

of

this

manual

for

the

schematics

and

assembly

drawings

t

correspond

to

each

discussion.

1.2

Power

Supply

Board

Circuitry

for

mains

or

battery

operation,

turn

on

control

circuitry,

isolai

supplies,

and

RS232

interface

are

contained

in

the

power

supply

board.

Ope

tion

of

the

power

supply

board

can

be

easily

described

in

a

block

diagram

n

Theory

of

OperationPower

Supply

Board

Service

Manual:

Model

resentation

as

shown

below,

each

block

is

described

in

detail.

Reference

pi

2503-01,

2503-03

to

follow

the

circuit

descriptions.

RS232

INTERFACE

AC/BATTERY

OPERATION

The

model

515

monitor

is

capable

of

either

AC

mains

operation,

or

op

tion

from

an

internal

battery.

When

the

line

cord

is

connected

and

the

rear

]

el

power

switch

is

on

(I

position)

a

green

LED

on

the

front

pane

illuminated.

This

indicates

that

the

AC

portion

of

the

power

supply

circuit!

powered

and

the

battery

is

being

charged.

When

the

mains

power

is

remc

the

unit

operates

under

battery

power

supplied

by

an

internal

lead

acid

i

Service

Manual:

Model

515

Theory

of

Operation:Power

Supply

Be

When

the

battery

runs

low

a

warning

message

is

displayed

which

instruct;

reconnect

the

mains

supply

in

order

to

recharge

the

battery.

If

the

battery

i

charges

to

a

predetermined

level

(=8

VDC)

the

unit

will

automatically

turn

self

off

to

avoid

damage

to

the

lead

acid

cell.

1.2.1

Transformer

and

rectifier

When

the

unit

is

powered

by

AC

(mains)

the

secondary

voltage

from

power

transformer

is

rectified

by

D13

and

filtered

by

Cl6.

Transistor

Q4

is

ased

on,

this

powers

IC4,

a

power

switching

regulator.

This

regulator

is

se:

13.8

volts

DC

by

VR2,

it

not

only

charges

the

battery

while

under

AC

(mai

operation

but

also

supplies

power

to

the

VBACK

regulator.

If

the

AC

(mai

is

removed

then

the

internal

lead

acid

battery

powers

the

monitor.

With

mains

power

diode

D6

is

forward

biased,

this

enables

the

battery

to

power

monitor.

When

AC

is

present

D6

is

reverse

biased

due

to

the

fact

that

voltage

on

its

cathode

(approx.

22

VDC)

is

more

positive

than

the

voltage

its

anode

(approx.

12

VDC).

Therefore

the

battery

receives

only

a

charge

w

age

from

IC4

via

D4,

FI,

and

R14.

Fuse

FI

and

resistor

R14

are

to

protect

battery

from

excessive

charge

currents.

Diode

D4

isolates

IC4

and

ICS

wl

under

battery

power.

1.2.2

Backup

regulator

Backup

memory

which

is

located

on

the

digital

board,

and

the

control

(

cuitry

which

turns

the

unit

on,

requires

power

even

when

the

unit

is

off

and

connected

to

the

AC

mains.

The

backup

regulator

IC2

will

have

either

4

VDC

(battery

power)

or

+13.8

VDC

(AC

mains

power)

at

8,

this

is

tl

regulated

to

+5

VDC

by

adjustment

of

VRl

and

appears

at

pins

1

and

2

of

I(

This

voltage

powers

ICl

and

IC3

which

control

turning

the

unit

on

and

off,

ii

also

run

to

the

2283

digital

board

via

P401

14

as

VBACK

which

pow

the

backup

memory.

1.2.3

Control

circuitry

The

operation

of

turning

the

unit

on

and

off

is

done

by

ICl

and

IC3,

tht

ICs

are

constantly

powered

by

either

the

battery

or

by

mains

regardless

whether

the

unit

is

on

or

off.

ICl

is

a

dual

D

flip-flop

that

is

configured

so

tl

it’s

Q1

output

(pinl)

will

toggle

with

each

CLK

(pin

3)

pulse

received.

1

CLK

input

to

ICl

is

driven

by

IC3

3

which

monitors

the

front

panel

POWI

button

(P401

12).

With

each

depression

of

the

front

panel

POWER

butt

3

of

IC3

will

pulse

high,

therefore

1

of

ICl

will

toggle

from

its

previc

state.

When

the

unit

is

off

pins

12

and

13

of

IC3

are

high,

therefore

11

is

lo

this

keeps

Q1

off

which

in

turn

biases

Q2

off.

With

Q2

off

IC6

receives

no

po

er

so

the

DC-DC

converter

is

inoperative.

By

pressing

the

POWER

button

f

1

of

ICl

will

toggle

low,

this

brings

IC3

11

high,

Q1

is

turned

on

biasing

(

Theory

of

OperationPower

Supply

Board

Service

Manual:

Mode

on.

With

Q2

on

IC6

is

powered

up

and

the

DC-DC

converter

turns

the

moi

on.

Pressing

the

POWER

button

again

will

turn

the

unit

off

by

causing

IC3

p

to

pulse

high

w'hich

toggles

1

of

ICl

high.

11

of

1C3

will

go

low

tur

the

unit

off,

provided

12

is

high

via

IC3

10.

If

the

OFFDIS

line

frorr

processor

is

high

then

the

monitor

will

not

shut

off

until

this

line

is

bro

low.

The

reason

for

this

is

to

ensure

that

power

remains

while

the

process(

writing

to

memory.

The

PSUST

line

informs

the

digital

board

the

status

of

the

DC-DC

con’

er,

IC3

pins

5

and

6

are

tied

to

the

gate

of

Q1

which

goes

high

while

the

ur

on,

C5

will

charge

up

through

Rll,

therefore

IC3

pin4

will

go

low.

Once

unit

is

turned

off

C5

quickly

discharges

through

Dl,

then

IC3

pin4

(PSL

goes

high.

1.2.4

Switching

regulator,

DC-DC

converter

Power

for

the

remaining

boards

in

the

monitor,

and

the

RS232

interfac

generated

by

a

switching

regulator

that

is

configured

as

a

DC-DC

conve

When

the

unit

is

turned

on

IC6

is

powered

up,

this

is

a

current

mode

p

width

modulator

which

drives

the

primary

winding

of

transformer

T2

via

The

N-channel

MOSFET

Q5

is

pulsed

by

IC6

6,

the

switching

frequent

approximately

18

KHz,

with

a

10%

duty

cycle

(=5

psec)

(the

duty

cycle

vary

with

load

requirements).

There

are

three

secondaries

on

T2.

The

-i-5

volt

digital

supply

is

gener

from

pins

5

and

6,

rectified

by

D9

and

filtered

by

C22,

Cl4,

and

L2.

Resii

R29,

R39,

R33

and

potentiometer

VR3

act

as

feedback

for

IC6

enabling

output

to

be

adjusted

and

regulated

for

-i-

5VDC.

Dual

analog

supplies

are

crated

at

pins

8

and

9

with

10

as

the

center

tap

(AGND).

Diodes

D7

D8

rectify

the

secondary

voltage

and

CIO,

Cll,

C13,

and

C15

filter

the

ou

An

isolated

supply

is

generated

at

pins

2

and

3

for

the

RS232

interface

cin

ry.

1.2.5

RS232

interface

The

RS232

interface

is

isolated

from

the

rest

of

the

circuitry,

an

isol

-I-5VDC

supply

is

generated

by

the

DC-DC

converter,

and

information

to

from

the

microcomputer

is

handled

by

four

opto-isolators.

Pins

2

and

1

transformer

T2

are

rectified

by

Dll

and

filtered

by

C23,

IC7

is

a

-i-5

regulator

for

the

isolated

portion

of

the

RS232

interface

circuitry.

The

25

D

connector

on

the

rear

panel

is

used

for

the

RS

communication,

information

from

the

D

connector

is

run

to

IC8

w

translates

the

incoming

RS232

levels

to

5

volt

logical

levels.

There

are

lines

which

are

transmitted

from

the

microcomputer

and

are

handled

by

Service

Manual:

Model

515

Theory

of

Operatlon:Dlgltal

Board

(TXO)

and

ICIO

(TXl).

The

TXO

infonnation

is

run

to

11

of

1C8,

^

infomiation

is

run

to

10

of

1C8

and

to

19

of

Jl()2

(25

D

connecto

the

rear

panel).

The

TX1I2

signal

at

19

of

J102

is

a

0-5

volt

level

si

which

is

dedicated

to

communicate

with

the

Analog

Output

Module

section

7.4).

The

outputs

of

108

14

(TXO)

and

7

(TXl)

are

transl

to

±10

volt

levels.

There

are

two

receive

lines,

RX

and

CTS.

These

signals

are

taken

in

f

the

D

connector

and

run

to

pins

13

(RXO)

and

8

(CTS)

of

1C8,

where

they

converted

to

0-5

volt

levels.

The

outputs

at

pins

12

(RX)

and

9

(CTS)

d

transistors

Q6

and

Q7

respectively.

These

transistors

drive

the

LEDs

of

I

and

IC12,

the

signals

are

transmitted

across

the

barrier

and

run

to

P401

|

(CTS)

and

6

(RX)

where

they

are

received

by

the

processor.

1.3

Digital

Board

#2283

The

processor

which

controls

the

monitor

along

with

all

of

its

support

cuitry

is

contained

on

the

digital

board.

All

of

the

timing

for

the

2288

An;

board

is

generated

on

the

2283

Digital

board

and

is

buffered

before

transr

sion

to

the

Analog

board

through

J104.

1.3.1

Microprocessor

The

processor

used

is

an

HD64180,

8

bit,

CMOS

microprocessor

(I(

The

clock

circuitry

consists

of

Cl,

C2,

and

Y1

which

develops

9.216

MHz

tween

the

XTAL

(pin

2)

and

EXTAL

(pin

3)

inputs.

This

crystal

frequenc;

divided

in

half

(4.608

MHz)

and

is

used

to

generate

the

timing

for

the

front

board

and

the

clocking

for

the

tone

generator.

The

processor

is

reset

at

power

up

by

C3,

R3,

and

D3

which

drive

schi

inverter

ICG2

3.

The

time

constant

of

C3

and

R3

will

reset

the

proce:

after

approximately

90

msec,

D3

will

prevent

any

negative

spikes

during

p(

er

down.

There

are

two

asynchronous

serial

communication

interface

channels,

first

(channel

0)

is

configured

for

2

way

communication

using

TXAO,

RX

and

CTSO,

the

second

(channel

1)

is

configured

for

transmission

only

TXAl.

The

transmit

pins

TXAO

(pin

45)

and

TXAl

(pin

48)

are

buffered

transistors

Q1

and

Q2

respectively.

The

outputs

from

the

transistors

drive

to

isolators

located

on

the

power

supply

board,

this

is

done

to

isolate

the

m

itor’s

internal

circuitry

from

the

RS232

output.

When

the

CTSO

is

high

no

c

is

transmitted

from

TXAO,

when

it

is

low

data

can

be

transmitted.

1.3.2

Memory

The

Erasable

Programmable

Read

Only

Memory

(EPROM)

is

a

27C!

(IC3).

The

ME

(Memory

Enable)

and

RD

(Read)

lines

are

ORed

through

h

Theory

of

Operation:Digital

Board

#2283

Service

Manual:

Model

pins

4,

5,

6

which

drive

the

IC’s

OE

(Output

Enable)

line

during

a

CPU

i

cycle.

The

CE

(Chip

Enable)

line

is

tied

to

address

line

A17,

this

will

en

the

line

(active

low)

in

the

address

range

of

0000H

to

0EEFH.

Provis

have

been

made

to

enable

the

use

of

a

27C101

(1Mb

EPROM)

by

bringing

dress

line

A16

to

the

EPROM

socket.

This

would

have

the

address

range

f

00000H

to

IFFFFH.

The

Random

Access

Memory

(RAM)

consists

of

two

HM62256

(:

IC6),

the

OE

(Output

Enable)

and

WE

(Write

Enable)

lines

are

commoi

both

RAMs.

The

OE

lines

are

tied

together

with

the

EPROM’s

and

there

is

activated

in

the

same

way.

The

WE

lines

are

enabled

by

the

ORed

resul

the

ME

(Memory

Enable)

and

WR

(Write)

lines

of

the

CPU,

this

ensures

the

ICs

will

be

written

to

only

at

CPU

memory

write

cycles.

The

address

coding

for

the

CE

(Chip

Enable)

lines

is

handled

by

logic

circuitry.

The

line

is

inverted

by

ICG2

10

then

ORed

with

the

A15

line

by

ICGl

pins

!

10,

then

it

is

ORed

with

the

inverted

A15

line

(ICG2

8)

by

ICGl

pins

12,

13.

This

produces

the

CSMl

(Chip

Select

Memory

1)

and

CSM2

(Chip

lect

Memory

2)

lines,

when

A17

is

high

and

A15

is

low

CSMl

will

be

sel

ed,

when

both

A17

and

A15

are

high

CSM2

will

be

selected.

The

add

range

for

IC4

is

20000H

to

27FFFH,

for

IC6

it

is

from

28000H

to

2FF1

The

decoded

CE

lines

(CSMl

and

CSM2)

are

then

individually

ORed

with

other

signal

at

ICS

pins

8,

9,

10

and

ICS

pins

11,

12,

13.

This

signal

is

the

suit

of

ORing

the

PSUST

(PSU

STatus),

which

is

low

when

power

is

on

high

when

the

unit

is

off,

and

the

RSTDSL

line

which

is

high

on

reset

only

(

pins

1,

2,

3).

As

ICS

is

powered

from

the

VBD

supply

(derived

from

Vback

supply)

it

ensures

that

the

CSMl

and

CSM2

lines

are

inhibited

f

activating

the

CE

lines

on

IC4

and

IC6

when

the

power

is

off

and

during

n

This

avoids

data

corruption

in

the

RAMs.

1.3.3

Real

Time

Clock

(RTC)

The

Real

Time

Clock

(RTC)

is

IC7

an

HD146818

RTC

chip,

its

CE

((

Enable)

line

is

driven

by

ORing

the

PSUST,

RSTDSL

at

ICS

pins

1,

2,

3

'

the

RTSO

line

at

ICS

pins

4,

S,

6.

The

RTSO

is

a

latched

output

from

the

C

the

IRQ

(Interrupt

Request)

19

of

IC7

is

connected

to

the

INT2

line

of

CPU,

this

is

a

low

priority

interrupt

source.

The

RES

of

IC7

is

connecte

the

RESOUT

line

to

ensure

that

the

RTC

does

not

generate

any

interrupts

power

up.

The

RTC

has

an

internal

multiplexed

address

and

a

bi-directional

data

which

is

controlled

through

the

R/W

(Read/Write),

AS

(Address

Strobe),

DS

(Data

Strobe)

pins.

When

R/W,

CE,

DS

inputs

are

low

the

address

pearing

on

the

data

bus

is

latched

on

the

negative

transition

of

the

AS

pin.

ta

is

written

to

the

device

in

the

same

way

except

the

AS

is

held

low

the

data

is

latched

on

the

negative

transition

of

the

DS

pin.

When

reading

(

the

R/W

is

high

and

the

data

is

read

by

the

CPU

just

before

the

nega

Service

Manual:

Model

515

Theory

of

Operation:Digital

Board

#;

transition

of

the

DS

pin.

The

RAV

of

IC7

is

connected

to

the

WR

ol

CPU,

it

is

low

during

write

cycles

and

high

during

read

cycles.

The

decoding

for

the

AS

and

DS

lines

are

handled

through

logic

circ

The

inverted

E

line

(synchronous

clock

output)

is

ORed

with

the

lOE

(In

Output

Enable)

at

ICG3

pins

1,2

to

produce

a

signal

which

controls

the

tin

of

the

AS

and

DS

signals.

This

output

is

NORed

with

the

Y1

output

of

lO

and

the

A0

line

at

ICG4

10

for

the

AS

line

and

is

active

in

the

add

range

80H,

82H

etc.

(when

A0

is

low).

The

DA

line

is

the

NORed

resul

the

Y1

of

ICG

15

and

the

inverted

A0

line

which

appears

at

ICG4

9,

th

active

in

the

address

range

81H,

83H

etc.

(when

A0

is

high).

The

timing

is

achieved

through

C5,

C6,

C7,

R5,

R6

and

Y2

which

fom

oscillator

circuit.

This

provides

the

RTC

with

a

clock

signal

from

which

a(

rate

time

can

be

continually

kept.

The

RTC

is

powered

by

the

VBD

(bac

voltage)

supply

which

keeps

the

correct

time

while

the

monitor

is

off.

If

VBD

is

removed

or

fails

the

PS

(pin22)

senses

this

through

R4,

C4,

and

the

time

will

not

be

used

since

it

is

invalid.

1.3.4

Tone

Generator

Circuit

The

tone

generator

circuitry

is

based

on

the

SN76496

tone

gener

(ICS).

The

volume

and

frequency

output

is

programmed

by

sending

coded

<

to

ICS’s

data

inputs

D7

-

D0

through

the

CPU

data

bus.

When

the

CE

(C

Enable)

and

WE

(Write

Enable)

pins

are

low

data

is

read

from

the

data

by

ICS.

This

process

takes

longer

than

the

standard

CPU

write

cycle

so

READY

line

from

ICS

is

tied

to

the

CPU’s

WAIT

line.

When

ICS

is

reac

data

the

READY

line

is

brought

low,

this

will

cause

the

CPU

to

pause

in

current

state

and

hold

the

data

on

the

data

bus.

When

the

data

has

been

i

the

READY

line

will

return

high

and

the

CPU

will

operate

as

normal.

The

and

WE

pins

are

tied

together

and

are

active

low,

this

signal

SGCS

(So

Generator

Chip

Select)

is

derived

by

GRing

the

CPU

WR

line

and

the

Y2

(

put

from

ICG15

at

ICG3

pins

8,

9,

10.

The

4.608

MHz

clock

signal

is

divided

in

half

by

ICG

10

6

and

is

c

nected

to

the

CLK

input

on

the

tone

generator.

This

frequency

is

divided

dc

by

the

tone

generator

to

obtain

the

desired

output

frequency.

To

prevent

random

noise

from

being

generated

on

power

up

the

output

from

ICG

10

is

hibited

by

the

RESET

line

which

is

connected

to

ICGlO’s

C

(clear)

input.

3

will

prevent

clock

signals

to

ICS

for

the

duration

of

the

reset

signal.

The

AUDGUT

from

ICS

is

decoupled

by

R7

and

C8

to

prevent

osci

tions.

The

output

is

then

AC

coupled

through

C9

and

fed

into

IC9

which

is

watt

audio

amplifier.

The

output

from

IC9

5

is

AC

coupled

through

two

pacitors*

in

parallel

to

J401

19

which

with

J401

20

is

run

to

the

spea

which

is

mounted

on

the

unit’s

chassis.

*On

rev

00

boards

they

are

C12A

and

CUB,

on

rev

01

boards

they

are

C13

and

C14.

Theory

of

Operation:Digital

Board

#2283

Service

Manual:

Model

1.3.5

VFD

Interface

Communication

between

the

VFD

(Vacuum

Fluorescent

Display)

and

CPU

occurs

at

J403,

there

are

two

control

lines

(WRDSP

and

PROBUS)

al

with

the

CPU

data

bus

D0-D7.

The

WRDSP

line

controls

the

programming

the

display,

when

this

line

is

low

(1CG3

6)

the

data

on

the

data

bus

is

i

by

the

display

module.

The

PROBUS

is

then

brought

low

by

the

display

rr

ule

while

it

processes

the

infomiation

sent

to

it.

This

line

is

read

by

the

C

via

ICG

18

before

any

data

is

sent

to

the

display,

if

the

line

is

low

no

data

be

sent,

it

will

be

checked

until

it

is

high

which

indicates

data

can

be

sent.

The

LNEST

line

(Line

Status)

indicates

whether

the

monitor

is

running

of

the

line

supply

or

off

of

battery

power.

When

this

line

is

high

the

monitc

hooked

up

to

the

mains

supply

and

a

green

LED

on

the

front

panel

is

illumi

ed.

LNEST

is

also

connected

to

A7

of

ICG

18

so

the

CPU

can

read

the

st;

of

this

signal.

The

RESET

line

is

brought

to

the

display

module

to

blank

display

during

power

up.

1.3.6

Keypanel

Interface

The

keypanel

interfaces

with

the

CPU

via

connector

J2.

All

of

the

keys

the

front

panel

are

momentary

normally

open

switches

which

short

to

gro

upon

depression

(J2

1).

The

inputs

from

the

keypanel

SW1-SW6

are

I

high

by

resistor

pack

RPGl

and

feed

ICG

18,

with

the

exception

of

ON/(

key

which

goes

directly

to

the

power

supply

board

to

turn

the

unit

on

and

off.

1.3.7

Front

End

Timing

All

of

the

timing

waveforms

for

the

2288

front

end

board

are

derived

f

the

logic

circuitry

on

the

2283

digital

board.

The

CPU

clock

line

(CLK)

is

di'

ed

in

half

by

ICG

10

to

produce

a

2.304

MHz

signal.

The

divi

that

signal

by

50,

this

is

done

by

ICG

13,

ICG8

and

the

other

half

of

ICC

The

negative

edge

of

the

2.304MHz

signal

increments

ICG

13,

when

Ql,

Q6

are

all

high

(occurs

after

49

counts)

8

of

ICG8

will

go

high.

This

si|

appears

at

the

“D”

input

of

ICG

10

12

and

is

transferred

to

the

RESET

on

ICG

13

on

the

going

pulse

of

the

2.304

MHz

signal

(ICG

10

11).

This

will

reset

ICG13

causing

the

Ql,

Q5,

Q6

outputs

to

reset

to

“0”,

output

of

ICG8

8

will

go

low,

and

this

low

will

be

transferred

to

the

REJ

of

ICG

13

(on

positive

clock

signal

to

ICG

10)

enabling

it

to

begin

coun

again.

The

resulting

output

is

49

clock

cycles

+

1

clock

cycle

during

reset

wl

gives

the

required

count

of

50,

the

output

frequency

is

therefore

46.08

KHz.

The

46.08

KHz

signal

drives

ICG14

which

is

negative

edge

triggered.

A

two

pulses

the

Q2

output

of

ICG14

will

go

high,

this

will

cause

ICGll

!

reset

ICG

14

on

the

edge,

this

sends

the

Q2

output

low.

The

set

signal

will

be

removed

on

the

edge

and

incrementing

will

j

ceed

on

the

following

negative

edge,

this

results

in

a

pulsed

output

at

ICC

Service

Manual:

Model

515

Theory

of

Operation:Digital

Board

9

of

15.36

KHz.

This

65.1iisec

pulse

drives

ICG16

which

sends

each

o

outputs

high

sequentially

from

Q0-Q9

with

each

input

pulse,

then

continu

recycles.

This

results

in

each

Q

output

of

ICG

16

producing

a

positive

g(

pulse

of

65.1|isec

every

651|isec.

The

QO

and

Q5

outputs

are

inverted

by

ICG7

pins

2

and

4,

these

out

drive

the

red

and

infrared

LEDs

on

the

front

end

board

(LEDl

and

LI

lines).

The

QO

and

Q5

lines

are

NANDed

together

with

the

Q1

output

f

ICG14

and

outputs

appear

at

ICG6

pins

6

and

8.

This

results

in

a

nega

pulse

of

2L7psec

which

occurs

in

the

middle

of

LEDl

and

LED2

signals.

Q3

and

Q8

outputs

of

ICG

16

are

ORed

at

ICG5

and

the

result

is

inverted

1CG7

pm

6,

this

signal

drives

the

shorting

FETs

on

the

front

end

board

(I

This

signal

turns

the

grounding

FETs

on

the

front

end

board

on

before

e

LED

drive

signal.

The

Q3

output

from

ICG

17

is

also

ORed

with

the

Q3

and

outputs

of

ICG

16

at

ICG5,

this

is

done

so

that

the

FZ

line

can

be

overrid

and

held

on

for

front

end

calibration

purposes.

1.3.8

Front

End

Board

Interface

The

Electrically

Erasable

Programmable

Read

Only

Memory

(E^PROM

controlled

through

ICG17

and

half

of

ICG20.

The

EESK

(EEPROM

Se

Clock),

EECS

(EEPROM

Chip

Select)

and

the

EEDI

(EEPROM

Data

lines

are

programmed

by

ICG

17

and

the

EEDO

(EEPROM

Data

Out)

is

r

at

bit

0

of

the

data

bus

by

ICG20.

The

SAl

and

SA2

lines

are

controlled

ICG

17,

these

lines

demultiplex

the

red

and

infrared

AC

signals,

and

discha

the

AC

coupling

capacitors

(FILTIN

line)

on

the

front

end

board.

One

half

of

ICG20

reads

data

from

the

front

end

board,

it

reads

the

El

ROM’s

data

out

line

and

the

red

and

infrared

status

lines

(STLEDl

;

STLED2).

The

other

half

is

used

as

a

static

address

bus

to

the

front

(

board,

this

is

used

to

reduce

noise

generated

by

the

CPU’s

address

and

d

busses

on

the

front

end

board.

It

works

in

such

a

way

that

the

DP0-DP7

;

AP0-AP2

lines

are

always

at

a

high

impedance

state

and

the

PWR

line

is

ways

at

a

logic

high

unless

these

lines

are

actually

being

used

to

transfer

d

to

or

from

the

front

end

board.

All

of

the

front

end

peripherals

are

within

the

dress

range

of

A0-B1H

as

shown

in

the

following

table.

Addres.s

I/O

E

WR

RD

E

Name

Function

80-87

88

89

90-97

98-9F

A0-A7

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

1

X

1

X

WRDSP

Display

Module

Write

Enable

AS

RTC

Address

Strobe

DS

RTC

Data

Strobe

sees

Sound

Generator

Chip

Select

Led

Status/EEPROM

0/P

(ICG20)

—

8

bit

I/P

port

(ICG

18

enable)

—

8

bit

latch

(ICG

17

enable)

—-

Clear

INT0

interrupt

WRADC

Start

conversion

ADC

chl-8

RDADC

Read

ADC

chl-8

Theory

of

Operation:Analog

Board

#2288

Service

Manual:

Model

1.4

1.4.1

A0-B7

0

X

Static

addr

bus

enable

(1/2

1CG2(

A0-B7

0

X

Static

data

bus

enable

(ICG

19

enl

A0-B7

0

X

1

PWR

Static

WR

line

A8-AB

0

X

CSGAN

Gain/offs

DAC

chip

select

AC-AF

0

X

UPOFF

Gain/offs

DAC

output

update

enb

B0-B1

0

X

CSLED

(0-logic

low;

1-logic

high;

X-don’tcare)

LED

drive

DAC

chip

select

The

Y4,

Y5,

Y6

outputs

of

ICG

15

that

correspond

to

I/O

addresses

for

LED

drive

DAC,

the

gain/offset

DAC

and

the

ADC

are

NANDed

at

ICG6

]

1,

2,

13,

the

output

is

then

inverted

by

ICG7

11

to

produce

a

signal

controls

the

enable

pins

of

ICG

19

and

half

of

ICG20

(this

allows

data

from

address

and

data

busses

to

be

transferred).

This

signal

is

also

ORed

with

CPU’s

WR

line

and

inverted

E

line

at

ICG9

to

produce

the

PWR

(static

line)

when

writing

data

to

the

front

end.

The

direction

of

the

data

flow

is

(

trolled

by

connecting

the

CPU’s

RD

line

to

the

DIR

line

of

ICG

19.

When

RD

line

is

low

(CPU

read

cycles)

the

data

flow

is

from

the

B

to

A

pin?

ICG

19,

when

RD

is

high

data

flows

in

the

opposite

direction.

Analog

Board

#2288

The

drive

circuitry

for

the

REDLED

and

IRLED

along

with

the

detec

and

decoding

circuitry

is

found

on

the

2288

analog

board.

The

processor

c

municates

with

the

analog

board

through

a

40

conductor

ribbon

cable

locate

El.

All

the

timing

signals

and

power

lines

are

run

through

the

ribbon

cabL

well.

The

sensor

connects

to

the

analog

board

at

J405

and

is

run

to

the

f

panel

connector

by

a

cable

assembly.

Probe

Detection

The

monitor

recognizes

that

a

probe

is

connected

by

monitoring

pins

5

6

of

J405

(REDLED

and

IRLED

cathodes).

A

dual

comparator

IC23

has

positive

inputs

tied

to

1/2

VLED

(=2.4

VDC).

The

negative

inputs

of

IC23

tied

to

the

REDLED

cathode

(pin

2)

by

R64,

and

to

the

IRLED

cathode

6)

by

R65.

Resistors

R66

and

R67

hold

the

negative

inputs

low

when

no

pi

is

connected.

When

the

probe

is

connected

both

pins

2

and

6

are

brought

1

which

brings

the

outputs

of

both

comparators

low.

When

the

probe

disconnected

pins

2

and

6

are

at

ground

potential

and

the

outputs

are

high

to

pull-up

resistors

R48

and

R47.

This

will

signal

the

processor

to

flas

“CONNECT

87XX

PROBE”

message

on

the

display.

If

either

of

the

LEDs

malfunctions

and

causes

the

output

of

a

comparatc

remain

high

while

the

other

goes

low

then

an

error

message

will

be

displa;

A

malfunction

with

the

IRLED

will

flash

“PROBE

ERROR-04”,

a

malfunc

with

the

REDLED

will

flash

“PROBE

ERROR-02”.

The

point

of

pins

3

and

:

IC23

is

also

monitored

by

the

A/D

converter

ICl

1,

if

IC24

were

to

malfunc

or

if

El

were

to

blow

then

“MONITOR

ERROR-0001”

would

be

displayed.

Service

Manual:

Model

515

Theory

of

Operation

:Analog

Board

#2

Resistors

R66

and

R67

along

with

C34

and

C35

form

low

pass

filters

to

ter

out

any

noise

that

may

falsely

trigger

the

comparators.

1.4.2

Power

Supplies

Three

separate

voltages

are

run

to

the

2288

analog

board.

A

digita

5VDC

(VDD)

and

dual

12

volt

analog

supplies

(+VA,

-VA).

The

dij

ground

(DGND)

and

the

analog

ground

(AGND)

are

connected

at

only

point

which

is

at

ICl

1

pins

8

and

28.

The

dual

analog

supplies

(+VAF,

-V.

are

filtered

by

L2,

L3,

C90,

and

C91,

these

supply

most

of

the

analog

circu

on

the

board

with

the

following

exceptions.

Voltage

regulator

IC19

develops

+5

volts

(+5VA)

from

the

+VAF

sup

this

is

for

IC12

which

drives

the

inputs

of

ICll,

this

is

done

in

order

to

pre^

over

voltage

damage

to

the

inputs

of

ICll.Voltage

regulator

IC24

develops

volts

VLED

and

VOPP

from

+VA.

The

VOPP

voltage

is

taken

directly

fi

the

output

of

IC24

and

powers

1C23

(LM393

dual

comparator).

The

VLEE

used

as

the

power

supply

for

the

RED

and

IR

LEDs.

Fuse

FI

protects

aga

short

circuits

or

excessive

power

consumption

by

the

LEDs,

LI

and

C38

ft

the

output

from

high

frequency

noise

created

from

the

fast

switching

of

LEDs.

The

dual

analog

supplies

4-VAF

and

-VAF

are

further

filtered

by

R

C96

for

+VA21,

and

R75,

C97

for

-VA21

to

power

IC21

which

handles

the

c

ical

front

end

circuitry.

1.4.3

Reference

Voltages

There

are

two

reference

voltages

on

the

2288

analog

board.

A

-1.23

V

potential

is

created

by

D5

and

R24,

it

appears

on

5

of

ICl5.

This

amplified

by

ICl5

7

with

a

gain

of

3.42

created

by

R25

and

R28,

;

appears

as

-4.2

VDC

(VREF-).

Capacitors

C17

and

Cl8

help

stabilize

reference

voltage,

C21

is

used

to

filter

noise

from

the

output

of

IC15

7.

"

negative

reference

voltage

(VREF-)

is

applied

to

ICl5

2

which

configured

as

an

inverting

unity

gain

amplifier

(R26

and

R27

set

the

gain

to

therefore

+4.2

VDC

appears

at

1

of

ICl5

(VREF+).

1.4.4

E^PROM

The

electrically

erasable

programmable

read

only

memory

(E^PRO

ICIO

is

used

to

store

offset

values

for

the

Ir

and

Red

channels

obtained

dur

a

factory

front

end

calibration.

It

also

stores

factory

programmed

battery

mo

toring

voltage

values.

This

device

can

store

64

separate

16

bit

values,

it

is

p

grammed

serially

through

pins

D1

(Data

In),

CS

(Chip

Select),

SK

(Sei

Clock),

and

DO

(Data

Out).

The

device

is

selected

by

bringing

the

CS

line

high,

then

the

first

three

I

on

the

DI

line

indicate

the

function

required

(read,

write,

or

erase).

Once

function

is

determined

the

bits

indicate

the

address

of

the

operati

Theory

of

Operation:Analog

Board

#2288

Service

Manual;

Model

(00H

-

3FH).

If

writing

then

the

bits

sent

is

the

value

to

be

sto

the

CS

line

is

taken

low

then

high

and

the

DO

line

is

scanned

until

a

high

1

is

read.

This

indicates

that

the

data

has

been

received

and

the

can

begin.

If

the

read

operation

was

selected

the

data

would

be

present

at

DO

line

once

the

address

was

sent.

1.4.5

LED

Drive

circuitry

The

intensities

of

the

REDLED

and

IRLED

are

controlled

by

the

proce

through

the

use

of

IC20,

an

8

bit

dual

digital

to

analog

converter

(DAC).

“A”

DAC

corresponds

to

the

REDLED

and

is

selected

when

6

is

(DACA).

The

“B”

channel

corresponds

to

the

IRLED

and

is

selected

bringing

6

high

(DACB).

Steady

state

DC

output

voltages

which

repre

the

digital

inputs

are

developed

at

IC22

1

for

the

REDLED

and

IC22

p

for

the

IRLED.

Because

both

DACs

use

the

same

reference

voltage

(VRI

the

output

voltage

swing

from

00H

to

FEH

is

the

same

for

each

(0

-

+4.

VDC).

The

voltages

that

drive

the

LEDs

are

pulsed,

this

is

controlled

by

h

pins

9,

10,

and

11

for

the

REDLED,

and

pins

14,

15,

and

16

for

the

IRL

When

IC25

9

goes

low

the

switch

between

pins

10

and

11

is

closed,

voltage

at

IC22

1

is

now

present

at

IC25

10

until

9

goes

high.

"

pulsing

is

controlled

by

the

LEDl

line.

The

same

applies

for

the

IRLED

cl

nel,

when

16

of

IC25

is

low

the

switch

from

pins

14

to

15

is

closed

and

voltage

at

IC22

8

is

present

at

15

of

IC25.

The

IRLED

pulsing

is

(

trolled

by

the

LED2

line.

Resistors

R53,

R54,

R55,

and

R56

form

a

voltage

vider

for

each

channel

to

bring

the

maximum

pulse

voltage

down

from

4.1

\

to

1

volt.

The

pulses

at

the

voltage

divider

of

R53

and

R55

drives

5

of

IC22

wl

with

pins

6,

7,

and

Q7

is

configured

as

a

unity

gain

amplifier.

The

voltage

appears

at

5

of

IC22

will

appear

at

the

junction

of

R60

and

the

emitte

Q7,

the

maximum

of

which

will

be

1

volt.

Since

the

collector

of

Q8

is

tied

to

cathode

of

the

REDLED,

when

Q7

is

pulsed

by

IC22

7

the

REDLED

conduct.

Resistor

R60

limits

the

current

through

the

LED

to

303

mA

volt/3.3^2).

Diode

D7

is

used

to

limit

any

negative

offset

that

may

be

ir

duced

by

IC22

to

-0.7

volts.

Pins

12,

13,

14

of

IC22

and

Q8

form

the

unit

j

amplifier

for

the

IRLED

channel.

The

operation

of

the

circuit

is

the

same

as

the

RED

channel.

Resistor

R61

limits

the

current

through

the

IRLED

to

mA

(1

volt/5.6Q)

and

D8

protects

against

any

negative

offset.

1.4.6

Photodiode

Return

Path

The

photodiode

in

the

sensor

is

connected

to

pins

9

and

10

of

IC21

whic

configured

as

a

current

to

voltage

convertor.

When

light

strikes

the

photodi

it

induces

a

small

current

to

flow

from

anode

to

cathode,

this

creates

a

cur

flow

into

10

of

IC21

(non-inverting

input).

This

current

flow

will

produc(

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