NXP Semiconductors KITPF5030FRDMEVM User manual

UM11853
KITPF5030FRDMEVM evaluation board
Rev. 1.0 — 7 March 2023 User manual
Document information
Information Content
Keywords PF5030, KITPF5030FRDMEVM, KL25Z, I2C, spf-53090
Abstract The KITPF5030FRDMEVM provides flexibility to explore all the features of the device and make
measurements on the main part of the application.

NXP Semiconductors UM11853
KITPF5030FRDMEVM evaluation board
Rev Date Description
v.1.0 20230307 •Initial release
Revision history
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Important notice
NXP provides the enclosed product(s) under the following conditions:
This evaluation kit is intended for use of ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES
ONLY. It is provided as a sample IC pre-soldered to a printed circuit board to make it easier to access inputs,
outputs, and supply terminals. This evaluation board may be used with any development system or other
source of I/O signals by simply connecting it to the host MCU or computer board via off-the-shelf cables. This
evaluation board is not a Reference Design and is not intended to represent a final design recommendation for
any particular application. Final device in an application will be heavily dependent on proper printed circuit board
layout and heat sinking design as well as attention to supply filtering, transient suppression, and I/O signal
quality.
The goods provided may not be complete in terms of required design, marketing, and or manufacturing related
protective considerations, including product safety measures typically found in the end product incorporating the
goods. Due to the open construction of the product, it is the user's responsibility to take any and all appropriate
precautions with regard to electrostatic discharge. In order to minimize risks associated with the customers
applications, adequate design and operating safeguards must be provided by the customer to minimize inherent
or procedural hazards. For any safety concerns, contact NXP sales and technical support services.
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1 Introduction
The KITPF5030FRDMEVM board user manual is intended for the engineers involved in the evaluation, design,
implementation, and validation of PF5030 Configurable Power Management IC.
The KITPF5030FRDMEVM enables development on PF5030 family of devices. The kit can be connected to the
NXP GUI software, which allows you to explore registers, try OTP configurations, and burn the part.
The devices can be placed and removed easily from the board by using the socket. This board supports
PF5030 family of devices.The board delivered comprises a soldered device with empty OTP content in order
to leave the opportunity to the user to burn the OTP configuration. The board contains a superset device
PPF5030BMDA0ES, allowing tests on all the PF5030 derivatives. Each device OTP can be burned twice, which
provides flexibility.
2 Finding resources and information on the NXP website
NXP Semiconductors provides online resources for this evaluation board and its supported devices on http://
www.nxp.com.
The information page for KITPF5030FRDMEVM board is available at www.nxp.com/KITPF5030FRDMEVM.
The information page provides overview information, documentation, software and tools, parametric data,
ordering information and a Getting Started tab. The Getting Started tab provides quick-reference information
applicable to using the KITPF5030FRDMEVM board, including the downloadable assets referenced in this
document.
The information page for "NXP GUI for Automotive PMIC Families" is at http://www.nxp.com/NXP GUI for
Automotive PMIC Families. The information page provides overview information, documentation, downloads,
and development tools.
Collaborate in the NXP community
In the NXP community, you can
•Share ideas and tips
•Ask and answer technical questions
•Receive input on just about any embedded design topic
The NXP community is at http://community.nxp.com.
3 Getting ready
Working with the KITPF5030FRDMEVM requires the kit contents, additional hardware, and a Windows PC
workstation with installed software.
3.1 Kit contents
•Assembled and tested KITPF5030FRDMEVM connected to a FRDM-KL25Z in an anti-static bag
•2 ft or 3 ft USB-STD A to USB-B-mini cable
•1x Pluggable terminal block, two positions, straight, 3.81 mm pitch
•3x Pluggable terminal block, three positions, straight, 3.81 mm pitch
•Jumpers mounted on board
•Quick Start Guide
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3.2 Additional hardware
In addition to the kit contents, the following hardware is necessary or beneficial when working with this kit.
•One or two power supplies with a range from 3.3 V to 5.0 V, and a current limit set initially to 1.0 A
3.3 Windows PC workstation
This evaluation board requires a Windows PC workstation. Meeting these minimum specifications should
produce great results when working with this evaluation board.
•USB-enabled computer with Windows 7 or Windows 10
3.4 Software
Installing software is necessary to work with this evaluation board. All listed software is available on the
evaluation boards information page.
•www.nxp.com/KITPF5030FRDMEVM
•NXP GUI for automotive PMIC families - latest version
4 Getting to know the hardware
The KITPF5030FRDMEVM provides flexibility to explore all the features of the device and make measurements
on the main part of the application. In combination with the FRDM-KL25Z MCU board, the NXP GUI software
allows access to the registers in read and write mode. All regulators are accessible through connectors. DC-
DC switching nodes and other nonuser signals are mapped on test points. Digital signals (I2C, RSTB) are
accessible through connectors. Pin PWRON has a switch to control them. A supply switch is available to power
on or off the device.
The main purpose of this kit is to burn the OTP configuration.The main purpose of this kit is to evaluate PF5030
in automotive applications. The device always starts loading the fused configuration (OTP) (that may be
blank) to the mirror registers, then the user can override the mirrors using Emulation mode. The device can be
programmed/fused two times. This board is able to fuse the OTP without any extra tools or board. In Emulation
mode, as long as the power is supplied, the board configuration stays valid. However, the main and fail-safe
configurations are lost when the device restarts or goes into deep fail-safe (DEEP-FS) state, because OTP is
reloaded and overwrite the mirrors content.
Note: Due to the socket, this kit is not optimized for performance measurement or current higher than 1.0 A.
4.1 Kit overview
The KITPF5030FRDMEVM is a hardware evaluation tool that allows OTP burning. Due to the socket,
PF5030 part can be configured without the need to solder it. Devices can be programmed two times.The
KITPF5030FRDMEVM is a hardware evaluation tool that allows performance test. PF5030 can be evaluated
with this board because it is populated with a superset part. The PPF5030BMDA0ES part soldered on the board
can be fused twice.
An Emulation mode is possible to test as many configurations as needed. From USB voltage, an external DC-
DC provides VDDIO_SEL voltage with a choice of 1.8 V, 3.3 V (default), or 5.0 V. Furthermore, another external
DC-DC generates the OTP programming voltage (7.95 V) without any need for an external power supply.
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4.2 KITPF5030FRDMEVM features
•VIN power supply connector (1x or 2x 3.3 V to 5.0 V)
•BUCK1 and BUCK2: 0.7 V to 1.5 V up to 1.0 A (socket limit)
•BUCK3: 1.0 V to 3.3 V up to 1.0 A (socket limit)
•LDO1 and LDO2: 1.5 V to 5.0 V
•PWRON switch
•FS0B external safety pin
•Embedded USB connection for easy connection to software NXP GUI (access to I2C bus, IOs, RSTB, FS0B,
INTB, debug, AMUX_OUT, regulators, register access, OTP emulation, and OTP programming)
•LEDs that indicate signals and regulator status
•Support OTP fuse capabilities
•Voltage monitoring jumper setting
4.3 Schematic, board layout, and bill of materials
The schematic, board layout, and bill of materials for the KITPF5030FRDMEVM board are available at
www.nxp.com/KITPF5030FRDMEVM.
4.3.1 VMON board configuration
The VMON configuration is highly dependent on the use case. This kit is delivered with a default configuration.
The user can assign VMON_EXT differently to address the use case using J4 and J7 connectors shown in
Figure 1. J7 is used to select the VMON_EXT (VMON0) external resistor divider to monitor 3.3 V or 5.0 V. J4
is used to connect the VMON_EXT external resistor divider input VMON_EXT_INPUT to an external voltage,
VIN_3V3, or VIN_5V. By default, VMON_EXT is monitoring VIN_3V3.
aaa-048954
R27
37.4 kΩ
1 2
VMON_EXT
3
J7
HDR_1X3
J4
VMON_EXT_INPUT
VMON_EXT resistor bridges PF5030 Signals
3.3 V to 0.8 V
resistor bridge
5 V to 0.8 V
resistor bridge
1
R29
12 kΩ
GND GND
R28
63.4 kΩ
3
2
4
6
8
10
12
14
16
5PWRON
VDDIO_EXT
VDDIO
I2C_SCL
I2C_SDA
VIN_3V3
VIN_5V
VMON_EXT_INPUT
DBG
AMUX_OUT 7
9
11
13
15
Figure 1. VMON_EXT assignment (VIN_3V3 default)
By default, BUCK2_FB (VMON2) is connected to BUCK2 though SJ2. However, When BUCK2 is disabled or
used in multiphase with BUCK1, BUCK2_FB can be connected to an external voltage. R17 and SJ4 must be
open in this case and the internal DAC must be configured to the voltage monitoring target.
By default, LDO1_MON (VMON4) and LDO2_MON (VMON5) pins are tied to LDO1 and LDO2, respectively.
LDO1_MON and LDO2_MON can be used to monitor an external voltage using test points TP25 (LDO1_MON)
and TP26 (LDO2_MON). Solder joints SJ12 and/or SJ13 must be opened in this case. Figure 2 shows the
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corresponding part of the schematic. The internal resistors dividers can be configured to select the voltage
monitoring target.
aaa-048933
3
2
LDO1_OUT LDO1 LDO1_MON
TP25
U1
LDO1_MON 1 2
SJ12
37
38
LDO2_OUT LDO2
LDO2_MON 1 2
SJ13
LDO2_MON
TP26
Figure 2. LDO1_MON and LDO2_MON input configuration
4.3.2 I2C
The I2C bus is connected to KL25Z MCU to communicate with NXP GUI. Another MCU can be connected to
the I2C bus on J4 connector, but R58 and R59 must be removed. In addition to this change, make sure that the
VDDIO voltage domain and ground are the same on MCU side and KITPF5030FRDMEVM side.
4.3.3 VDDIO
The VDDIO pin is powered through VDDIO net and is used to supply internal buffers and I2C communication.
The selection of VDDIO is made using R1, R2, R5, R7, and R9 resistors as shown in Figure 3. By default, an
external LDO is provided to feed VDDIO through the VDDIO_SEL net.
aaa-048939
C74
0.1 µF
GND
VDDIO
R5
0 Ω
VDDIO_SEL
R7
0 Ω
DNP
VDDIO_EXT
R9
0 Ω
DNP
VIN_3V3
R2
0 Ω
DNP
LDO1
R1
0 Ω
DNP
LDO2
Figure 3. VDDIO selection
The I2C is compatible with 1.8 V, 3.3 V, and 5.0 V, therefore VDDIO_SEL voltage is configurable between 1.8 V,
3.3 V, or 5.0 V using SJ8, SJ9, and SJ10 connectors (3.3 V by default) shown in Figure 4.
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aaa-048940
P5V_KL25Z 1 2
SJ8
U11
C50
1.0 µF
R106
0 Ω
DNP GND
Closed
1 2
SJ9
5 V
Open
C67
10 nF
DNP
NCV8537MNADJR2G
VIN_5V
GND
GND GND
VDDIO_SEL
R80
191 kΩ
3.3 V
R88
115 kΩ
R105
0 Ω
C51
2.2 µF
GND
R109
71.5 kΩ
1.8 V
2
1
SJ10 Open
8
6
N
C
SD
10
VIN2
9 1
3
VIN1
For VDDIO_SEL 1.8 V:
For VDDIO_SEL 3.3 V:
For VDDIO_SEL 5 V:
Close SJ8, SJ10 and Open SJ9
Close SJ8 and Open SJ9, SJ10
Close SJ9 and Open SJ8
VOUT1
VDDIO
5
PWRG
2VOUT2
GND
EPAD
7
4 11
N
R
ADJ
Figure 4. VDDIO_SEL supply voltage selection
4.4 Kit featured components
Figure 5 identifies important components and Table 1 provides details.
Figure 5. Evaluation board featured components location
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Number Description
1 VIN_5V and VIN_3V3 power supply input
3 VIN three position switch
•Left position: VIN from USB
•Middle position: board not supplied
•Right position: VIN from J1
4 BUCK1/2 regulators output
5 BUCK3 regulator output
6 LDO1/2 regulators output
7 USB connectors (OpenSDA for MCU flash; KL25Z for NXP GUI control)
8 Debug connectivity. Access to PF5030 signals
9 PWRON switch
10 VMON_EXT resistor bridge configuration (choice between monitoring 3.3 V or 5.0 V)
11 OTP mode switch
12 DBG pin to ground if unplugged
13 BUCK1 inductor current measurement jumper
14 BUCK2 inductor current measurement jumper
15 BUCK3 inductor current measurement jumper
16 KL25Z freedom board connectors
17 VLED supply configuration
Table 1. Evaluation board featured components location
4.4.1 Connectors
Figure 6 shows the location of connectors on the board.
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Figure 6. Evaluation board connectors location
4.4.1.1 VIN connector (J1)
Schematic label Signal name Description
J1-1 VIN_5V 5 V voltage supply input
J1-2 VIN_3V3 3.3 V voltage supply input
J1-3 GND Ground
Table 2. VIN_5V and VIN_3V3 connector (J1)
4.4.1.2 Output power supply connectors
Schematic label Signal name Description
J5-1 LDO2 LDO2 regulator output
J5-2 LDO1 LDO1 regulator output
J5-3 GND Ground
Table 3. LDO1/2 connector (J5)
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Schematic label Signal name Description
J6-1 BUCK2 BUCK2 regulator output
J6-2 BUCK1 BUCK1 regulator output
J6-3 GND Ground
Table 4. BUCK1/2 connector (J6)
Schematic label Signal name Description
J8-1 BUCK3 BUCK3 regulator output
J8-2 GND Ground
Table 5. BUCK3 connector (J8)
4.4.1.3 Debug connector (J4)
Schematic label Signal name Description
J4-1 n.c. Not connected
J4-2 VDDIO_EXT External VDDIO voltage supply
J4-3 INTB Interrupt output pin (active low)
J4-4 n.c. Not connected
J4-5 PWRON PWRON input pin
J4-6 I2C_SCL I2C serial clock
J4-7 AMUX_OUT Analog multiplexer output
J4-8 I2C_SDA I2C serial data
J4-9 n.c. Not connected
J4-10 VIN_3V3 VIN_3V3 voltage supply
J4-11 n.c. Not connected
J4-12 VMON_EXT_INPUT VMON_EXT voltage divider input
J4-13 n.c. Not connected
J4-14 VIN_5V VIN_5V voltage supply
J4-15 n.c. Not connected
J4-16 GND Ground
Table 6. Debug connector (J4)
4.4.1.4 FRDM-KL25Z board connectors
Schematic label Signal name Description
J1-1 to J1-9 n.c. Not connected
J1-6 INTB_MCU Interruption (active low-logic level)
J1-7 n.c. Not connected
J1-8 RSTB_MCU Reset (active low-logic level)
Table 7. FRDM-KL25Z safety output connector (J1)
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Schematic label Signal name Description
J1-9 to J1-11 n.c. Not connected
J1-12 FS0b_MCU Fail-safe (active low-logic level)
J1-13 to J1-16 n.c. Not connected
Table 7. FRDM-KL25Z safety output connector (J1)...continued
Schematic label Signal name Description
J2-1 to J2-13 n.c. Not connected
J2-14 GND Ground
J2-15 to J2-17 n.c. Not connected
J2-18 I2C_SDA_MCU I2C serial data line
J2-19 n.c. Not connected
J2-20 I2C_SCL_MCU I2C serial clock line
Table 8. FRDM-KL25Z I2C connector (J2)
Schematic label Signal name Description
J10-1 BUCK2_ADC BUCK2 regulator output to KL25Z ADC
J10-2 DBG_ADC DBG pin voltage to KL25Z ADC
J10-3 BUCK1_ADC BUCK1 regulator output to KL25Z ADC
J10-4 AMUX_ADC AMUX pin to KL25Z ADC
J10-5 BUCK3_ADC BUCK3 regulator output to KL25Z ADC
J10-6 LDO1_ADC LDO1 regulator output to KL25Z ADC
J10-7 n.c. Not connected
J10-8 LDO2_ADC LDO2 regulator output to KL25Z ADC
J10-9 n.c. Not connected
J10-10 VIN_ADC VIN pin voltage to KL25Z ADC
J10-11 n.c. Not connected
J10-12 VDDIO_ADC VDDIO pin voltage to KL25Z ADC
Table 9. FRDM-KL25Z ADC connector (J10)
Schematic label Signal name Description
J14-1 to J14-3 n.c. Not connected
J14-4 P3V3_KL25Z 3.3 V generated from KL25Z
J14-5 to J14-7 n.c. Not connected
J14-8 P3V3_KL25Z 3.3 V generated from KL25Z
J14-9 n.c. Not connected
Table 10. FRDM-KL25Z supply connector (J14)
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Schematic label Signal name Description
J14-10 P5V_KL25Z 5.0 V generated from USB
J14-11 n.c. Not connected
J14-12 GND Ground
J14-13 n.c. Not connected
J14-14 GND Ground
J14-15 n.c. Not connected
J14-16 n.c. not connected
Table 10. FRDM-KL25Z supply connector (J14)...continued
Schematic label Signal name Description
KL25Z NA USB connector used to communicate with the PF5030 part
OpenSDA NA USB connector used to flash the KL25Z MCU
Table 11. FRDM-KL25Z USB connectors
4.4.2 Test points
Figure 7 shows test points that provide access to various signals to and from the boards.
Figure 7. Evaluation board test points
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Test point name Signal name Description
TP7 RSTB Reset pin (active low)
TP8 AMUX Analog multiplexer output
TP9 FS0B Fail-safe pin (active low)
TP10 INTB Interruption pin (active low)
TP12 PGOOD Power good pin (active high)
TP13 BUCK1 BUCK1 regulator output
TP15 BUCK2 BUCK2 regulator output
TP17 BUCK3 BUCK3 regulator output
TP18 LDO1 LDO1 regulator output
TP20 LDO2 LDO2 regulator output
TP22 VIN_5V VIN pin voltage
TP23 VIN_3V3 BUCK1/2_IN pin voltage
TP25 LDO1_MON LDO1_MON pin voltage
TP26 LDO2_MON LDO2_MON pin voltage
TP11, TP14, TP16,
TP19, TP21
GND Ground
Table 12. Evaluation board test points description
4.4.3 Jumpers
Figure 8 shows jumper locations for board configuration.
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Figure 8. Evaluation board jumpers location (with default position)
Name Function Pin number Description
J3 Apply voltage to DBG pin 1−2 Either 4.5 V (DBG mode) or 7.95 V (OTP / test mode). See SW1 position
10−12 VIN_3V3J4 VMON_EXT input selection
12−14 VIN_5V
1−2 VIN_3V3J7 VLED selection
2−3 P3V3_KL25Z
1−2 Monitors 3.3 VJ9 VMON_EXT resistor bridge
selection 2−3 Monitors 5.0 V
J10 FS0B pull-up jumper 1−2 FS0B pull-up connection to VDDIO or another rail
JP1 BUCK1 inductor jumper 1−2 BUCK1 inductor current measurement
JP2 BUCK2 inductor jumper 1−2 BUCK2 inductor current measurement
JP3 BUCK3 inductor jumper 1−2 BUCK3 inductor current measurement
Table 13. Evaluation board jumpers description
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4.4.4 LED signaling
Figure 9 shows the LEDs provided as visual output devices for the evaluation board:
Figure 9. Evaluation board LED signaling location
Label Name Color Description
D2 RSTB Red RSTB asserted (low-logic level)
D3 FS0B Red FS0B asserted (low-logic level)
D4 INTB Red INTB asserted (low-logic level)
D5 PGOOD Green PGOOD released
D6 LDO2 Green LDO2 ON
D7 LDO1 Green LDO1 ON
D8 BUCK3 Green BUCK3 ON
D9 BUCK2 Green BUCK2 ON
D10 BUCK1 Green BUCK1 ON
D11 VIN_5V Green VIN_5V ON
D12 P3V3_KL25Z Green P3V3_KL25Z ON
D14 DBG ≥ 7.85 V Blue DBG pin voltage ≥ 7.85 V (OTP programming)
D15 VLED Green VLED ON
Table 14. Evaluation board LED signaling description
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4.4.5 Switches
Figure 10 and Figure 11 show switches locations for board operation.
Figure 10. Switches location top
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Figure 11. Switches location bottom
Position Function Description
RIGHT OTP mode ON PF5030 OTP can be emulated and
programmed when J3 populated
LEFT OTP mode OFF PF5030 OTP cannot be emulated
and programmed
Table 15. SW1 description
Position Function Description
RIGHT PWRON pin high PF5030 can power up
LEFT PWRON pin low PF5030 cannot power up
Table 16. SW2 description
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Switch number Voltage rail LED Description
1 VIN_5V D11
2 BUCK1 D10
3 BUCK2 D9
4 BUCK3 D8
5 LDO1 D7
6 LDO2 D6
Each LED is connected through an
independent switch. Disconnecting
them allows more accurate
efficiency measurement.
The switches also disconnect the
FRDM-KL25Z ADC inputs.
Table 17. SW3 description
Position Device output LED Description
1 PGOOD D5
2 INTB D4
3 FS0B D3
4 RSTB D2
Each LED is connected through an
independent switch. Disconnecting
them allows more accurate
efficiency measurement.
The switches also disconnect the
level shifters to the FRDM-KL25Z
inputs.
Table 18. SW4 description
Position Function Description
RIGHT VIN ON PF5030 supplied from USB
MIDDLE VIN OFF PF5030 not supplied
LEFT VIN ON PF5030 supplied from J1
Table 19. SW5 description
5 Installing and configuring software and tools
The programming/evaluation boards are always delivered with the GUI firmware already flashed. If MCU
firmware is already flashed, you can ignore this section. If it is specified that firmware must be updated or it is
malfunctioning, follow these instructions.
5.1 Flashing or updating the FRDM-KL25Z GUI firmware
If bootloader is already loaded in the FRDM-KL25Z board, steps 1-3 are not required. Start from step 4.
1. Disable the Storage Service and Windows Search: Run Services, double click, and stop them as shown in
Figure 12.
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Figure 12. Services configuration
2. Press the RST push button and connect the USB cable to the SDA port on the FRDM-KL25Z board.
•A new “bootloader” device appears on the left pane of the file explorer
3. Drag and drop the file “MSD-DEBUG-FRDM-KL25Z_Pemicro_v118.SDA” to the bootloader drive
Ensure that there is enough time for the firmware to be saved in the bootloader
4. Disconnect the USB cable, then reconnect it to the SDA port WITHOUT pressing the RST push button
•This time, FRDM_KL25Z device appears on the left pane of the file explorer as in Figure 13.
Figure 13. FRDM-KL25Z in left pane
5. Locate the file “nxp-gui-fw-frdmkl25z-usb_hid-device_<version>.bin” from the package. Drag and drop this
file into the FRDM_KL25Z device.
Ensure that there is enough time for the firmware to be saved.
6. Freedom board firmware is successfully loaded. Disconnect the USB-cable and reconnect it to the KL25Z
USB port.
5.2 Installing NXP GUI software package
To install the "NXP GUI for Automotive PMIC Families" or obtain the NXP GUI package, unzip an open "1 -
NXP_GUI_Setup" folder as shown in Figure 14.
Figure 14. NXP_GUI_Setup folder
UM11853 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved.
User manual Rev. 1.0 — 7 March 2023
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