ON Semiconductor ALPINE NCRHA926 User manual

©Semiconductor Components Industries, LLC, 2020
December, 2020 − Rev. 0 1Publication Order Number:
EVBUM2724/D
Evaluation Board
User's Manual
ALPINE (NCRHA926)
Introduction
The Alpine Evaluation Module (Alpine EVM) is an ARM®
926EJ−S Processor based SoC targeted towards space−based
applications. This EVM can be used for application development
based on ARM core.
The Alpine EVM has major peripherals to create a space−based
application, formidable for single−board testing environment.
Key Features
The Alpine is a high−performance and low−power platform that
enables users to evaluate and develop space communication
applications with Alpine SoC from ON Semiconductor. The Alpine
EVM has the following key features:
•Alpine SoC−LGA564
♦SDRAM
♦FLASH
♦GR1553B
♦SPI
♦SpaceWire
♦CAN 2.0 Controller
♦UART TO USB
♦External AHB through FMC Connector
⋅Mezzanine (Daughter card) or
⋅Main Board Connector Options
♦Mounting option of Yamaichi socket TCBGA564.
•Alpine SoC Test Ports
♦Alpine JTAG
♦ARM®926EJ−S Processor Debug
•On−Board Oscillators
♦100 MHz for System Clock
⋅50 MHz for SpaceWire clock (Derived form System Clock
Regulator)
⋅25 MHz for SPI External clock (Derived form System Clock
Regulator)
♦20 MHz for MIL1553 Clock
•Off−Board/External Clocking Support
♦System Clock
♦SpaceWire CLK
♦SPI External Clock
♦GR1553B Clock
•General User I/O’s
♦16 General Purpose IO’s can be configured with External
Connection Option through Header
♦8 LEDS Configuration
♦8 DIP Switches
•SPI Peripherals
♦SD Card
♦Temperature Sensor
♦ADC 8 Channels
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EVAL BOARD USER’S MANUAL

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•External Interface Headers
♦CAN 2.0 9−Pin D−SUB Male−2 Ports
♦GR1553B BNC −2 Ports
♦SpaceWire 9−pin D−SUB Male −2 Ports
♦USB TO UART Micro USB Type B
♦Micro SD connector
♦ADC SMA connectors – 8no’s
•Push Button and DIP Switches
♦Reset Push Button
♦User DIP Switches for GPIO Configuration
•Power
♦The Board is powered by either a Bench Power Supply or a DC
Power Adaptor
♦Green Power LED
♦Probe Points for Manual Power Measurements
♦Option to support a Fan for the Alpine ASIC from a 12 V Supply
♦3.3 V for All On Board Devices
♦1.8 V for FMC Connector Voltage Level Shifters
♦3.3 V for Alpine SoC IO Supply
♦1.2 V for Alpine SoC Core Supply
•PCB
♦Standard FR4 Di−electric Material 170Tg

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Functional Block Diagram
Figure 1 shows the functional block diagram of the Alpine EVM.
Figure 1. Alpine Functional Block Diagram

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Memory Map
Table 1. MEMORY MAP
Module
Map #0 Start Address
Map #0 End Address
Map #1 Start Address
Map #1 End Address
External MRAM
0x0000_0000
0x007F_FFFF
0x5000_0000
0x507F_FFFF
External SDRAM
0x4000_0000
0x7FFF_FFFF
0x0000_0000
0x3FFF_FFFF
0x8000_0000 1
0x8000_00FF 1
0x4000_0000 1
0x4000_00FF 1
0x8000_0100 2
0x8000_03FF 2
0x4000_0100 2
0x4000_03FF 2
Internal SRAM #1
0x9000_0000
0x9000_7FFF
0x9000_0000
0x9000_7FFF
Internal SRAM #2
0x9000_8000
0x9000_BFFF
0x9000_8000
0x9000_BFFF
Internal SRAM #3
0x9000_C000
0x9000_FFFF
0x9000_C000
0x9000_FFFF
Interrupt Controller #1
0xA000_0000
0xA000_0FFF
0xA000_0000
0xA000_0FFF
Interrupt Controller #2
0xA100_0000
0xA100_0FFF
0xA100_0000
0xA100_0FFF
GPIOs
0xA200_0000
0xA200_0FFF
0xA200_0000
0xA200_0FFF
DMA Controller
0xA300_0000
0xA300_0FFF
0xA300_0000
0xA300_0FFF
System Controller
0xA400_0000
0xA400_0FFF
0xA400_0000
0xA400_0FFF
Watchdog
0xA410_0000
0xA410_0FFF
0xA410_0000
0xA410_0FFF
Timer #1
0xA420_0000
0xA420_0FFF
0xA420_0000
0xA420_0FFF
Timer #2
0xA430_0000
0xA430_0FFF
0xA430_0000
0xA430_0FFF
Timer #3
0xA440_0000
0xA440_0FFF
0xA440_0000
0xA440_0FFF
UART
0xA450_0000
0xA450_0FFF
0xA450_0000
0xA450_0FFF
SPI
0xA460_0000
0xA460_00FF
0xA460_0000
0xA460_00FF
CAN
0xA470_0000
0xA470_00FF
0xA470_0000
0xA470_00FF
SpaceWire
0xA480_0000
0xA480_00FF
0xA480_0000
0xA480_00FF
GR1553B
0xA490_0000
0xA490_00FF
0xA490_0000
0xA490_00FF
External AHB Controller
0xB000_0000
0xCFFF_FFFF
0xB000_0000
0xCFFF_FFFF
1. SDRAM Controller configuration registers.
2. SDRAM Controller reserved address space. Should not be accessed by software.

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Board Layout
The Alpine EVM has dimensions of 236.35 mm ×194.69 mm and is a 12−layer board fabricated with FR4 grade material.
Figure 2 shows the top view of the Alpine board.
Figure 3 shows the bottom view of the Alpine board.
Figure 2. Alpine Board (Top View)

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Figure 3. Alpine Board (Bottom View)

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Hardware Setup
Below are the instructions to set up the Alpine EVM.
1. Before power up the board insert jumpers J41, J43, J49 and J58.
2. Connect 20 Pin SEGGER®J−LINK PUS Adapter JTAG to J65 (ARM®926EJ−S Processor JTAG) on the Alpine
EVM as per below Figure 4.
Figure 4. ARM)926EJ−S Processor JTAG Connection
3. Connect USB 2.0 USB Mini−B cable to Alpine micro USB−B (J48) as per below Figure 5 and connect other side to
host for serial port connection. Open Tera−Term or any serial port application and configure settings.
♦Baud rate to 115200
♦Data bit as 8
♦Parity as None
♦Stop bit as 1bit
♦Flow control as None
4. Apply power by connecting the DC Barrel Jack from the provided 12 VDC Power Adapter to connector (J16) and
turning the power switch (SW2) to the “ON” position.

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Figure 5. Alpine Serial Port Connection
Software Setup
Installation Guidelines
a. Download the latest version of JFlash.exe from the below link and install it.
https://www.segger.com/downloads/jlink/#J−LinkSoftwareAndDocumentationPack
b. Open README.txt from JFLASH folder(attached) and follow the instruction.
c. Extract the u−boot.bin and alpine.bin from the images directory of the Alpine SDK alpine_sdk_v1p0.tar.gz
d. Open the J−Flash V6.40 application
e. Open the SEGGER®J−Flash Configuration File:
•File →Open Project
Figure 6.

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•Navigate to <Installation>\JLink_V640\Samples\JFlash\ProjectFiles\ONSemi folder and select AlpineV1.jflash file.
A copy of the AlpineV1.jflash file can be located in the Alpine SDK jflash directory.
Figure 7.
f. Open u−boot.bin
•File →Open data file ( Ctrl+O ) and open u−boot.bin file.
Figure 8.
•Enter 0x0 as the start address, i.e. offset 0x0 of Flash device
Figure 9.

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g. Program the target:
•Target →Production Programming (F7)
Figure 10.
•Wait for flashing to complete
Figure 11.
h. After successful programming of u−boot.bin close and reopen J−Flash and repeat steps ‘e’, ‘f’ and ‘g’ with start
address in step ‘f’ as 0x40000 for programming RTEMS_APP.bin (RTEMS).
Figure 12.

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i. After successful programming of u−boot.bin and alpine.bin, power cycle the board.
j. Below is the LED pattern,
•Uboot starts booting: All LED’s will be in OFF state.
•Uboot up and running: LED1 and LED2 will toggle upon UART receive and transmit activity.
•RTEMS up and running: LED1,LED2, LED5 and LED6 will be in ON state.
LED3, LED4, LED7 and LED8 will be in OFF state.
k. Monitor the debug terminal connected to the micro USB port (J48) for command prompt.
Power Supply
Use the recommended power supply or an equivalent (12VDC/9A) power supply to connect to DC Barrel jack (J16) on the
Alpine EVM. Or with equivalent power from bench supply through Jack connector to J36 positive lead and Ground to J42,
refer Figure 13. The recommended DC Barrel Plug dimensions are 2.1 mm I.D. x 5.0 mm O.D. x 11.0 mm.
To apply power to Alpine board, insert the DC plug of the power supply into the Alpine. Then, connect the AC plug of the
power supply to the AC power source. Hot plugging the Alpine (connecting the AC plug before the DC plug) may damage
the board.
To remove power from the Alpine, disconnect the AC plug of the power supply from the AC power source. Then, disconnect
the DC plug of the power supply from the Alpine board.
Figure 13. Power Supply Connections

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INTERFACE DETAILS
Clock Distribution
Figure 14 shows the clock distribution circuit. One 100−MHz and 20 MHz oscillator used on board. 100−MHz oscillator
is for Alpine system clock, the 20 MHz oscillator is for mil1553 clock input and for remaining interfaces clock is divided from
100−MHz oscillator using clock dividers.
Table 2. CLOCK DISTRIBUTION
Signal
Description
Frequency
CLK_IN
System Clock
100 MHz
SPW_CLK
SpaceWire Clock
50 MHz
SPI_EXT_CLK
SPI External Clock
25 MHz
CLK_1553
GR1553B Clock
20 MHz
Figure 14. Alpine Clock Distribution

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Reset Circuit Distribution
The Alpine EVM features power on reset and push button reset (MR) for resetting the Alpine SoC device.
TPS3802K33DCKR supervisory circuit monitors 3.3 V, when the voltage drops below 2.93 V it provides reset signal to the
system.
Alpine reset is also connected to Alpine JTAG and ARM®926EJ−S Processor Debug header as show below Figure 15.
Figure 15. Reset Distribution

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Memory Interface
SDR−SDRAM Interface
The Alpine EVM features dual configurations of SDRAM, which are factory configurable as shown in Figure 16. Below
are the details of the configurations,
•640 Mb (16Mx32 Data & 16Mx8 ECC bits) of SDRAM using two SDRAMs according to the below configurations
♦16Mx32 SDRAM for 32−bit data lines
♦16Mx16 SDRAM for 8−bit ECC bits and remaining 8 bits are unused
•2.5 Gb (2 Gb for Data & 0.5 Gb for ECC bits) – Optional Device
♦16Mx40 SDRAM for 32−bit data lines & 8−bit ECC
Figure 16. SDRAM Connection Diagram

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FLASH Interface
The Alpine EVM features dual configurations of Boot Memory through MRAM controller which are factory configurable.
Below are the details of the configurations,
•64 Mb NOR Flash
♦8/16 Bit configurable
•64 Mb MRAM – Optional Device
Figure 17. Boot Memory Interface
ALPINE
SoC
MRAM Controller
EXTMADDR[22:1]
EXTMDATA[14:0]
EXTM_SIZ E
NOR FLASH (4Mx16)
S29GL064S70DHI040
DQ14-DQ0
A21 A0
SELECTION
JUMPER
3.3 V
BYTE#
MRAM (8Mx8)
UT8MR8M8
OPTIONAL
Bus Width selection
switch(8bit/16bit)
EXTMW En
EXTMO En
EXTMC En CE#
OE#
WE#
EXTMADDR [0]
EXTMDATA[15] DQ15/A-1
A22 A1
E_All#
W#
G#
D7-0
A0

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GR1553B Interface
Alpine EVM features dual redundant GR1553B bus. Key features of this interface are
•Bus Controller (BC), Remote Terminal (RT) and Bus Monitor (BM) modes of operation.
•All transfer types supported, including RT−to−RT and broadcast transfers.
•Bus A and B interface to 75Ohm BNC connectors.
3.3 V Monolithic Dual Transceivers (HI−1573PSM) along with Isolation Transformer has been used to interface the
GR1553B Bus to the connector.
Figure 18. GR1553B Interface
ALPINE
ASIC
GR1553B
CLK_1553
TXINA_1553
RXA_1553
RXAn_1553
TXA_1553
TXAn_1553
RXENA_1553
TXINB_1553
RXB_1553
RXBn_1553
TXB_1553
TXBn_1553
RXENB_1553
HI-1573PSM
3.3V Monolithic
Dual Transceivers
BUSA
BUSAn
RXENA
BUSB
BUSBn
RXENB
RXBn
RXB
TXINHB
TXB
TXBn
RXAn
RXA
TXINHA
TXA
TXAn
20MHz
CLK
MIL-STD-1553
Isolation
Transformers
(PM-DB2745S)
BNC CONNECTOR
031-70221
BNC CONNECTOR
031-70221
CAN Controller Interface
The Alpine EVM features a CAN interface, 3.3 V CAN Transceiver is interfaced with Alpine SoC. CAN data lines are
terminated to 9 pin D−SUB connector.
Figure 19. CAN Interface
ALPINE
ASIC
CAN INTERFACE
CAN_TXD
CAN_RXD
CAN_STBY
CAN
TRANSCEIVER
SN65HVD230DQ
D
R
RS
CANH
Vref
CANL
9 PIN D-SUB
Connector
5747840-6
CANH
CANL
Termination
Jumper
Below are the pin out details of the D−Sub connector,
Table 3. CAN CONNECTOR
Pin
Signal
1
No Connect
2
CAN_L
3
GND
4
No Connect
5
CAN_SHLD
6
GND
7
CAN_H
8
No Connect
9
No Connect

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SpaceWire Interface
The Alpine EVM features two ports of SpaceWire interface. SpaceWire data lines are converted to LVDS using Quad LVDS
driver & Quad LVDS receiver and terminated two independent 9 pin d−sub connector. All differential lines are trace length
matched and PCB tracks have a 100 Wdifferential impedance.
Figure 20. SpaceWire Interface
ALPINE ASIC
SPACE WIRE
INTERFACE
SPW_CLK
SPW_RXS[1]
SPW_RXS[0]
SPW_RXD[1]
SPW_RXD[0]
SPW_TXS[1]
SPW_TXS[0]
SPW_TXD[1]
SPW_TXD[0]
ISOLATION
RESISTOR
ADN4667
50MHz
CLK
ISOLATION
RESISTOR
DIN1
DIN2
DIN3
DIN4
DOUT1+
DOUT1-
DOUT2+
DOUT2-
DOUT3+
DOUT3-
DOUT4+
DOUT4-
ADN4668
RIN1
RIN2
RIN3
RIN4
ROUT1+
ROUT1-
ROUT2+
ROUT2-
ROUT3+
ROUT3-
ROUT4+
ROUT4-
9 PIN D-SUB
Connector
100E
Termination
resistor
9 PIN D-SUB
Connector
Below are the pin out details of the D−Sub connector,
Table 4. CAN CONNECTOR
Pin
DSUB−0 Signal
Pin
DSUB−1 Signal
1
SPW_RXD_P0
1
SPW_RXD_P1
2
SPW_RXS_P0
2
SPW_RXS_P1
3
SPW_SHIELD0
3
SPW_SHIELD1
4
SPW_TXS_N0
4
SPW_TXS_N1
5
SPW_TXD_N0
5
SPW_TXD_N1
6
SPW_RXD_N0
6
SPW_RXD_N1
7
SPW_RXS_N0
7
SPW_RXS_N1
8
SPW_TXS_P0
8
SPW_TXS_P1
9
SPW_TXD_P0
9
SPW_TXD_P1
UART to USB Interface
The Alpine EVM features UART TO USB with micro USB connectivity. FT232RL used to convert UART signals to USB
and vice versa.
Figure 21. UART to USB Interface
Alpine
ASIC UART
USB to
UART
transceiver
FT232RL
Micro B USB
connector
629105136821
UART_RXD
UART_TXD

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External AHB Interface
The Alpine EVM features AHB interface through external FMC connector. FMC Connector I/O Voltage can be either set
to 1.8 V or 3.3 V depending on the jumper setting. SN74AVC16T245DGGR shall be used for voltage level shifting between
3.3 V to 1.8 V.
Figure 22. External AHB Interface
Alpine ASIC
FMC BANK
3.3V to 1.8V/3.3V level
shifter
SN74AVC16T245DGGR
FMC CONNECTOR
ASP-134486-01
GPIO[15-0]
HRDATAM[31-0]
HADDRM[31-0]
HBURSTM[2-0]
HPROTM[3-0]
HSIZEM[1-0]
HTRANSM[1-0]
HWDATAM[1-0]
HWRITEM
HLOCKM
HRESETn
HRESPM[0]
HREADYM
HCLKM

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GPIO Interface
The Alpine EVM features 16 GPIO’s. The GPIO lines are jumper configurable to take multiple configurations.
•GPIO [15:8] lines can be configured as either to take input from slide switch or connected to FMC connector through a
level translator.
•GPIO [7:0] lines can be configured as either to drive LED’s or connected to FMC connector through a level translator.
Figure 23. GPIO Interface
SN74AVC16T245DGGR
SN74AVC16T245DGGR SN74AVC16T245DGGR

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SPI Interface
The Alpine EVM has one SPI port with 4 Slave selection lines refer Figure 24. SPI lines are terminated to four headers (SPI00
to SPI03) for external interface. SPI lines are also connected to below configuration through jumper selection. Temperature
Sensor is located on the bottom side of the PCB underneath the Alpine to monitor device temperature.
•SPI0 − SPI Header
•SPI1 – SPI Header & Serial ADC (AD5592R) with 8 SMA Connectors for analog input
•SPI2 – SPI Header & Temperature Sensor (TMP125)
•SPI3 – SPI Header & SD card
Figure 24. SPI Connection Diagram
Alpine ASIC
SPI Interface
Temperature
Sensor
ADC
SD CARD
SMA
CONNECTORS
0-7
SPI External
jumper_3
SPI_SSN_0
SPI_SSN_1
SPI_SSN_2
SPI_SSN_3
SPI_MISO
SPI_MOSI
SPI_CLK
SPI_EXT_CLK
SPI External
jumper_2
SPI External
jumper_1
SPI External
jumper_0
8
ISOLATION
JUMPERS
25MHz
CLK