ON Semiconductor NCV91300 User manual

©Semiconductor Components Industries, LLC, 2021
March, 2021 −Rev. 0
1Publication Order Number:
EVBUM2789/D
NCV91300 Evaluation Kit
User Manual
EVBUM2789
DOCUMENT DESCRIPTION
Goal of Document
This document describes the operation and use of the NCV91300
evaluation kit. This kit is provided by ON Semiconductor to help user
to evaluate and set up the NCV91300 numerous operation modes as
well as the typical operating characteristics.
In this document, user will find information about hardware and
Graphical User Interface software, as well as typical Bill of Material,
board schematic and layout.
Applicable and Reference Documents
APPLICATION INFORMATION
Figure 1. Typical Application Schematic
1.0 mH
Processor
Core
NCV91300
Power Good
DCDC
Modular
Driver
Power Supply Input
DCDC
Controller Sense
Enable Control
Input
10 mF
AGND
SDA
PG
EN
SW
PVIN
PGND
FB
BOOT
10 nF
Enabling
Test / I2C
Clocking
Output
Monitoring
Interrupt
Thermal
Protection
AGND
AVIN
Supply Input
Core
External Clock SYNC
Interrupt INTB
AGND
SCL
I2C BUS
2.15 MHz
3.0 A
10 mF
4.7 mF
NCV91300 Data Sheet
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EVAL BOARD USER’S MANUAL

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INTRODUCTION
The NCV91300 is a synchronous PWM buck converter
optimized to supply the different sub systems of automotive
applications post regulation system up to 5 V input. The
device is able to deliver up to 3.0 A, with programmable
output voltage from 0.6 V to 3.3 V. Operation at up to
2.15 MHz switching frequency allows the use of small
components. Synchronous rectification and automatic PFM
to PWM transitions improve overall solution efficiency. The
NCV91300 is housed in low profile 3.0 x 3.0 mm QFN−16
package.
Content
The evaluation kit comes with 2 boards, associated cables
and a self−extractable software.
Requirements
In order to operate properly, user should connect and
configure the following components:
•Personal Computer (PC) with at least one USB port to
communicate with the Interface Board. Microsoft “.NET
Framework 3.5” at least has to be installed. The Graphical
User Interface software is installed on this PC and, with
this software; user will have full control of the NCV91300
on the evaluation board.
•Evaluation board PCB
•USB interface board. This board is a USB to I2C interface.
It receives from PC Graphical User Interface software all
requests and converts it into NCV91300 understandable
I2C command that sets NCV91300 internal registers. If
there is an error or if NCV91300 does not acknowledge
the request as described in the I2C specification, the
interface board will detect it and will inform the PC
Graphical User Interface software. NCV91300 registers
are also read through this interface. In that case, the board
translates I2C format received from NCV91300 to USB
readable standard. PC Graphical User Interface software
will then display the result and NCV91300 configuration
to the user.
Eval Kit Installation
To properly operate the eval kit, NCV91300 GUI should
be installed:
NCV91300 GUI software installation (Refer to Section
GUI Software Installation)
GUI Software Installation
Click on the self−extractable Setup_NCV91300.exe
The installation procedure will install all needed drivers
and software. You may have to re−boot your computer after
installation completion.

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GETTING STARTED
Input / Output Description
This section describes the connectors and jumper settings for proper operation as well as the voltage appropriate range.
Table 1. EVALUATION BOARD OPERATING RANGE
Symbol Parameter Min Typ Max Unit
PVIN Power Supply Range 1.9 3.3 5.5 V
AVIN Analog Supply Range 3.0 3.3 5.5 V
Table 2. CONFIGURATION CONNECTORS DESCRIPTION
Input / Output Description Default Setting
CN1 / CN2 Interface board connector N/A
J1/J8 Banana Analog Supply Input (positive/negative) N/A
J3/J8
J5
Banana Power Supply Input (positive/negative)
SL5 connector Power supply input
N/A
J2 EN Level Settings
•1−2 EN = VBAT
•2−3 EN = Driven by USB Interface Board
2−3
J9 SYNC Level Settings
•1−2 SYNC = connected to J6 SMA
•2−3 SYNC = Driven by USB Interface Board
2−3
J4 PG pull up Closed
J7 INTB pull up Closed
J13/J11
J12
Banana Output voltage (positive/negative)
SL5 connector Output Voltage
N/A
J10 Inductor current sense measurement for differential probe (measured across R6 resistor) N/A
J11 Load transient sense measurement for differential probe (measured across R10 resistor) N/A
J15 CBOOT measurement for differential probe (measured across C13)
J6 SMA for SYNC clock injection N/A
JMP1 / JMP2 GND connector N/A
S3 Input ferrite bead bypass Closed
S1 SCL connection to interface board Closed
S2 SDA connection to interface board Closed
S4 Output ferrite bead bypass Closed
S5 DCDC sense selection (local or remote) Local

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The evaluation board duplicates most important signals on test points to the user.
Table 3. TEST POINT
Test Points Description
TP1 EN: Hardware Enable
•EN = LOW: NCV91300 is disabled
•EN = HIGH: NCV91300 is enabled
TP2 SYNC signal
TP3 PG: Power Good Signal
•PG = LOW: Output voltage out of range
•PG = HIGH: Output voltage in range
TP4 SDA: I2C Data signal
TP5 SCL: I2C Clock signal
TP6 SW: DC to DC converter switching node
TP7 INTB: Interrupt Signal
•INTB = LOW: Interrupt detected
•INTB = HIGH: No interrupt
TP8 PGND sense
TP9 PVIN Sense
TP10/TP11 Feedback loop for bode measurements (across R7)
TP12/TP13 VOUT: Output voltage sense (across C17)
TP14 Gate of the Q1 transistor used for Load Transient
TP15 AVIN Sense
TP16 Iout force
Setup
The following steps should be followed before the
Evaluation Board is operated
1. Install the Graphical User Interface (GUI)
Software on computer
2. Connect the Interface Board to the Board, using
the ribbon cable or board to board connectors
3. Connect Output Voltage and Loads (if any) to the
board
4. Configure all jumpers to Default Settings
5. Connect the interface board to computer with USB
cable
6. Connect NCV91300 Board 2.5 V~5.5 V (See
table 1) power supply to J3/J8 (J5) and J1/J8
connectors, pay attention to polarity of power
supply and the V clamp of the power supply.
7. Turn power supply on
8. Run the NCV91300 Graphical User Interface
Software

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Figure 2. Hardware Setup of EVKit (Board To Board Connection)
Figure 3. Hardware Setup of EVKit (Ribbon Cable Connection)

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BOARD LAYOUT
This section includes the SST layer of PCB layout and EVB board pictures.
Figure 4. TOP Assembly
Figure 5. BOTTOM Assembly
2
3
1
3 POINTS CONFIGURATION
JUMPERS PIN OUT

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Figure 6. TOP
Figure 7. Inner 1

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Figure 8. Inner 2
Figure 9. Bottom

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Figure 10. Board Picture TOP View
J5 Input
Connector J12 Output
Connector

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BOARD SCHEMATIC AND BOM
This section provides the board schematic as well as standard Bill of Material.
Schematic
Figure 11. Board Schematic

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Bill of Material
NCV91300 QFN16 REVC
Revision: 2.1
25−Feb−20
Item Quantity Reference Value Tolerance Voltage Techno Part Number Part Number (Alternate) PCB Footprint
11 2x10 15210206601000 15210202601000 HEADER50−100−2x10_F 21 CON26A HTST−113−01−T−DV−P−TR HE10−26−SMALL−CI_REV2
33 47 mF6.3 V X7S CGA6P1X7S0J476M250AC GCM32ER70J476ME19 SMD_1210 42 100 nF 50 V X7R CGA3E2X7R1H104K080A GCJ188R71C104KA01 SMD_0603 58 DNP SMD_0603 61 10 nF 6.3 V X7R CGA3E2X7R2A103K080AA GCM188R72A103KA37D SMD_0603 75 10 mF6.3 V X7R CGA4J1X7R0J106K125AC GCM21BR70J106KE22L SMD_0805 81 10 mF6.3 V X7R CGA5L1X7R1E106K160AC GCM31CR71C106KA64 SMD_1206 93 DNP SMD_1210
10 4 FIXHOLE3.2 FIX3v2H 11 2 STRAP GND JUMPER400H 12 3 CONN_DEKTRON_571_RED DEKTRON_571−0500 BANANA_JACK_REV2
13 2 STRAP 3pins STRAP3P 14 6 STRAP 2pins HEADER_2_100H 15 2 SL5.08_2PT CON2P−5v08_COUDE 16 1 Clock Generator 131−3701−261 CONN_SMB_V 17 2 CONN_DEKTRON_571_BLACK DEKTRON_571−0100 BANANA_JACK_REV2
18 1 DNP SMD_4040_2520 19 1 1.0 mHSPM4020−1R0M−D FDSD0420D−1R0M MURATA_4040
20 1 DNP SMD_0603_0805 21 1 1.0 mHTFM252012ALMA1R0MTAA DFE2HCAH1R0MJ0 MURATA_2520 22 1 NTD3055L104 DPACK_1234 23 2 10K 0.05 SMD_0603 24 2 0R 0.05 SMD_0603 25 2 51 0.05 SMD_0603 26 2 DNP 0.05 SMD_0603 27 1 0.01R 5% KRL2012E−M−R010−F−T1 SMD_1220
28 1 0.1 5% SMD_1220 29 5 STRAP PCB STRAP_PCB 30 1 Strap_PCB_3 STRAP_PCB3 31 16 TEST_POINT TP_T2_16 32 1 NCV91300 QFN16_3x3_05
Table 4. BILL OF MATERIAL
CN1 CN2 C1,C4,C5 C2,C6 C3, C7, C8, C9, C10 ,C19 ,C20, 23 C11 C12, C14, C15, C16, C17 C13 C18, C21, C22 H1, H2, H3, H4 JMP1, JMP2 J1, J3, J11 J2, J9 J4, J7, J10, J14, J15, J16 J5, J12 J6 J8, J13 L1 L2 L3 L4 Q1 R1, R2 R3, R7 R4, R10
R5, R8 R6 R9
S1, S2, S3, S4, S5
S6
TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8, TP9, TP10, TP11, TP12, TP13, TP14, TP15, TP16
U1

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GUI SOFTWARE
Once hardware is properly installed and set up, user may
use the Graphical User Interface software (GUI in the rest of
the document) to set up NCV91300 and read configurations
At start up, the GUI will first read NCV91300
configuration. Please make sure that hardware is supplied
prior to GUI startup. Otherwise, the following error will be
displayed
Figure 12.
If during software power up, all the controls are empty,
please verified I2C address and ribbon cable insertion or
board to board connection.
Then, the main GUI screen is displayed
Figure 13. GUI Main Screen

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You can click on the Generic tab to access to the generic window, where individual register can be addressed
Figure 14. Generic Window
You can click on the Register tab to access to the Register window, where all register can be read and write
Figure 15. Register Window

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NCV91300 CONFIGURATION
Table 5. NCV91300 CONFIGURATION
Configuration
3.5 A
NCV91300A
2.5 A
NCV91300B
Default I2C address
PID product identification
RID revision identification
FID feature identification
ADD1 – 14h : 0010100R/W
93h
Metal
00h
ADD1 – 14h : 0010100R/W
93h
Metal
01h
Default VOUT 1.25 V 1.1 V
Default MODE Forced PWM Forced PWM
Default IPEAK 4.5 A 3.5 A
OPN NCV91300MNWATXG NCV91300MNWBTXG
Marking WA W3
Output filter 4 x 10 mF4 x 10 mF
Table 6. I2C REGISTERS MAP CONFIGURATION (NCV91300MNWATXG)
Add.
Register
Name Type Def. Function
00h INT_ACK1 W1C 00h Interrupt register 1
01h INT_ACK2 W1C 00h Interrupt register 2
02h INT_SEN1 R 00h Sense register 1 (real time status)
03h INT_SEN2 R 00h Sense register 2 (real time status)
04h INT_MSK1 RW FFh Mask register 1 to enable or disable interrupt sources (trim)
05h INT_MSK2 RW FFh Mask register 2 to enable or disable interrupt sources (trim)
06h PID R 93h Product Identification
07h RID R Metal Revision Identification
08h FID R 00h Features Identification (trim)
09h PROG RW 69h Output voltage settings (trim)
0Ah COMMAND RW D7h Operating mode, Power good and active discharge settings register (trim)
0Bh TIME RW 27h Enabling and DVS timings register (trim)
0Ch LIMCONF RW D2h Reset and limit configuration register (trim)
0Dh to FFh − − − Reserved. Test Registers

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Table 7. I2C REGISTERS MAP CONFIGURATION (NCV91300MNWBTXG)
Add.
Register
Name Type Def. Function
00h INT_ACK1 W1C 00h Interrupt register 1
01h INT_ACK2 W1C 00h Interrupt register 2
02h INT_SEN1 R 00h Sense register 1 (real time status)
03h INT_SEN2 R 00h Sense register 2 (real time status)
04h INT_MSK1 RW FFh Mask register 1 to enable or disable interrupt sources (trim)
05h INT_MSK2 RW FFh Mask register 2 to enable or disable interrupt sources (trim)
06h PID R 93h Product Identification
07h RID R Metal Revision Identification
08h FID R 01h Features Identification (trim)
09h PROG RW 5Ah Output voltage settings (trim)
0Ah COMMAND RW D7h Operating mode, Power good and active discharge settings register (trim)
0Bh TIME RW 2F Enabling and DVS timings register (trim)
0Ch LIMCONF RW 52h Reset and limit configuration register (trim)
0Dh to FFh − − −Reserved. Test Registers

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REGISTERS DESCRIPTION
The tables below describe the I2C registers.
Registers / Bits Operations:
R Read only register
W1C Write to 1 to Clear
RW Read and Write register
Reserved Address is reserved and register / bit is not
physically designed
Spare Address is reserved and register / bit is
physically designed
In bold default can be factory programmed upon request.
Table 8. INTERRUPT ACKNOWLEDGE REGISTER 1
Name: INTACK1 Address: 00h
Type: W1C Default: 00000000b (00h)
Trigger: Dual Edge [D7..D0]
D7 D6 D5 D4 D3 D2 D1 D0
Spare = 0 ACK_UVLO ACK_UVP ACK_OVP Spare = 0 ACK_ISHORT ACK_IDCDCHS ACK_IDCDCLS
Bit Bit Description
ACK_IDCDCLS DC−DC Negative Over Current Sense Acknowledgement
0: Cleared
1: DC−DC Negative Over Current Event detected
ACK_IDCDCHS DC−DC Over Current Sense Acknowledgement
0: Cleared
1: DC−DC Over Current Event detected
ACK_ISHORT DC−DC Short−Circuit Protection Sense Acknowledgement
0: Cleared
1: DC−DC Short circuit protection detected
ACK_OVP PVIN Overvoltage Protection Sense Acknowledgement
0: Cleared
1: OVP Event detected
ACK_UVP PVIN Undervoltage Protection Sense Acknowledgement
0: Cleared
1: UVP Event detected
ACK_UVLO Under Voltage Sense Acknowledgement
0: Cleared
1: Under Voltage Event detected

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Table 9. INTERRUPT ACKNOWLEDGE REGISTER 2
Name: INTACK2 Address: 01h
Type: W1C Default: 00000000b (00h)
Trigger: Dual Edge [D7..D0]
D7 D6 D5 D4 D3 D2 D1 D0
Spare = 0 ACK_TSD ACK_TWARN ACK_TPREW Spare = 0 ACK_BUS ACK_CLK ACK_PG
Bit Bit Description
ACK_PG Power Good Sense Acknowledgement
0: Cleared
1: DC−DC Power Good Event detected
ACK_CLK Working Clock Indicator Acknowledgement
0: Cleared
1: DC−DC switching frequency source changed
ACK_BUS Double write Error Acknowledgement
0: Cleared
1: Invalid double write access
ACK_TPREW Thermal Pre Warning Sense Acknowledgement
0: Cleared
1: Thermal Pre Warning Event detected
ACK_TWARN Thermal Warning Sense Acknowledgement
0: Cleared
1: Thermal Warning Event detected
ACK_TSD Thermal Shutdown Sense Acknowledgement
0: Cleared
1: Thermal Shutdown Event detected
Table 10. INTERRUPT SENSE REGISTER 1
Name: INTSEN1 Address: 02h
Type: R Default: 00000000b (00h)
Trigger: N/A
D7 D6 D5 D4 D3 D2 D1 D0
Spare = 0 SEN_UVLO SEN_UVP SEN_OVP Spare = 0 Spare= 0 SEN_IDCDCHS SEN_IDCDCLS
Bit Bit Description
SEN_IDCDCLS DC−DC negative over current sense
0: DC−DC negative current is below limit
1: DC−DC negative current is over limit
SEN_IDCDCHS DC−DC over current sense
0: DC−DC output current is below limit
1: DC−DC output current is over limit
SEN_OVP PVIN Overvoltage Protection Sense
0: OVP not detected
1: OVP detected
SEN_UVP PVIN Undervoltage Protection Sense
0: UVP not detected
1: UVP detected
SEN_UVLO Under Voltage Sense
0: Input Voltage higher than UVLO threshold
1: Input Voltage lower than UVLO threshold

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Table 11. INTERRUPT SENSE REGISTER 2
Name: INTSEN2 Address: 03h
Type: R Default: 00000000b (00h)
Trigger: N/A
D7 D6 D5 D4 D3 D2 D1 D0
Spare = 0 SEN_TSD SEN_TWARN SEN_TPREW Spare = 0 SEN_BUS SEN_CLK SEN_PG
Bit Bit Description
SEN_PG Power Good Sense
0: DC−DC Output Voltage below target
1: DC−DC Output Voltage within nominal range
SNS_CLK Working Clock Indicator Sense
0: DC−DC switching frequency follows the Internal Oscillator
1: DC−DC switching frequency follows the SYNC pin
SEN_BUS Double write Error Sense
0: No error
1: Invalid double write access
SEN_TPREW Thermal Pre Warning Sense
0: Junction temperature below thermal pre−warning limit
1: Junction temperature over thermal pre−warning limit
SEN_TWARN Thermal Warning Sense
0: Junction temperature below thermal warning limit
1: Junction temperature over thermal warning limit
SEN_TSD Thermal Shutdown Sense
0: Junction temperature below thermal shutdown limit
1: Junction temperature over thermal shutdown limit
Table 12. INTERRUPT MASK REGISTER 1
Name: INTMSK1 Address: 04h
Type: RW Default: See Register map
Trigger: N/A
D7 D6 D5 D4 D3 D2 D1 D0
Spare = 1 MSK_UVLO MSK_UVP MSK_OVP Spare = 1 MSK_ISHORT MSK_IDCDCHS MSK_IDCDCLS
Bit Bit Description
MSK_IDCDCLS DC−DC negative over current interrupt mask
0: Interrupt is Enabled
1: Interrupt is Masked
MSK_IDCDCHS DC−DC over current interrupt mask
0: Interrupt is Enabled
1: Interrupt is Masked
MSK_ISHORT DC−DC Short−Circuit Protection mask
0: Interrupt is Enabled
1: Interrupt is Masked
MSK_OVP PVIN Over Voltage interrupt Mask
0: Interrupt is Enabled
1: Interrupt is Masked
MSK_UVP PVIN Under Voltage interrupt Mask
0: Interrupt is Enabled
1: Interrupt is Masked
MSK_UVLO Under Voltage interrupt mask
0: Interrupt is Enabled
1: Interrupt is Masked

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Table 13. INTERRUPT MASK REGISTER 2
Name: INTMSK2 Address: 05h
Type: RW Default: See Register map
Trigger: N/A
D7 D6 D5 D4 D3 D2 D1 D0
Spare = 1 MSK_TSD MSK_TWARN MSK_TPREW Spare = 1 MSK_BUS MSK_CLK MSK_PG
Bit Bit Description
MSK_PG Power Good interrupt source mask
0: Interrupt is Enabled
1: Interrupt is Masked
MSK_CLK Working Clock Indicator interrupt Mask
0: Interrupt is Enabled
1: Interrupt is Masked
MSK_BUS Double write Error interrupt source mask
0: Interrupt is Enabled
1: Interrupt is Masked
MSK_TPREW Thermal Pre Warning interrupt mask
0: Interrupt is Enabled
1: Interrupt is Masked
MSK_TWARN Thermal Warning interrupt mask
0: Interrupt is Enabled
1: Interrupt is Masked
MSK_TSD Thermal Shutdown interrupt mask
0: Interrupt is Enabled
1: Interrupt is Masked
Table 14. PRODUCT ID REGISTER
Name: PID Address: 06h
Type: R Default: 00011011b (93h)
Trigger: N/A Reset on N/A
D7 D6 D5 D4 D3 D2 D1 D0
PID_7 PID_6 PID_5 PID_4 PID_3 PID_2 PID_1 PID_0
Table 15. REVISION ID REGISTER
Name: RID Address: 07h
Type: R Default: Metal
Trigger: N/A
D7 D6 D5 D4 D3 D2 D1 D0
RID_7 RID_6 RID_5 RID_4 RID_3 RID_2 RID_1 RID_0
Bit Bit Description
RID[7..0] Revision Identification
10000000: V3P1
00100000: V1TC
10000100: Pass 2.0

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Table 16. FEATURE ID REGISTER
Name: FID Address: 08h
Type: R Default: See Register map
Trigger: N/A
D7 D6 D5 D4 D3 D2 D1 D0
Spare Spare Spare Spare FID_3 FID_2 FID_1 FID_0
Bit Bit Description
FID[3..0] Feature Identification
Table 17. DC−DC VOLTAGE PROG REGISTER
Name: PROG Address: 09h
Type: RW Default: See Register map
Trigger: N/A
D7 D6 D5 D4 D3 D2 D1 D0
Vout [7..0]
Bit Bit Description
Vout [7..0] Sets the DC−DC converter output voltage
00000000b = 600 mV (5mV step)
00000001b = 605 mV (5 mV step)
…
01001111b = 950 mV (5 mV step)
01010000b = 1000 mV (10 mV step)
01010001b = 1010 mV (10 mV step)
…
10110011b = 1990 mV (10 mV step)
10110100b = 2000 mV (20 mV step)
10110101b = 2020 mV (20 mV step)
…
11110100b = 3280 mV (20 mV step)
11110101b = 3300 mV (20 mV step)
…
11111111b = 3300 mV