Parallella P1600 User manual

Parallella-1.x

Reference Manual

REV 14.09.09 1

Revision History

Version Comments

0.13.2.13 Initial release

1.13.6.24 Updated PEC_POWER Pin outs

Part Numbers Added + Document Links

Changed flash to 128Mb

Replaced 5V DC/USB power mux with pin header

Changed power sub-system

Epiphany now uses 1.8V IO voltage

Added UART 2-pin header

Changed license to creative common

1.13.7.27 Added UART interface back to PEC_POWER

Added test points for SYS_5V and 1P0V

Added 2-pin header for 5V mounting hole

14.04.15 Removed second USB port “PC connection” as supported feature

No longer supporting the USB-OTG (only host mode)

14.09.09 Removed reference to reset button

Remove reference to 2nd USB port

Added numerous tables, design details

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Related Documents

Epiphany Architecture Reference Manual:

http://www.adapteva.com/docs/epiphany_arch_ref.pdf

Epiphany SDK Reference Manual:

http://www.adapteva.com/docs/epiphany_sdk_ref.pdf

Epiphany-III Datasheet:

http://www.adapteva.com/docs/e16g301_datasheet.pdf

Epiphany-IV Datasheet:

http://www.adapteva.com/docs/e64g401_datasheet.pdf

Software Repositories:

Parallella Hardware and Software Repository

https://github.com/parallella

Epiphany SDK Software Repository

https://github.com/adapteva

SD Card Images:

ftp://ftp.parallella.org

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Table of Contents

Contents

1 Overview..................................................................................................................................... 9

Table 1: Parallella Feature Summary ............................................................................................................ 9

Figure 1: The Parallella Board (top view).................................................................................................... 10

Figure 2: The Parallella Board (bottom view) ............................................................................................. 10

Figure 3: Zynq Connectivity Diagram .......................................................................................................... 11

Figure 4: Parallella High Level Architecture ................................................................................................ 12

2 Quick Start Guide...................................................................................................................... 13

Step1: Ensure that you have the required accessories.........................................................................13

Step 2: Create a bootable micro-SD card .............................................................................................. 13

Step 3: Familiarize yourself with known issues .................................................................................... 13

Step 4. Connect peripherals, fit the heat-sink and apply power.......................................................... 14

Step 5: Build and run a program............................................................................................................ 14

3 Feature Descriptions................................................................................................................. 15

3.1 Introduction ................................................................................................................................ 15

3.2 CPU..............................................................................................................................................15

3.3 Epiphany Coprocessor.................................................................................................................17

3.4 SDRAM ........................................................................................................................................ 17

3.5 Flash ............................................................................................................................................ 17

3.6 Gigabit Ethernet.......................................................................................................................... 18

3.7 USB 2.0 Host Port........................................................................................................................ 18

3.8 Micro SD...................................................................................................................................... 18

3.9 HDMI Port ...................................................................................................................................18

3.10 LED Indicators .............................................................................................................................18

3.11 Serial Port.................................................................................................................................... 18

3.12 I2C ...............................................................................................................................................18

3.13 Audio ...........................................................................................................................................18

3.14 Analog Input................................................................................................................................ 18

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3.15 JTAG Debugging ..........................................................................................................................18

3.16 Powering the board .................................................................................................................... 18

3.17 Parallella On-Board Power Management ...................................................................................19

3.18 Parallella Supply Outputs............................................................................................................20

3.19 Parallella Expansion Connectors................................................................................................. 20

3.20 Mounting Holes........................................................................................................................... 22

4 Parallella System Architecture.................................................................................................. 23

4.1 Zynq Memory Map......................................................................................................................23

4.2 Epiphany Memory Map ..............................................................................................................24

4.3 Epiphany Specific FPGA Resources .............................................................................................25

5 Board Configuration ................................................................................................................. 27

5.1 FPGA Pin Assignment .................................................................................................................. 27

6 Booting the Parallella................................................................................................................ 32

7 Parallella Expansion Connector Details .................................................................................... 33

7.1 PEC_POWER................................................................................................................................33

7.2 PEC_FPGA.................................................................................................................................... 36

7.3 PEC_NORTH/PEC_SOUTH ...........................................................................................................38

8 Electrical and Performance Specifications ............................................................................... 43

8.1 Dimensions and Weight.............................................................................................................. 43

8.2 Power Consumption ................................................................................................................... 43

8.3 Performance Metrics ..................................................................................................................43

8.4 IC Metrics Summary.................................................................................................................... 44

9 About the Parallella Board........................................................................................................ 45

9.1 Design Information ..................................................................................................................... 45

9.2 Build Options............................................................................................................................... 45

9.3 Contributors................................................................................................................................ 46

9.4 Attributions ................................................................................................................................. 47

9.5 Licensing...................................................................................................................................... 47

9.6 Disclaimers ..................................................................................................................................48

9.7 Warranty ..................................................................................................................................... 50

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List of Figures

Figure 1: The Parallella Board (top view)....................................................................................................10

Figure 2: The Parallella Board (bottom view) ............................................................................................. 10

Figure 3: Zynq Connectivity Diagram .......................................................................................................... 11

Figure 4: Parallella High Level Architecture ................................................................................................ 12

Figure 5: Power Management ....................................................................................................................19

Figure 6: PEC Placement Diagram...............................................................................................................21

Figure 7: Parallella Expansion Connectors (PEC) ........................................................................................ 21

Figure 8: Daughter Card Configurations ..................................................................................................... 22

Figure 9: Zynq Memory Map.......................................................................................................................23

Figure 10: Epiphany Memory Map ............................................................................................................. 24

List of Table

Table 1: Parallella Feature Summary ............................................................................................................ 9

Table 2: Parallella IC summary....................................................................................................................15

Table 3: Zynq Feature Summary ................................................................................................................. 16

Table 4: Epiphany System Registers ........................................................................................................... 26

Table 5: Zynq Bank32 Pin Assignments.......................................................................................................28

Table 6: Zynq Bank 34 Pin Assignments...................................................................................................... 30

Table 7: Zynq Bank 13 Pin Assignments......................................................................................................31

Table 8: PEC_POWER Signal Summary ....................................................................................................... 34

Table 9: PEC_POWER Pin Mapping ............................................................................................................. 35

Table 10: PEC_FPGA Signal Summary ......................................................................................................... 36

Table 11: PEC_FPGA Pin Mapping............................................................................................................... 37

Table 12: PEC_NORTH/SOUTH Signal Summary .........................................................................................38

Table 13: PEC_NORTH Pin Mapping for Parallella-16.................................................................................39

Table 14: PEC_NORTH Pin Mapping for Parallella-64.................................................................................40

Table 16: PEC_SOUTH Pin Mapping for Parallella-16 .................................................................................41

Table 17: PEC_SOUTH Pin Mapping for Parallella-64 .................................................................................

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Table 18: Dimensions and Weight .............................................................................................................. 43

Table 19: Power Consumption....................................................................................................................43

Table 20: Paralllella Performance Summary............................................................................................... 44

Table 21: IC Metrics .................................................................................................................................... 44

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