Pentek 4283 User manual

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Pentek Model 4283 Operating Manual Page 1
Manual Part No: 800.42830 Rev.: G.1 - January 26, 1999
Pentek, Inc.
One Park Way
Upper Saddle River, NJ 07458
[phone]
http://www.pentek.com/
Copyright ©1991 - 1999
OPERATING MANUAL
MODEL 4283
TMS320C30 DSP-Based
MIX Baseboard for VMEbus Systems
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Page 2 Pentek Model 4283 Operating Manual
Pentek Model 4283 Operating Manual - Revision History
WARRANTY
Pentek warrants that all products manufactured by Pentek conform to published Pentek specifications and are free from defects in materials and
workmanship for a period of one year from the date of delivery when used under normal operating conditions and within the service conditions
for which they were furnished.
The obligation of Pentek arising from a warranty claim shall be limited to repairing or at its option, replacing without charge, any product which in
Pentek’s sole opinion proves to be defective within the scope of the warranty.
Pentek must be notified in writing of the defect or nonconformity within the warranty period and the affected product returned to Pentek within
thirty days after discovery of such defect or nonconformity.
Buyer shall prepay shipping charges, taxes, duties and insurance for products returned to Pentek for warranty service. Pentek shall pay for the
return of products to buyer except for products returned from another country.
Pentek shall have no responsibility for any defect or damage caused by improper installation, unauthorized modification, misuse, neglect, inade-
quate maintenance, accident or for any product which has been repaired or altered by anyone other than Pentek or its authorized representatives.
The warranty described above is buyer’s sole and exclusive remedy and no other warranty, whether written or oral, is expressed or
implied. Pentek specifically disclaims fitness for a particular purpose. Under no circumstances shall Pentek be liable for any direct,
indirect, special, incidental or consequential damages, expenses, losses or delays (including loss of profits) based on contract, tort, or
any other legal theory.
COPYRIGHT
Copyright © 1991 - 1999, Pentek, Inc. All Rights Reserved. Contents of this publication may not be reproduced in any form
without written permission.
Date Rev Applicable Serial #’s Comments
01/14/98 G 9405001 - Forward Section 2.10 - Wire jumper is soldered to pins 2 and 3 of jumper block position J6; this prevents the
unintentional selection of the internal ROM
01/26/98 G.1 9405001 - Forward Section 3.6 - Previously stated that ‘C30 Control Regis-
ter is write only; corrected to state that it is Read/Write.
Added - Section 7.10 Writing Programming Code to
the EPROM
Added - Appendix B -Model 4283 bootcode
Printed in the United States of America.
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Pentek Model 4283 Operating Manual Page 3
Page
Table of Contents
Rev.: G.1
Chapter 1: Overview
1.1 Introduction............................................................................................................................................ 9
1.2 System Configuration ........................................................................................................................... 9
1.3 Software Development Support ......................................................................................................... 9
1.4 Specifications........................................................................................................................................ 11
1.5 Block Diagram...................................................................................................................................... 12
Figure 1-1: Block Diagram ................................................................................................................. 12
1.5.1 TMS320C30 ..........................................................................................................................12
1.5.2 Primary Data and Address Bus .......................................................................................13
1.5.3 Expansion Bus .....................................................................................................................13
1.5.4 Host Control Register ........................................................................................................13
1.5.5 Single Level Bus Arbiter ....................................................................................................13
1.5.6 Interrupt Handler ...............................................................................................................13
1.5.7 Interrupt Generator and IACK Vector Register ............................................................13
1.5.8 Static RAM ...........................................................................................................................13
1.5.9 EPROM ................................................................................................................................14
1.5.10 VMEbus Master Interface .................................................................................................14
1.5.11 Dual Port DRAM ................................................................................................................14
Chapter 2: Installation
2.1 Introduction.......................................................................................................................................... 15
2.2 Selecting DRAM Memory Size.......................................................................................................... 15
Figure 2-1: Jumper Block J1 - 4 MB Dram......................................................................................15
Table 2-1: Memory Size Jumpers .....................................................................................................15
Figure 2-2: Component, Switch and Jumper Block Placement..................................................16
2.3 Selecting the Host Control & IACK Vector Register Base Address ............................................ 17
Table 2-2: Host Control Register and IACK Vector Register Address Jumpers ....................17
Figure 2-3: A16_base Address jumpers Set for 0x0080.................................................................18
2.4 Selecting VMEbus Interrupter Level................................................................................................ 18
Figure 2-4: Jumper block J1 for interrupt requester level 3........................................................18
Table 2-3: IRQ and IACK Vector Address Jumpers.....................................................................18
2.5 Selecting VMEbus Interrupt Handler Level ................................................................................... 19
Table 2-4: VMEbus Interrupt Source Selection Jumpers ............................................................19
Figure 2-5: Jumper Block J4 - Host Control Register, IRQ6 and IRQ7 ....................................19
2.6 Selecting VMEbus Bus Request Level - Bus Master Interface ..................................................... 20
Figure 2-6: Jumpers Installed for Bus Request level BRQ2........................................................20
Table of Contents
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Page 4 Pentek Model 4283 Operating Manual
Page
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Rev.: G.1
2.7 Selecting Bus Arbiter Operation - Level 3....................................................................................... 20
Table 2-6: Bus Arbiter Jumpers Installed - Level 3 ...................................................................... 20
Figure 2-7: J7 Configured for Bus Arbiter Operation .................................................................. 20
Table 2-5: Bus Request Level Selection Jumpers ......................................................................... 20
2.8 SYSRST INPUT & OUTPUT Jumpers.............................................................................................. 21
Figure 2-7: SYSRST Jumpers............................................................................................................. 21
2.9 Driving VMEbus SYSCLK.................................................................................................................. 21
Figure 2-8: SYSCLK Jumper.............................................................................................................. 21
2.10 Selecting Internal ROM...................................................................................................................... 21
Figure 2-9: ROM Jumper - External Mode Selected .................................................................... 21
2.11 Factory Default Jumper Settings ...................................................................................................... 22
Figure 2-10: Factory Default Jumpers (1 MB Dram Option) ...................................................... 22
Figure 2-11: Factory Default Jumpers (4 MB Dram Option) ...................................................... 23
Figure 2-12: Factory Default Jumpers (8 MB Dram Option) ...................................................... 23
Chapter 3: TMS320C30 Memory Map
3.1 Introduction ......................................................................................................................................... 25
3.2 TMS320C30 Memory Map................................................................................................................. 25
3.3 EPROM - 'C30 Address 0x0000 0000 through 0x0000 7FFF ........................................................ 25
3.4 Static RAM - 'C30 Address 0x0010 0000 through 0x0010 FFFF.................................................... 25
3.5 DRAM - 'C30 Address 0x0020 0000 through 0x003F FFFF........................................................... 25
Table 3-1: Dram Organization .......................................................................................................... 25
Table 3-2: TMS320C30 Memory Map.............................................................................................. 26
3.6 TMS320C30 Control Register - Read/Write @ 'C30 Address 0x0080 0000 ............................... 27
3.6.1 SRST - Bit 0 - Active on Low-to-High Edge ................................................................ 27
Figure 3-1: Reset Circuitry Schematic Diagram........................................................... 27
Table 3-3: ‘C30 Control Register - ‘C30 Address 0x0080 0000 ................................... 27
3.6.2 IACK1, IACK2and IACK3................................................................................................ 28
3.6.3 VMEINT - Bit 4 - Active HIGH ........................................................................................ 28
Figure 3-2: Interrupt Generator Circuitry ..................................................................... 28
3.6.4 TRSEL0 through TRSEL3 (Transfer Select Bits) - Bits 5, 6, 8, and 9 .......................... 28
3.6.4.1 Longword (32-bit) Memory Cycle ............................................................... 29
Table 3-4: Transfer Select (TRSEL) Bit Functions....................................................... 29
3.6.4.2 Word (16-bit) Memory Cycle (Double Cycle) ........................................... 30
3.6.4.3 Word (16-bit) Memory Cycle (Single Cycle) ............................................. 30
3.6.4.4 Byte (8-bit) Memory Cycle (Single Cycle) .................................................. 30
3.6.4.5 IACK Cycle ...................................................................................................... 30
3.6.5 LOCK - Bit D7 - Active HIGH .......................................................................................... 30
3.7 Interrupt Status Register - 'C30 Address 0x0080 0800................................................................... 31
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Pentek Model 4283 Operating Manual Page 5
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Rev.: G.1
3.8 VMEbus Address Modifier Register -'C30 Address 0x0080 0001 (Write Only)......................... 31
Table 3-5: Interrupt Status Register -’C30 Address 0x0080 0800................................................31
Table 3-6: VMEbus Address Modifier Register ............................................................................31
3.9 Page Address Register - 'C30 Address 0x0080 0002 (Write Only).............................................. 32
Table 3-7: Address Modifier Codes .................................................................................................32
Table 3-8: Page Address Register .....................................................................................................32
3.10 VMEbus IACK Address Register - 'C30 Address 0x0080 0003 (Write Only) ............................ 33
3.11 MIX Expansion Bus Address Region - 'C30 Address 0x0080 4000 thru 0x0080 5FFF .............. 33
Table 3-9: VMEbus IACK Address Register..................................................................................33
3.12 'C30 Internal RAM - 'C30 Address 0x0080 9800 through 0x0080 9FFF....................................... 34
3.13 VMEbus IACK Cycle Address - 'C30 Address 0x0080 A000 through 0x008F FFFF.................. 34
3.14 VMEbus Bus Master Access - 'C30 Address 0x00C0 0000 through 0x00FF FFFF ..................... 34
3.15 'C30 Internal Memory Mapped Registers - 'C30 Address 0x0080 8000 thru 0x0080 9FFF...... 34
Table 3-10: ‘C30 Internal Ram Address Map .................................................................................34
Table 3-11: ‘C30 Internal Memory Mapped Registers .................................................................34
Chapter 4: VMEbus Memory Map
4.1 Introduction.......................................................................................................................................... 35
4.2 VMEbus Addresses.............................................................................................................................. 35
4.2.1 Address Modifier Codes ...................................................................................................35
Table 4-1: Address Modifier Codes ................................................................................ 35
4.3 VMEbus Memory Map ....................................................................................................................... 36
4.4 Addressing the DRAM - VMEbus Access........................................................................................ 36
Table 4-2: VMEbus Memory Map....................................................................................................36
4.4.1 A32 DRAM Access ..............................................................................................................37
Figure 4-1: Base Address Switches .................................................................................37
4.4.1.1 A32 DRAM Access - 8 MByte Option .........................................................38
4.4.1.2 A32 DRAM Access - 4MByte Option .........................................................38
4.4.1.3 A32 DRAM Access - 1 MByte Option .........................................................39
Figure 4-2: Base Address Switches (A32) ..................................................39
4.4.2 A24 DRAM Access ..............................................................................................................40
Figure 4-3: A24 Base Address Switch.............................................................................40
4.4.2.1 A24 DRAM Access - 8 MByte Option .........................................................40
4.4.2.2 A24 DRAM Access - 4 MByte Option .........................................................41
4.4.2.3 A24 DRAM Access - 1 MByte Option .........................................................41
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Page 6 Pentek Model 4283 Operating Manual
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Rev.: G.1
4.5 Host Control and IACK Vector Registers ....................................................................................... 42
4.5.1 Host Control Register ........................................................................................................ 42
4.5.1.1 HOST INT - Bit 1 ............................................................................................ 42
Table 4-3: Host Control Register................................................................. 42
4.5.1.2 HOSTRST - Bit 0 ............................................................................................. 43
Figure 4-5: HOSTRST Diagram .................................................................. 43
4.5.2 IACK Vector Register ........................................................................................................ 43
Table 4-4: IACK Vector Register - VMEbus Address A16 Base............................... 43
Chapter 5: MIX Expansion Bus
5.1 Introduction ......................................................................................................................................... 45
5.2 MIX Baseboard - Model 4283 ............................................................................................................ 45
5.3 Expansion Modules (MIX modules) ................................................................................................ 45
5.4 MIX Bus Connector Signals............................................................................................................... 46
Table 5-1:MIX Bus Signals ................................................................................................................ 46
5.5 MIX Module Interface Timing .......................................................................................................... 49
Figure 5-1: MIX Module Interface Timing Diagram.................................................................... 49
Table 5-2: Module Interface Timing .............................................................................................. 49
5.6 Addressing the MIX Expansion Modules...................................................................................... 50
Table 5-3: Page Address Register..................................................................................................... 50
5.7 Servicing Interrupts for MIX Modules ............................................................................................ 51
Figure 5-2: MIX Interrupts to ‘C30................................................................................................... 51
Chapter 6: Interfaces
6.1 Auxiliary Port Connector ................................................................................................................... 53
Figure 6-1: Auxiliary Port Connector............................................................................................... 53
Table 6-1: Auxiliary Port Connector................................................................................................ 53
6.2 XDS Emulator Connector .................................................................................................................. 54
Figure 6-2: XDS Connector Pin-out ................................................................................................. 54
6.3 Reset Switch ......................................................................................................................................... 54
6.4 XF0 LED ................................................................................................................................................ 54
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Pentek Model 4283 Operating Manual Page 7
Page
Table of Contents
Rev.: G.1
Chapter 7: Operating Procedures
7.1 Introduction.......................................................................................................................................... 55
7.2 Handling Interrupts............................................................................................................................ 55
Table 7-1: Reset and Interrupt Vectors - TMS320C30..................................................................55
7.2.1 Interrupt Vectors ................................................................................................................56
7.2.2 Delayed Branch Table .......................................................................................................56
7.2.3 Reset Vector .........................................................................................................................57
7.3 Starting Program Execution............................................................................................................... 57
7.4 Reset Operation ................................................................................................................................... 58
Figure 7-1: Reset Circuit Schematic .................................................................................................58
7.5 VMEbus Interrupter Operation ........................................................................................................ 59
Figure 7-2: Interrupt Generator Circuitry.......................................................................................60
Table 7-2: IRQ and IACK Vector Address Jumpers.....................................................................60
7.6 VMEbus Interrupt Handler Operation............................................................................................ 61
7.7 VMEbus Requester (Bus Master) Operation................................................................................... 62
7.8 VMEbus Arbiter Operation................................................................................................................ 65
7.9 Bus Grant Bypass................................................................................................................................. 65
7.10 Writing Programming Code to the EPROM................................................................................... 65
Table 7-3: Bus Grant Bypass Jumpers .............................................................................................65
Appendix A: Programming Example
A.1 MIX Module Interrupt Service Routine......................................................................................... A-1
Appendix B: Model 4283 Bootcode
B.1 General Information.......................................................................................................................... B-1
asm.bat................................................................................................................................ code page - 1
prom30.cmd (Linker Command File.............................................................................code page - 2
prom30.asm (TMS320C30)............................................................................................... code page - 3
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Page 8 Pentek Model 4283 Operating Manual
Page
Table of Contents
Rev.: G.1
This page is intentionally blank
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Pentek Model 4283 Operating Manual Page 9
Rev.: G.1
Chapter 1: Overview
1.1 Introduction
The Model 4283 Processor Board for VMEbus is based on the Texas Instruments
TMS320C30 Floating Point Digital Signal Processor. It features the 32 MFlop TMS320C30
DSP chip, up to 8MBytes of dual-ported DRAM, 256 kBytes of high-speed SRAM, and
128 kByte of EPROM. An expansion connector utilizing the MIX bus supports a growing
family of digital and analog I/O modules and co-processor expansion modules.
Since the Model 4283 may function as a VMEbus master and/or system controller, the
TMS320C30 may access VMEbus resources simply by reading or writing to certain
portions of its memory map. When installed in Slot 1, the Model 4283 can drive the
system clock and reset signals and function as the bus arbiter. The DRAM on the Model
4283 is available as a VMEbus memory slave relocatable on 1, 4, or 8 Mbyte address
boundaries.
This manual will describe the installation and operation of the Model 4283 in several
typical VMEbus environments.
1.2 System Configuration
The Model 4283 can be tailored to many different types of systems. Here are a few of the
typical application environments:
Stand-alone The Model 4283 can act as the main executive processor in the
Processor system. In this case the unit may contain executable code stored in
EPROM and boot directly. Acting as a VMEbus master, it can access other
devices on the VMEbus.
DSP & Data When combined with the data acquisition, digital and analog I/O
Acquisition and co-processor MIX expansion modules, the Model 4283 can
Sub-System perform complete DSP, control, and communications functions. It
can participate in a larger multi-master VMEbus system as a
high-powered node.
Application With a VMEbus host operating system in place, such as MS-DOS,
Accelerator SUN UNIX, and other UNIX systems with C language support, the Model
4283 can act as an host application accelerator and as a pre-processor for
the data acquisition expansion modules.
1.3 Software Development Support
No DSP hardware product offering is complete without a full complement of
development software. Software products that support the Model 4283 are described on
the next page.
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Page 10 Pentek Model 4283 Operating Manual
Rev.: G.1
1.3 Software Development Support (continued)
SwiftTools Pentek’s SwiftTools is a complete software development environment
for PC-AT and SUN workstations. It is tailored to work directly with
Pentek’s family of digital signal processing products which incorpo-
rate TMS320C40 and TMS320C30 digital signal processors. SwiftTools
integrates all of the operations involved in a typical software develop-
ment project and supports full C language source code generation and
debugging with a comprehensive suite of powerful tools for a wide
range of applications. SwiftTools includes an in-line assembler and
dis-assembler for on-screen changes to object code in RAM. Registers
can be examined and loaded, memory regions can be examined, filled,
and moved. Full file uploading and downloading routines are pro-
vided and provisions for EPROM byte manipulation are included.
SwiftNet Pentek’s SwiftNet is a software product that supports a network of
distributed VMEbus systems connected via Ethernet to a host com-
puter, such as a SUN workstation or PC-AT. All software develop-
ment tools are run on the host with remote target access provided
transparently to the user. SwiftNet utilizes the industry standard
TCP/IP interface for Ethernet, making it quite portable across many
OS environments.
Macro The assembler translates assembly language source code into machine
language object files in common object file format (COFF). The linker
section combines the COFF object files into an executable object mod-
ule. The archiver supports a macro library accessible by the assembler.
C Compiler The compiler is a full implementation of Kernighan and Ritchie C lan-
guage, generating assembly language compatible with the Macro
Assembler/Linker. Time critical assembly language routines are call-
able within the C program.
SPOX SPOX is a real-time kernel operating system featuring a set of high-
level C-callable routines for host system interfaces (standard I/O rou-
tines) and a complete DSP math library. SPOX speeds up program
development and supports the development of real time applications
written in C.
XDS-500 The Texas Instruments XDS500 Emulator allows the user to access the
‘C30 through a ‘back door’ port provided by a special 12-pin connector
on the board. The emulator board is installed in a PC/AT computer
where all software development can take place.
Bus Adaptors Pentek offers bus adaptors to provide a connecting link between the
computer your ‘C30 programs will be developed on and the VMEbus
card cage where those programs will be run. Supported platforms
include PC/AT compatibles, SUN SPARCStations and HP Worksta-
tions.
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Pentek Model 4283 Operating Manual Page 11
Rev.: G.1
1.4 Specifications
Processor: Texas Instruments TMS320C30
Processor Clock:
Standard: 32 MHz
Option 400: 40 MHz
Dual-Port DRAM:
Size:
Standard: 256k x 32 (1 MByte)
Option 002: 1M x 32 (4 MBytes)
Option 007: 2M x 32 (8 MBytes)
Arbitration: Hardware, fully transparent
'C30 Access: Memory mapped on primary bus - 3 wait states
VMEbus Access: 1, 4 or 8 MBytes slave memory - Relocatable on 1 MByte
boundaries - 250 ns cycle time
Static RAM:
Size: 64k x 32 (256 kB)
'C30 Access: Memory mapped on primary bus - 0 wait states
EPROM:
Size: 32K x 32 (128kB)
'C30 Access: Memory mapped on primary bus - 1 wait state
Expansion Bus:
Type: Conforms to Intel MIX Bus Specification
Width: 32-bits for data and address
Speed: 11 MBytes/sec typical
XDS Connector: 12-pin Connector for Texas Instruments XDS-500 Emulator
Serial I/O Connector: Front Panel 17-pin connector for serial ports, timers, & flags
VMEbus Compliance:
Bus Master: D32 A32 I(1-7) IH(1-7)
Slave: D32 A32
Physical:
Dimensions: 6U Eurocard - (160 mm x 233.35 mm)
Multilayer construction.
Power: + 5V DC @ 3 A max.
+12V DC @ 0 A (passed through to MIX modules only)
-12V DC @ 0 A (passed through to MIX modules only)
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Page 12 Pentek Model 4283 Operating Manual
Rev.: G.1
1.5 Block Diagram
The block diagram of the Model 4283 is shown below. Each of the major elements will be
described below. Each element which appears in the TMS320C30 address map has the
'C30 hex address shown next to it. The arrows show flow of data and/or control,
depending on the function
.
1.5.1 TMS320C30
The TMS320C30 processor is the central feature of the unit. It acts as the exec-
utive for all data transfers within the board, over the MIX expansion bus, and
to the VMEbus. It also serves as a powerful 32 Mflop floating-point digital sig-
nal processor and a complete DMA controller which runs concurrently with
the CPU. Other internal features of the 'C30 are: a 64 x 32 instruction cache,
two 1k x 32 RAM's, eight extended precision registers, two address generators,
two serial ports, two counter timers, and two general purpose I/O flags. The
'C30 has become an industry standard for floating point DSP applications and
is widely supported with software products from various vendors.
Figure 1-1: Model 4283 - Block Diagram
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Pentek Model 4283 Operating Manual Page 13
Rev.: G.1
1.5 Block Diagram (continued)
1.5.2 Primary Data and Address Bus
This bus serves as the local data and address bus for the board. The 32-bit
data bus connects the major board resources to the 'C30 including the SRAM,
EPROM, DRAM, and the VMEbus Master Interface. The 24-bit address bus is
sufficient for memory mapping all of these resources directly.
1.5.3 Expansion Bus
This 32-bit data bus serves as the path for the MIX expansion bus as well as
four auxiliary registers: the C30 Control Register, the VME Address Modifier
Register, VMEbus and MIXbus Page Register, and VMEbus IACK register. Its
13-bit address bus drives the lower 13-bits of the MIX bus for direct accessing
of the MIX expansion modules.
1.5.4 Host Control Register
This register is addressable in A16 space on the VMEbus and controls reset
and interrupt functions to the TMS320C30.
1.5.5 Single Level Bus Arbiter
When enabled, the Model 4283 can be placed in slot 1 and function as a
VMEbus arbiter for bus requests on level 3.
1.5.6 Interrupt Handler
The Model 4283 will respond to VMEbus interrupts on any of 7 levels and
interrogate the interrupt generator with interrupt acknowledge bus cycles.
1.5.7 Interrupt Generator and IACK Vector Register
The 'C30 can generate an interrupt on any of 7 levels on the VMEbus by
setting a control register bit. The IACK Vector Register stores the ID byte
which is sent over the bus in response to an IACK cycle.
1.5.8 Static RAM
The 256 kByte Static RAM is organized as 64k x 32 and features 0 wait state
operation. It is ideal for program and data storage where fast access is
required.
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Page 14 Pentek Model 4283 Operating Manual
Rev.: G.1
1.5 Block Diagram (continued)
1.5.9 EPROM
The EPROM is organized as 32k x 32 and is implemented with four socketed
32k x 8 devices. These EPROM's may be removed from the unit and re-
programmed for non-volatile program and data storage. By setting a jumper,
the Model 4283 can begin executing a program from the EPROM.
1.5.10 VMEbus Master Interface
The Model 4283 can access data on the VMEbus by performing reads and
writes in A16, A24, and A32 address space with data widths of 8, 16, and 32
bits. The bottom 24 bits are directly addressed by the TMS320C30 while the
upper 8 bits are determined by the Page Register.
1.5.11 Dual Port DRAM
The dual port DRAM is available in sizes of 1, 4, and 8 MBytes. It is a
organized with a 32-bit wide data field and can be accessed directly by both
the TMS320C30 and the VMEbus. Full arbitration logic is employed on a
cycle-to-cycle basis.
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Pentek Model 4283 Operating Manual Page 15
Rev.: G.1
Chapter 2: Installation
2.1 Introduction
This chapter contains information and instructions for the configuration and various
modes of operation of the Model 4283. These are achieved by setting jumpers and
switches on the board before it is installed in the VMEbus card cage.
The Model 4283 supports a number of expansion modules which are attached to the MIX
stacking connector. These modules and the MIX interface system are described in
Appendix A of this manual. It is recommended to wait until the Model 4283 has been
successfully installed by itself before attaching any expansion modules since this would
make access to the switches and jumpers more difficult.
Figure 2-2, on Page 16, is a component placement drawing of the Model 4283 PC Board,
showing the switches and jumper blocks referred to in the sections below.
2.2 Selecting DRAM Memory Size
The dual-port DRAM appears as a VMEbus slave device at a base memory address
selected by switches SW1 and SW2. The base address is the VMEbus address
corresponding to the bottom (or lowest address) of the DRAM. Detailed instructions for
setting these DRAM base address switches is contained in Section 4.4, Page 36.
The size of the DRAM is set at the factory and normally should not be changed. The
three memory size options are 1M, 4M and 8 MB. The memory size configuration
jumper s are shown for a 4 MB case in Figure 2-1, below.
Table 2-1: Model 4283 - Memory Size Jumpers
Memory Size Jumpers Installed SW1 Selections set to ‘open’
1 MB J1-3, 20 J1-2, 19 J1-1, 18 -
4 MB J1-3, 20 - - SW1-1&2
8 MB - - - SW1-1, 2, &3
Figure 2-1: Model 4283 - Jumper Block J1
shown with jumpers installed for 4 MB Dram
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Page 16 Pentek Model 4283 Operating Manual
Rev.: G.1
Figure 2-2: Model 4283 - Component, Switch and Jumper Block Placement
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Pentek Model 4283 Operating Manual Page 17
Rev.: G.1
2.3 Selecting the Host Control & IACK Vector Register Base Address
The Host Control Register allows a VMEbus Bus Master to control the reset and interrupt
lines into the 'C30. The IACK Vector Register is an 8-bit register loaded from the
VMEbus which stores a vector which the Model 4283 sends in response to an interrupt
acknowledge cycle.
Both of these registers are mapped into the bottom 1k locations of 16-bit Address Space
for AM Codes 29 and 2D. This corresponds to VMEbus Address 0x0000 through 0x03FF.
This 1k region is divided into sixteen 64-byte locations, one of which is selected by setting
four jumpers on jumper block J4. If there is more than one Model 4283 in a card cage,
these jumpers must be set to uniquely configure a different base addresses for the 64-
byte region on each board. This address will be called the A16_base address.
For any given board, the IACK Vector Register is mapped at the A16_base address and
the Host Control Register is mapped at A16_base+0x0002. Table 2-2, below, defines the
addresses of these registers for all 16 jumper configurations. Please refer to Section 4.5,
Page 42, for more details.
Table 2-2: Model 4283 - Host Control Register and
IACK Vector Register Address Jumpers
IACK
Vector
Register
Host
Control
Register
J4-
12,29
J4-
11,28
J4-
10,27
J4-
9,26
00000002XXXX
0040 0042 X X X
0080 0082 X X X
00C0 00C2 X X
0100 0102 X X X
0140 0142 X X
0180 0182 X X
01C0 01C2 X
0200 0202 X X X
0240 0242 X X
0280 0282 X X
02C0 02C2 X
0300 0302 X X
0340 0342 X
0380 0382 X
03C0 03C2
X = jumper installed
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Page 18 Pentek Model 4283 Operating Manual
Rev.: G.1
2.3 Selecting the Host Control & IACK Vector Register Base Address (cont.)
2.4 Selecting VMEbus Interrupter Level
As a VMEbus Interrupter, the Model
4283 can generate interrupts to the
VMEbus. Besides driving one of the
bus interrupt lines low, an interrupter
must also respond to an interrupt
acknowledge bus cycle (IACK cycle).
This requires that the interrupter
recognizes a 3-bit IACK address and
sends an 8-bit IACK Vector over the
data bus so that the interrupt handler
can determine the identity of the
requester. This 8-bit IACK Vector is
programmable over the bus and is
described in Figure 2-3 and Section 4.5.2, Page 43.
These two requirements of an
interrupter (driving an interrupt line
and responding to an IACK cycle) are
configured by setting two groups of
jumpers. The IRQ jumpers
determine which interrupt line is
driven and the IACK Address
jumpers determine the 3-bit IACK
address. The two groups of jumpers
must always agree in interrupt
level. Note that only one interrupt
level is permitted.
These two requir ements of an interrupter (driving an i nterrupt line and respondi ng to an IACK cycle) are configu red by setting two groups of jump ers. The IRQ jumpe rs determine which inte rrupt line is driven and the IACK Addr ess jumpers determin e the
3-bit IACK addre ss. The two group s of jumpers must always ag ree in interrupt level. Note that only on ei nterrupt level is permitted.
Figure 2-3: Model 4283 -
A16_base Address jumpers Set for 0x0080
Figure 2-4: Model 4283 - Jumper block
J1 shown with jumpers installed for
interrupt requester level 3
Table 2-3: Model4283 -
IRQ and IACK Vector Address Jumpers
Int
Level
IRQ
Jumper
IACK Vector
Address Jumpers
1 J1-17,34 J1-10,27 and J1-8,25
2 J1-16,33 J1-10,27 and J1-7,24
3 J1-15,32 J1-10,27
4 J1-14,31 J1-8,25 and J1-7,24
5 J1-13,30 J1-8,25
6 J1-12,29 J1-7,24
7 J1-11,28 none
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Pentek Model 4283 Operating Manual Page 19
Rev.: G.1
2.5 Selecting VMEbus Interrupt Handler Level
As a VMEbus Interrupt Handler, the
Model 4283 can respond to any of
nine interrupt sources: the 7 IRQ
lines on the VMEbus, bit 1 of the
Host Control Register and the
VMEbus Timeout Interrupt.
Jumper block J4 is used to select
which interrupt sources drive the
INT0 pin of the TMS320C30. Up to
four interrupts can be connected at a
time: one from each of the four
groups shown in Table 2-4. Group 1
includes the Host Control Register
Interrupt and VMEbus lines IRQ1
through IRQ7. Only one jumper can
be connected at a time within Group
1. Groups 2 and 3 support IRQ6 and
IRQ7. The VME Bus Timeout
interrupt in Group 4 is always
enabled and no jumpering is required.
Jumper J4 is shown to the right
configured for handling interrupts
from four sources: the VMEbus timeout
bit, the Host Control Register and
VMEbus lines IRQ6 and IRQ7.
Table 2-4: Model 4283 -
VMEbus Interrupt Source
Selection Jumpers
Interrupt Source Jumper Group Notes
Host Central Reg J4-1,18
1
Only One at a time
IRQ1 J4-2,19
IRQ2 J4-3,20
IRQ3 J4-4,21
IRQ4 J4-5,22
IRQ5 J4-6,23
IRQ6 J4-7,24
IRQ7 J4-8,25
IRQ6 J4-13,30 2
IRQ7 J4-14,31 3
Bus Timeout Always
Enabled 4
Figure 2-5: Model 4283 - Jumper Block J4
configured for Host Control Register,
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