Pentek 4283 User manual

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Pentek Model 4283 Operating Manual Page 1
Manual Part No: 800.42830 Rev.: G.1 - January 26, 1999
Pentek, Inc.
One Park Way
Upper Saddle River, NJ 07458
[phone]
http://www.pentek.com/
Copyright ©1991 - 1999
OPERATING MANUAL
MODEL 4283
TMS320C30 DSP-Based
MIX Baseboard for VMEbus Systems
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Page 2 Pentek Model 4283 Operating Manual
Pentek Model 4283 Operating Manual - Revision History
WARRANTY
Pentek warrants that all products manufactured by Pentek conform to published Pentek specifications and are free from defects in materials and
workmanship for a period of one year from the date of delivery when used under normal operating conditions and within the service conditions
for which they were furnished.
The obligation of Pentek arising from a warranty claim shall be limited to repairing or at its option, replacing without charge, any product which in
Pentek’s sole opinion proves to be defective within the scope of the warranty.
Pentek must be notified in writing of the defect or nonconformity within the warranty period and the affected product returned to Pentek within
thirty days after discovery of such defect or nonconformity.
Buyer shall prepay shipping charges, taxes, duties and insurance for products returned to Pentek for warranty service. Pentek shall pay for the
return of products to buyer except for products returned from another country.
Pentek shall have no responsibility for any defect or damage caused by improper installation, unauthorized modification, misuse, neglect, inade-
quate maintenance, accident or for any product which has been repaired or altered by anyone other than Pentek or its authorized representatives.
The warranty described above is buyer’s sole and exclusive remedy and no other warranty, whether written or oral, is expressed or
implied. Pentek specifically disclaims fitness for a particular purpose. Under no circumstances shall Pentek be liable for any direct,
indirect, special, incidental or consequential damages, expenses, losses or delays (including loss of profits) based on contract, tort, or
any other legal theory.
COPYRIGHT
Copyright © 1991 - 1999, Pentek, Inc. All Rights Reserved. Contents of this publication may not be reproduced in any form
without written permission.
Date Rev Applicable Serial #’s Comments
01/14/98 G 9405001 - Forward Section 2.10 - Wire jumper is soldered to pins 2 and 3 of jumper block position J6; this prevents the
unintentional selection of the internal ROM
01/26/98 G.1 9405001 - Forward Section 3.6 - Previously stated that ‘C30 Control Regis-
ter is write only; corrected to state that it is Read/Write.
Added - Section 7.10 Writing Programming Code to
the EPROM
Added - Appendix B -Model 4283 bootcode
Printed in the United States of America.
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Pentek Model 4283 Operating Manual Page 3
Page
Table of Contents
Rev.: G.1
Chapter 1: Overview
1.1 Introduction............................................................................................................................................ 9
1.2 System Configuration ........................................................................................................................... 9
1.3 Software Development Support ......................................................................................................... 9
1.4 Specifications........................................................................................................................................ 11
1.5 Block Diagram...................................................................................................................................... 12
Figure 1-1: Block Diagram ................................................................................................................. 12
1.5.1 TMS320C30 ..........................................................................................................................12
1.5.2 Primary Data and Address Bus .......................................................................................13
1.5.3 Expansion Bus .....................................................................................................................13
1.5.4 Host Control Register ........................................................................................................13
1.5.5 Single Level Bus Arbiter ....................................................................................................13
1.5.6 Interrupt Handler ...............................................................................................................13
1.5.7 Interrupt Generator and IACK Vector Register ............................................................13
1.5.8 Static RAM ...........................................................................................................................13
1.5.9 EPROM ................................................................................................................................14
1.5.10 VMEbus Master Interface .................................................................................................14
1.5.11 Dual Port DRAM ................................................................................................................14
Chapter 2: Installation
2.1 Introduction.......................................................................................................................................... 15
2.2 Selecting DRAM Memory Size.......................................................................................................... 15
Figure 2-1: Jumper Block J1 - 4 MB Dram......................................................................................15
Table 2-1: Memory Size Jumpers .....................................................................................................15
Figure 2-2: Component, Switch and Jumper Block Placement..................................................16
2.3 Selecting the Host Control & IACK Vector Register Base Address ............................................ 17
Table 2-2: Host Control Register and IACK Vector Register Address Jumpers ....................17
Figure 2-3: A16_base Address jumpers Set for 0x0080.................................................................18
2.4 Selecting VMEbus Interrupter Level................................................................................................ 18
Figure 2-4: Jumper block J1 for interrupt requester level 3........................................................18
Table 2-3: IRQ and IACK Vector Address Jumpers.....................................................................18
2.5 Selecting VMEbus Interrupt Handler Level ................................................................................... 19
Table 2-4: VMEbus Interrupt Source Selection Jumpers ............................................................19
Figure 2-5: Jumper Block J4 - Host Control Register, IRQ6 and IRQ7 ....................................19
2.6 Selecting VMEbus Bus Request Level - Bus Master Interface ..................................................... 20
Figure 2-6: Jumpers Installed for Bus Request level BRQ2........................................................20
Table of Contents
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Page 4 Pentek Model 4283 Operating Manual
Page
Table of Contents
Rev.: G.1
2.7 Selecting Bus Arbiter Operation - Level 3....................................................................................... 20
Table 2-6: Bus Arbiter Jumpers Installed - Level 3 ...................................................................... 20
Figure 2-7: J7 Configured for Bus Arbiter Operation .................................................................. 20
Table 2-5: Bus Request Level Selection Jumpers ......................................................................... 20
2.8 SYSRST INPUT & OUTPUT Jumpers.............................................................................................. 21
Figure 2-7: SYSRST Jumpers............................................................................................................. 21
2.9 Driving VMEbus SYSCLK.................................................................................................................. 21
Figure 2-8: SYSCLK Jumper.............................................................................................................. 21
2.10 Selecting Internal ROM...................................................................................................................... 21
Figure 2-9: ROM Jumper - External Mode Selected .................................................................... 21
2.11 Factory Default Jumper Settings ...................................................................................................... 22
Figure 2-10: Factory Default Jumpers (1 MB Dram Option) ...................................................... 22
Figure 2-11: Factory Default Jumpers (4 MB Dram Option) ...................................................... 23
Figure 2-12: Factory Default Jumpers (8 MB Dram Option) ...................................................... 23
Chapter 3: TMS320C30 Memory Map
3.1 Introduction ......................................................................................................................................... 25
3.2 TMS320C30 Memory Map................................................................................................................. 25
3.3 EPROM - 'C30 Address 0x0000 0000 through 0x0000 7FFF ........................................................ 25
3.4 Static RAM - 'C30 Address 0x0010 0000 through 0x0010 FFFF.................................................... 25
3.5 DRAM - 'C30 Address 0x0020 0000 through 0x003F FFFF........................................................... 25
Table 3-1: Dram Organization .......................................................................................................... 25
Table 3-2: TMS320C30 Memory Map.............................................................................................. 26
3.6 TMS320C30 Control Register - Read/Write @ 'C30 Address 0x0080 0000 ............................... 27
3.6.1 SRST - Bit 0 - Active on Low-to-High Edge ................................................................ 27
Figure 3-1: Reset Circuitry Schematic Diagram........................................................... 27
Table 3-3: ‘C30 Control Register - ‘C30 Address 0x0080 0000 ................................... 27
3.6.2 IACK1, IACK2and IACK3................................................................................................ 28
3.6.3 VMEINT - Bit 4 - Active HIGH ........................................................................................ 28
Figure 3-2: Interrupt Generator Circuitry ..................................................................... 28
3.6.4 TRSEL0 through TRSEL3 (Transfer Select Bits) - Bits 5, 6, 8, and 9 .......................... 28
3.6.4.1 Longword (32-bit) Memory Cycle ............................................................... 29
Table 3-4: Transfer Select (TRSEL) Bit Functions....................................................... 29
3.6.4.2 Word (16-bit) Memory Cycle (Double Cycle) ........................................... 30
3.6.4.3 Word (16-bit) Memory Cycle (Single Cycle) ............................................. 30
3.6.4.4 Byte (8-bit) Memory Cycle (Single Cycle) .................................................. 30
3.6.4.5 IACK Cycle ...................................................................................................... 30
3.6.5 LOCK - Bit D7 - Active HIGH .......................................................................................... 30
3.7 Interrupt Status Register - 'C30 Address 0x0080 0800................................................................... 31
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Pentek Model 4283 Operating Manual Page 5
Page
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Rev.: G.1
3.8 VMEbus Address Modifier Register -'C30 Address 0x0080 0001 (Write Only)......................... 31
Table 3-5: Interrupt Status Register -’C30 Address 0x0080 0800................................................31
Table 3-6: VMEbus Address Modifier Register ............................................................................31
3.9 Page Address Register - 'C30 Address 0x0080 0002 (Write Only).............................................. 32
Table 3-7: Address Modifier Codes .................................................................................................32
Table 3-8: Page Address Register .....................................................................................................32
3.10 VMEbus IACK Address Register - 'C30 Address 0x0080 0003 (Write Only) ............................ 33
3.11 MIX Expansion Bus Address Region - 'C30 Address 0x0080 4000 thru 0x0080 5FFF .............. 33
Table 3-9: VMEbus IACK Address Register..................................................................................33
3.12 'C30 Internal RAM - 'C30 Address 0x0080 9800 through 0x0080 9FFF....................................... 34
3.13 VMEbus IACK Cycle Address - 'C30 Address 0x0080 A000 through 0x008F FFFF.................. 34
3.14 VMEbus Bus Master Access - 'C30 Address 0x00C0 0000 through 0x00FF FFFF ..................... 34
3.15 'C30 Internal Memory Mapped Registers - 'C30 Address 0x0080 8000 thru 0x0080 9FFF...... 34
Table 3-10: ‘C30 Internal Ram Address Map .................................................................................34
Table 3-11: ‘C30 Internal Memory Mapped Registers .................................................................34
Chapter 4: VMEbus Memory Map
4.1 Introduction.......................................................................................................................................... 35
4.2 VMEbus Addresses.............................................................................................................................. 35
4.2.1 Address Modifier Codes ...................................................................................................35
Table 4-1: Address Modifier Codes ................................................................................ 35
4.3 VMEbus Memory Map ....................................................................................................................... 36
4.4 Addressing the DRAM - VMEbus Access........................................................................................ 36
Table 4-2: VMEbus Memory Map....................................................................................................36
4.4.1 A32 DRAM Access ..............................................................................................................37
Figure 4-1: Base Address Switches .................................................................................37
4.4.1.1 A32 DRAM Access - 8 MByte Option .........................................................38
4.4.1.2 A32 DRAM Access - 4MByte Option .........................................................38
4.4.1.3 A32 DRAM Access - 1 MByte Option .........................................................39
Figure 4-2: Base Address Switches (A32) ..................................................39
4.4.2 A24 DRAM Access ..............................................................................................................40
Figure 4-3: A24 Base Address Switch.............................................................................40
4.4.2.1 A24 DRAM Access - 8 MByte Option .........................................................40
4.4.2.2 A24 DRAM Access - 4 MByte Option .........................................................41
4.4.2.3 A24 DRAM Access - 1 MByte Option .........................................................41
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Page 6 Pentek Model 4283 Operating Manual
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Rev.: G.1
4.5 Host Control and IACK Vector Registers ....................................................................................... 42
4.5.1 Host Control Register ........................................................................................................ 42
4.5.1.1 HOST INT - Bit 1 ............................................................................................ 42
Table 4-3: Host Control Register................................................................. 42
4.5.1.2 HOSTRST - Bit 0 ............................................................................................. 43
Figure 4-5: HOSTRST Diagram .................................................................. 43
4.5.2 IACK Vector Register ........................................................................................................ 43
Table 4-4: IACK Vector Register - VMEbus Address A16 Base............................... 43
Chapter 5: MIX Expansion Bus
5.1 Introduction ......................................................................................................................................... 45
5.2 MIX Baseboard - Model 4283 ............................................................................................................ 45
5.3 Expansion Modules (MIX modules) ................................................................................................ 45
5.4 MIX Bus Connector Signals............................................................................................................... 46
Table 5-1:MIX Bus Signals ................................................................................................................ 46
5.5 MIX Module Interface Timing .......................................................................................................... 49
Figure 5-1: MIX Module Interface Timing Diagram.................................................................... 49
Table 5-2: Module Interface Timing .............................................................................................. 49
5.6 Addressing the MIX Expansion Modules...................................................................................... 50
Table 5-3: Page Address Register..................................................................................................... 50
5.7 Servicing Interrupts for MIX Modules ............................................................................................ 51
Figure 5-2: MIX Interrupts to ‘C30................................................................................................... 51
Chapter 6: Interfaces
6.1 Auxiliary Port Connector ................................................................................................................... 53
Figure 6-1: Auxiliary Port Connector............................................................................................... 53
Table 6-1: Auxiliary Port Connector................................................................................................ 53
6.2 XDS Emulator Connector .................................................................................................................. 54
Figure 6-2: XDS Connector Pin-out ................................................................................................. 54
6.3 Reset Switch ......................................................................................................................................... 54
6.4 XF0 LED ................................................................................................................................................ 54
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Pentek Model 4283 Operating Manual Page 7
Page
Table of Contents
Rev.: G.1
Chapter 7: Operating Procedures
7.1 Introduction.......................................................................................................................................... 55
7.2 Handling Interrupts............................................................................................................................ 55
Table 7-1: Reset and Interrupt Vectors - TMS320C30..................................................................55
7.2.1 Interrupt Vectors ................................................................................................................56
7.2.2 Delayed Branch Table .......................................................................................................56
7.2.3 Reset Vector .........................................................................................................................57
7.3 Starting Program Execution............................................................................................................... 57
7.4 Reset Operation ................................................................................................................................... 58
Figure 7-1: Reset Circuit Schematic .................................................................................................58
7.5 VMEbus Interrupter Operation ........................................................................................................ 59
Figure 7-2: Interrupt Generator Circuitry.......................................................................................60
Table 7-2: IRQ and IACK Vector Address Jumpers.....................................................................60
7.6 VMEbus Interrupt Handler Operation............................................................................................ 61
7.7 VMEbus Requester (Bus Master) Operation................................................................................... 62
7.8 VMEbus Arbiter Operation................................................................................................................ 65
7.9 Bus Grant Bypass................................................................................................................................. 65
7.10 Writing Programming Code to the EPROM................................................................................... 65
Table 7-3: Bus Grant Bypass Jumpers .............................................................................................65
Appendix A: Programming Example
A.1 MIX Module Interrupt Service Routine......................................................................................... A-1
Appendix B: Model 4283 Bootcode
B.1 General Information.......................................................................................................................... B-1
asm.bat................................................................................................................................ code page - 1
prom30.cmd (Linker Command File.............................................................................code page - 2
prom30.asm (TMS320C30)............................................................................................... code page - 3
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Page 8 Pentek Model 4283 Operating Manual
Page
Table of Contents
Rev.: G.1
This page is intentionally blank
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Pentek Model 4283 Operating Manual Page 9
Rev.: G.1
Chapter 1: Overview
1.1 Introduction
The Model 4283 Processor Board for VMEbus is based on the Texas Instruments
TMS320C30 Floating Point Digital Signal Processor. It features the 32 MFlop TMS320C30
DSP chip, up to 8MBytes of dual-ported DRAM, 256 kBytes of high-speed SRAM, and
128 kByte of EPROM. An expansion connector utilizing the MIX bus supports a growing
family of digital and analog I/O modules and co-processor expansion modules.
Since the Model 4283 may function as a VMEbus master and/or system controller, the
TMS320C30 may access VMEbus resources simply by reading or writing to certain
portions of its memory map. When installed in Slot 1, the Model 4283 can drive the
system clock and reset signals and function as the bus arbiter. The DRAM on the Model
4283 is available as a VMEbus memory slave relocatable on 1, 4, or 8 Mbyte address
boundaries.
This manual will describe the installation and operation of the Model 4283 in several
typical VMEbus environments.
1.2 System Configuration
The Model 4283 can be tailored to many different types of systems. Here are a few of the
typical application environments:
Stand-alone The Model 4283 can act as the main executive processor in the
Processor system. In this case the unit may contain executable code stored in
EPROM and boot directly. Acting as a VMEbus master, it can access other
devices on the VMEbus.
DSP & Data When combined with the data acquisition, digital and analog I/O
Acquisition and co-processor MIX expansion modules, the Model 4283 can
Sub-System perform complete DSP, control, and communications functions. It
can participate in a larger multi-master VMEbus system as a
high-powered node.
Application With a VMEbus host operating system in place, such as MS-DOS,
Accelerator SUN UNIX, and other UNIX systems with C language support, the Model
4283 can act as an host application accelerator and as a pre-processor for
the data acquisition expansion modules.
1.3 Software Development Support
No DSP hardware product offering is complete without a full complement of
development software. Software products that support the Model 4283 are described on
the next page.
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