Pentek 4200A User manual

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Pentek Models 4200A and 4201A Operating Manual Page 1
Rev.: A.2
Pentek, Inc.
One Park Way
Upper Saddle River, NJ 074 8
(201) 818- 900
Copyright © 1993 - 2003
Manual Part No: 800.42000 Rev: A.2 - March 12, 2003
OPERATING MANUAL
MODELS 4200A and 4201A
MIX Baseboard for VMEbus Systems
Master/Sla e Interface
VSB Master Interface (Model 4200A)
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Page 2 Pentek Models 4200A and 4201A Operating Manual
Rev.: A.2
Pentek Model 4200/01(A) Operating Manual
Revision History
Date Rev Appli able Serial #'s Comments
06/1 /93 Preliminary 9308006 - Forward Initial product release
04/22/94 A 9416001 - Forward Complete re-write. Expanded and revised.
06/10/94 A.1 9416001 - Forward Added Section 3.2.6 (VIC/VAC register access
from 68030), and added these address ranges to
68030 Address Map (Table 3-6). Added info on
re-mapping Interrupt Vectors (Table 3-11) to
Section 3.7.1.1. Changed number of table
already in this section from 3-9 to 3-10.
Clarify the difference between the three Host
Monitor commands to run downloaded code in
Section 2.4.14. Corrected MIX Flag Register
address in Figs. 2-9 and 2-10, and in Tables 3-
6, 3-8 and 3-9. Corrected grammatical error in
Section 3.7.1.2. Added new Appendix (B) about
Distribution Disk. Renamed previous Appen-
dices B and C as C and D.
03/12/03 A.2 9416001 - Forward Minimal update for 4200/01A.
Printed in the USA. All rights reserved. Contents of this publication may not be reproduced in any form without written permission.
WARRANTY
Pentek warrants that all products manufactured by Pentek conform to published Pentek specifications and are
free from defects in materials and workmanship for a period of one year from the date of delivery when used
under normal operating conditions and within the service conditions for which they were furnished.
The obligation of Pentek arising from a warranty claim shall be limited to repairing or at its option, replacing
without charge, any product which in Pentek’s sole opinion proves to be defective within the scope of the
warranty.
Pentek must be notified in writing of the defect or nonconformity within the warranty period and the affected
product returned to Pentek within thirty days after discovery of such defect or nonconformity.
Buyer shall prepay shipping charges, taxes, duties and insurance for products returned to Pentek for war-
ranty service. Pentek shall pay for the return of products to buyer except for products returned from another
country.
Pentek shall have no responsibility for any defect or damage caused by improper installation, unauthorized
modification, misuse, neglect, inadequate maintenance, accident or for any product which has been repaired
or altered by anyone other than Pentek or its authorized representatives.
The warranty described above is buyer’s sole and exclusive remedy and no other warranty, whether written
or oral, is expressed or implied. Pentek specifically disclaims fitness for a particular purpose. Under no
circumstances shall Pentek be liable for any direct, indirect, special, incidental or consequential damages,
expenses, losses or delays (including loss of profits) based on contract, tort, or any other legal theory.
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Pentek Models 4200A and 4201A Operating Manual Page 3
Rev.: A.2
Table of Contents
Page
Chapter 1 - General Information
1.1 Introduction.......................................................................................................................... 7
1.2 Features ................................................................................................................................. 7
1.2.1 VMEbus and VSB Interfaces .......................................................................... 7
1.2.1.1 System Controller ......................................................................... 7
1.2.1.2 VMEbus Master Cycles ............................................................... 8
1.2.1.3 VMEbus Slave Cycles .................................................................. 8
1.2.1.4 Block Transfers ............................................................................. 9
1.2.1. Interrupt Generation.................................................................... 9
1.2.1.6 Interrupt Handling ...................................................................... 9
1.2.1.7 Local Bus Address Decoder ........................................................ 9
1.2.2 68030 Processor ................................................................................................ 9
1.2.3 MIX Bus Interface .......................................................................................... 10
1.2.4 Memory Resources ........................................................................................ 11
1.2.4.1 Static RAM .................................................................................. 11
1.2.4.2 Flash EEPROM ........................................................................... 11
1.2. Dual Serial I/O ............................................................................................... 11
1.3 Block Diagram.................................................................................................................... 12
1.4 Specifications...................................................................................................................... 12
Chapter 2: Installation, Connections and Setup
2.1 Inspection ........................................................................................................................... 17
2.2 Jumper Settings .................................................................................................................. 17
2.2.1 VMEbus Slot 1 System Controller Jumper ................................................. 17
2.2.2 VMEbus Slave Base Address Jumpers ........................................................ 20
2.2.4 Flash EEPROM Write Protect Jumpers....................................................... 21
2.2.3 VSB System Arbiter Jumpers ....................................................................... 21
2.2. Serial Port Connectivity Jumpers ................................................................ 22
2.3 The Model 4200/01 Front Panel ...................................................................................... 23
2.3.1 The Reset Switch ............................................................................................ 23
2.3.2 The Interrupt Switch ..................................................................................... 24
2.3.2.1 Restoring Factory Defaults with the Interrupt and Reset Switches .. 24
2.3.3 The LED Indicator ......................................................................................... 24
2.3.4 The External Port Header ............................................................................. 24
2.3.4.1 Port Receive & Transmit Signals.............................................. 2
2.3.4.2 External Interrupt Signal........................................................... 2
2.3.4.3 Reset Signals ............................................................................... 2
2.4 The 4200/01 Monitor Program ........................................................................................ 26
2.4.1 Connecting to the Serial Port ....................................................................... 26
2.4.2 Default Communication Parameters .......................................................... 26
2.4.3 Booting the Monitor Program ...................................................................... 27
2.4.4 Changing the VME Slave Base Address Table .......................................... 29
2.4. Changing the 68030’s Memory Map ........................................................... 32
2.4.6 VME Attributes .............................................................................................. 3
2.4.7 Examining and Modifying 4200/01 Memory Contents ........................... 37
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Page 4 Pentek Models 4200A and 4201A Operating Manual
Rev.: A.2
Table of Contents (continued)
Page
Chapter 2: Installation, Connections and Setup (continued)
2.4 The 4200/01 Monitor Program (continued)
2.4.8 Loading Programs to the 4200/01 with the Monitor ............................... 38
2.4.8.1 Loading Programs to the 4200/01’s SRAM ............................ 38
2.4.8.2 Loading Programs to the User/Configuration Flash EEPROM ... 39
2.4.8.3 Copying EEPROM Code into SRAM ...................................... 40
2.4.9 Starting and Stopping Programs from the Monitor ................................. 41
2.4.10 Upgrading 4200/01 Firmware ..................................................................... 41
2.4.11 Selecting Interrupt Settings with the Monitor ........................................... 44
2.4.12 Automatically Executing User Code .......................................................... 44
2.4.13 Issuing Other Commands with the Monitor ............................................. 44
2.4.14 VMEbus Access to Monitor Features .......................................................... 44
2.4.14.1 Host Interface Program - 4200.C ............................................. 46
2.4.14.2 Host Interface Program Interrupt Access ............................... 48
2.4.14.3 Modifying A32 or A24 Base Addresses from VME A16 Space .... 49
2.4.14.4 Changing the VSB Access Region Size from the VMEbus ... 0
2. Removing and Installing the Model 4200/01 Front Panel ......................................... 1
2. .1 Tools Required ............................................................................................... 1
2. .2 Removing the 4200/01 Mezzanine Board .................................................. 1
2. .3 Removing or Installing the Front Panel Board Header ........................... 2
2. .4 Removing the Front Panel ............................................................................ 3
2. . Installing the Front Panel ............................................................................. 3
2. .6 Replacing the Mezzanine Board .................................................................. 4
2.6 Installing MIX Expansion Modules on the 4200/01 .................................................... 4
Chapter 3: peration
3.1 Operating Theory ..............................................................................................................
3.1.1 The VME Interface Controller (VIC068A) ..................................................
3.1.2 The VME Address Controller (VAC068A)................................................. 8
3.1.3 The 68030......................................................................................................... 8
3.1.4 SRAM Allocation ........................................................................................... 9
3.1. The MIX Bus Interface ................................................................................... 9
3.1.6 4200/01 Data Cycles ...................................................................................... 60
3.1.7 Local Bus Arbitration .................................................................................... 61
3.2 Model 4200/01 Memory Maps ........................................................................................ 61
3.2.1 VME Slave Memory Map ............................................................................. 61
3.2.2 68030 Memory Map ....................................................................................... 64
3.2.3 The MIX Control Register ............................................................................. 6
3.2.4 The MIX Flag Register ................................................................................... 67
3.2. The MIX Status Register ............................................................................... 69
3.2.6 Access to the VIC and VAC Registers from the 68030 ............................. 70
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Pentek Models 4200A and 4201A Operating Manual Page 5
Rev.: A.2
Table of Contents (continued)
Page
Chapter 3: peration (continued)
3.3 Modifying the Contents of the Flash EEPROMs .......................................................... 71
3.3.1 Saving Changes to the Address Tables ...................................................... 71
3.3.2 Writing Application Code into the Flash EEPROMs ............................... 74
3.4 Slave Operation ................................................................................................................. 74
3.4.1 The 4200/01 as a VMEbus Slave.................................................................. 7
3.4.2 The 4200/01 as a MIX Bus Slave.................................................................. 7
3. Master Operation............................................................................................................... 76
3. .1 The 4200/01 as a VMEbus Master ............................................................... 76
3. .2 The 4200/01 as a MIX Bus Master ............................................................... 77
3. .2.1 The 4200/01’s MIX Interface as a VMEbus Master ............... 77
3. .2.2 The 4200’s MIX Interface as a VSBus Master ......................... 77
3. .3 The 4200 as a VSBus Master ......................................................................... 78
3. .4 DMA and the Model 4200/01 ...................................................................... 78
3.6 System Controller Operation ........................................................................................... 79
3.6.1 The 4200/01 as a VMEbus System Controller ........................................... 79
3.6.2 The 4200 as a VSBus System Arbiter ........................................................... 79
3.7 Generating Interrupts with the 4200/01 ........................................................................ 79
3.7.1 The 4200/01 as a VMEbus Interrupter ....................................................... 79
3.7.1.1 Interrupting the VMEbus from a MIX Module ..................... 80
3.7.1.2 Interrupting the VMEbus from a 68030 Program.................. 81
3.7.2 The 4200/01 as a MIX Bus Interrupter ....................................................... 81
3.7.2.1 Interrupting the MIX Bus from the VMEbus ......................... 82
3.7.2.2 Interrupting MIX Processor Modules from 68030 Programs .. 82
3.7.2.3 Local Conditions That Will Generate MIX Interrupts .......... 82
3.8 Handling Interrupts to the 4200/01 ............................................................................... 84
3.8.1 The 4200/01 as a VMEbus Interrupt Handler ........................................... 84
3.8.1.1 VMEbus Interrupts to the 68030 .............................................. 84
3.8.1.2 VMEbus Interrupts to the MIX Bus ......................................... 84
3.8.2 The 4200/01 as a MIX Bus Interrupt Handler ........................................... 84
3.8.2.1 MIX Bus Interrupts to the 68030 .............................................. 84
3.8.2.2 MIX Bus Interrupts to the VMEbus ......................................... 8
3.8.3 The 4200 as a VSBus Interrupt Handler ..................................................... 8
3.8.3.1 VSBus Interrupts to the 68030 .................................................. 8
3.8.3.2 VSBus Interrupts to the MIX Bus ............................................. 8
3.9 Additional Features of the Model 4200/01 ................................................................... 8
3.9.1 Using the VAC’s Programmable Timer ..................................................... 8
3.9.2 Using the VAC’s UART ............................................................................... 86
3.9.3 Split Bus Operation........................................................................................ 87
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Page 6 Pentek Models 4200A and 4201A Operating Manual
Rev.: A.2
Table of Contents (continued)
Page
Appendix A: Cypress Semiconductor VIC068A/VAC068A Register Maps and Definitions
A.1 VIC068A Register Map and Definitions ..................................................................... A - 3
A.2 VAC068A Register Map and Definitions .................................................................. A-3
Appendix B: The 4200/01 Distribution Diskette
B.1 Introduction..................................................................................................................... B - 1
B.2 Contents of 4200.zip ....................................................................................................... B -1
B.3 Utility Programs for the Model 4200/01..................................................................... B -
Appendix C: MIX Tutorial
C.0 Introduction..................................................................................................................... C - 1
C.1 MIX Baseboards .............................................................................................................. C-1
C.2 MIX Modules (Expansion Modules) ........................................................................... C - 2
C.3 MIX Baseboard Connector ............................................................................................ C- 4
C.4 MIX Stiffener ................................................................................................................... C - 4
C. Flathead Screws ..............................................................................................................C-4
C.6 First Slot (Nested) Module Installation ....................................................................... C -
C.7 Installing Ejector Handles on the MIX Module Front Panel.................................... C- 6
C.8 MIX Stacking Connector ............................................................................................... C - 7
C.9 MIX Jackscrews ...............................................................................................................C-7
C.10 MIX Spacer Board ........................................................................................................... C-7
C.11 Second Slot Module Installation .................................................................................. C - 8
C.12 Adding a Second Expansion Module .......................................................................... C- 8
C.13 Adding a Third Expansion Module............................................................................. C- 9
C.14 Installing the Assembly into the VMEbus Card Cage ............................................ C-10
C.1 A Glossary of MIX Terms ............................................................................................ C-11
Appendix D: perating Note - A24 Slave Addressing
D.1 Introduction..................................................................................................................... D - 1
D.2 A24 Address Decoding and the VAC068A ................................................................ D - 1
D.3 Case 1: No P2 Connectors ............................................................................................ D - 1
D.4 Case 2: The Bus Master Does Not Drive the P2 Address Lines.............................. D - 2
D. Case 3: The Upper Address Lines are Driven by the Bus Master .......................... D - 2
D.6 Flash EEPROM Address Conflict ................................................................................ D - 2
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Pentek Models 4200A and 4201A Operating Manual Page 7
Rev.: A.2
Chapter 1 - General Information
1.1 Introdu tion
The Pentek Models 4200A and 4201A convert Pentek’s full complement of MIX modules
into standard 6U single-slot VMEbus boards with full bus master capability. The
Model 4200A features three bus interfaces; VME, VSB (VME Subsystem Bus) and MIX.
Master and slave operations are supported by both the VME and MIX interfaces, while
the VSB interface offers master operation only. The Model 4201A is the same as the
Model 4200A, but without the VSB interface.
The MIX Bus is a local daughter card bus that accepts one, two or three MIX daughter
card modules in a stacking arrangement. Each module requires one slot in the VME
card cage.
1.2 Features
The following subsections summarize and briefly describe the features of the Pentek
Model 4200A and Model 4201A VME/MIX Baseboards.
1.2.1 VMEbus and VSB Interfa es
The VMEbus interface is implemented with the Cypress Semiconductor
VIC068A VMEbus Interface Controller (VIC) and the VAC068A VMEbus
Address Controller (VAC) chip set, providing well-defined and fully-
characterized VMEbus signal timing. These devices fully meet the require-
ments of the IEEE VMEbus Specification 1014 Rev C.1.
The VIC/VAC set is designed to be highly compatible with the 68030, which
serves as the initialization and control resource for these devices. The com-
bination of these three elements (68030/VIC/VAC) represents an extremely
popular and standard configuration, found on hundreds of VMEbus prod-
ucts, and available from dozens of manufacturers.
The VME Subsystem Bus (VSB) is a secondary bus utilizing the outer rows of
pins on the VME P2 connector, which are unused in the standard VMEbus
implementation. The Model 4200A operates as a VSB master and interrupt
handler, via the VSB1400A/B chip set from PLX. There is no VSB interface
on the Model 4201A.
1.2.1.1 System Controller
Because of its general purpose architecture, the Model 4200/01A
can serve as a complete VMEbus system controller in the VMEbus
chassis.
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Page 8 Pentek Models 4200A and 4201A Operating Manual
Rev.: A.2
1.2 Features (continued)
1.2.1 VMEbus and VSB Interfa es (continued)
1.2.1.1 System Controller (continued)
Within the 4200/01A, the VIC supports priority and round robin
arbitration schemes; drives the IACK daisy-chain and the Bus
Grant I/O daisy-chain; drives the SYSCLK and SYSRESET lines;
and provides VMEbus arbitration and transfer timeout timers.
1.2.1.2 VMEbus Master Cycles
All phases of VMEbus mastership are supported when access to
the VMEbus is requested by the 68030, the VIC/VAC DMA
controller, or MIX Bus master devices. Additional bus master
features are: data transfers in A32, A24 or A16 address space,
utilizing D32, D16, or D08 data widths; full address modifier
(AM) code generation; bus requests on all four levels; Release on
Request, Release When Done, Release on Clear, Release under
RMC, and Bus Capture and Hold requester capabilities; Indivis-
ible Read-Modify-Write and Multiple-Address cycles; Deadlock
and self-access handling provisions; and Master Write-Posting
(latches data from the local bus and releases it to be free from
VMEbus arbitration delays).
1.2.1.3 VMEbus Slave Cycles
Slave access from the VMEbus is supported in many different
configurations, providing memory mapping of each MIX module,
the local bus memory resources and the VSB. Slave support
features include: data transfers in A32, A24 or A16 address space,
utilizing D32, D16, or D08 data widths; full address modifier
(AM) code handling; Block Transfers, programmable for both
accelerated and non-accelerated modes; programmable Physical
Address Strobe and data acquisition delays; and Slave Write-
Posting (latches data from the VMEbus and releases it to be free
from local bus arbitration delays).
Two separate slave base address registers within the VAC allow
the Model 4200A to respond to two different slave addresses. The
size of data words is separately programmable for the A16 and
A24 address spaces, i. e., it is possible for one slave address to be
programmed for A24/D16 access, and the other for A16/D32.
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Pentek Models 4200A and 4201A Operating Manual Page 9
Rev.: A.2
1.2 Features (continued)
1.2.1 VMEbus and VSB Interfa es (continued)
1.2.1.4 Block Transfers
Both master and slave block transfers are supported with ex-
tended addressing (32-bit incrementing address) provided by the
VAC. Every time a 2 6-byte boundary is crossed, a new Address
Strobe is asserted to maintain VMEbus compliance. Other Block
Transfer-related features include Master block transfers with
local DMA, MOVEM-type block transfers, and Slave transfers in
accelerated or non-accelerated mode.
1.2.1. Interrupt Generation
All seven interrupts levels of the VMEbus can be generated and a
user defined interrupt vector is supported for each level. Inter-
rupts can also be generated to the 68030 for various VMEbus
transfer error conditions including ACFAIL, SYSFAIL, BERR and
bus arbitration timeout.
1.2.1.6 Interrupt Handling
The VIC handles interrupts from the following sources: all seven
levels of the VMEbus; all three MIX modules on the MIX bus; the
VSB interrupt; four interrupts from the two VAC serial ports;
status and control interrupts from the VAC; and seven interrupts
from the 68030. Also supported are edge/level control, polarity
control, and user defined local IPL (Interrupt Priority Level).
1.2.1.7 Local Bus Address Decoder
The VAC decodes nearly all of the address space within the
Model 4200/01A. This provides a very flexible allocation of
memory within the onboard SRAM, Flash EEPROM memories,
the VSB interface, and the MIX interface.
1.2.2 68030 Pro essor
The Model 4200A and Model 4201A feature an onboard 40 MHz 68EC030
processor that acts as the interface controller and DMA engine. A 1 MB
Static RAM (optionally 4 MB) and two 2 6 kB EPROMs service the 68030 via
the local bus. The 68030 has full memory access to the VMEbus, the VSB and
the MIX bus, with 32-bit data and 32-bit address support for all transfers.
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