Pentek 4200A User manual

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Pentek Models 4200A and 4201A Operating Manual Page 1
Rev.: A.2
Pentek, Inc.
One Park Way
Upper Saddle River, NJ 074 8
(201) 818- 900
Copyright © 1993 - 2003
Manual Part No: 800.42000 Rev: A.2 - March 12, 2003
OPERATING MANUAL
MODELS 4200A and 4201A
MIX Baseboard for VMEbus Systems
Master/Sla e Interface
VSB Master Interface (Model 4200A)
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Page 2 Pentek Models 4200A and 4201A Operating Manual
Rev.: A.2
Pentek Model 4200/01(A) Operating Manual
Revision History
Date Rev Appli able Serial #'s Comments
06/1 /93 Preliminary 9308006 - Forward Initial product release
04/22/94 A 9416001 - Forward Complete re-write. Expanded and revised.
06/10/94 A.1 9416001 - Forward Added Section 3.2.6 (VIC/VAC register access
from 68030), and added these address ranges to
68030 Address Map (Table 3-6). Added info on
re-mapping Interrupt Vectors (Table 3-11) to
Section 3.7.1.1. Changed number of table
already in this section from 3-9 to 3-10.
Clarify the difference between the three Host
Monitor commands to run downloaded code in
Section 2.4.14. Corrected MIX Flag Register
address in Figs. 2-9 and 2-10, and in Tables 3-
6, 3-8 and 3-9. Corrected grammatical error in
Section 3.7.1.2. Added new Appendix (B) about
Distribution Disk. Renamed previous Appen-
dices B and C as C and D.
03/12/03 A.2 9416001 - Forward Minimal update for 4200/01A.
Printed in the USA. All rights reserved. Contents of this publication may not be reproduced in any form without written permission.
WARRANTY
Pentek warrants that all products manufactured by Pentek conform to published Pentek specifications and are
free from defects in materials and workmanship for a period of one year from the date of delivery when used
under normal operating conditions and within the service conditions for which they were furnished.
The obligation of Pentek arising from a warranty claim shall be limited to repairing or at its option, replacing
without charge, any product which in Pentek’s sole opinion proves to be defective within the scope of the
warranty.
Pentek must be notified in writing of the defect or nonconformity within the warranty period and the affected
product returned to Pentek within thirty days after discovery of such defect or nonconformity.
Buyer shall prepay shipping charges, taxes, duties and insurance for products returned to Pentek for war-
ranty service. Pentek shall pay for the return of products to buyer except for products returned from another
country.
Pentek shall have no responsibility for any defect or damage caused by improper installation, unauthorized
modification, misuse, neglect, inadequate maintenance, accident or for any product which has been repaired
or altered by anyone other than Pentek or its authorized representatives.
The warranty described above is buyer’s sole and exclusive remedy and no other warranty, whether written
or oral, is expressed or implied. Pentek specifically disclaims fitness for a particular purpose. Under no
circumstances shall Pentek be liable for any direct, indirect, special, incidental or consequential damages,
expenses, losses or delays (including loss of profits) based on contract, tort, or any other legal theory.
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Pentek Models 4200A and 4201A Operating Manual Page 3
Rev.: A.2
Table of Contents
Page
Chapter 1 - General Information
1.1 Introduction.......................................................................................................................... 7
1.2 Features ................................................................................................................................. 7
1.2.1 VMEbus and VSB Interfaces .......................................................................... 7
1.2.1.1 System Controller ......................................................................... 7
1.2.1.2 VMEbus Master Cycles ............................................................... 8
1.2.1.3 VMEbus Slave Cycles .................................................................. 8
1.2.1.4 Block Transfers ............................................................................. 9
1.2.1. Interrupt Generation.................................................................... 9
1.2.1.6 Interrupt Handling ...................................................................... 9
1.2.1.7 Local Bus Address Decoder ........................................................ 9
1.2.2 68030 Processor ................................................................................................ 9
1.2.3 MIX Bus Interface .......................................................................................... 10
1.2.4 Memory Resources ........................................................................................ 11
1.2.4.1 Static RAM .................................................................................. 11
1.2.4.2 Flash EEPROM ........................................................................... 11
1.2. Dual Serial I/O ............................................................................................... 11
1.3 Block Diagram.................................................................................................................... 12
1.4 Specifications...................................................................................................................... 12
Chapter 2: Installation, Connections and Setup
2.1 Inspection ........................................................................................................................... 17
2.2 Jumper Settings .................................................................................................................. 17
2.2.1 VMEbus Slot 1 System Controller Jumper ................................................. 17
2.2.2 VMEbus Slave Base Address Jumpers ........................................................ 20
2.2.4 Flash EEPROM Write Protect Jumpers....................................................... 21
2.2.3 VSB System Arbiter Jumpers ....................................................................... 21
2.2. Serial Port Connectivity Jumpers ................................................................ 22
2.3 The Model 4200/01 Front Panel ...................................................................................... 23
2.3.1 The Reset Switch ............................................................................................ 23
2.3.2 The Interrupt Switch ..................................................................................... 24
2.3.2.1 Restoring Factory Defaults with the Interrupt and Reset Switches .. 24
2.3.3 The LED Indicator ......................................................................................... 24
2.3.4 The External Port Header ............................................................................. 24
2.3.4.1 Port Receive & Transmit Signals.............................................. 2
2.3.4.2 External Interrupt Signal........................................................... 2
2.3.4.3 Reset Signals ............................................................................... 2
2.4 The 4200/01 Monitor Program ........................................................................................ 26
2.4.1 Connecting to the Serial Port ....................................................................... 26
2.4.2 Default Communication Parameters .......................................................... 26
2.4.3 Booting the Monitor Program ...................................................................... 27
2.4.4 Changing the VME Slave Base Address Table .......................................... 29
2.4. Changing the 68030’s Memory Map ........................................................... 32
2.4.6 VME Attributes .............................................................................................. 3
2.4.7 Examining and Modifying 4200/01 Memory Contents ........................... 37
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Page 4 Pentek Models 4200A and 4201A Operating Manual
Rev.: A.2
Table of Contents (continued)
Page
Chapter 2: Installation, Connections and Setup (continued)
2.4 The 4200/01 Monitor Program (continued)
2.4.8 Loading Programs to the 4200/01 with the Monitor ............................... 38
2.4.8.1 Loading Programs to the 4200/01’s SRAM ............................ 38
2.4.8.2 Loading Programs to the User/Configuration Flash EEPROM ... 39
2.4.8.3 Copying EEPROM Code into SRAM ...................................... 40
2.4.9 Starting and Stopping Programs from the Monitor ................................. 41
2.4.10 Upgrading 4200/01 Firmware ..................................................................... 41
2.4.11 Selecting Interrupt Settings with the Monitor ........................................... 44
2.4.12 Automatically Executing User Code .......................................................... 44
2.4.13 Issuing Other Commands with the Monitor ............................................. 44
2.4.14 VMEbus Access to Monitor Features .......................................................... 44
2.4.14.1 Host Interface Program - 4200.C ............................................. 46
2.4.14.2 Host Interface Program Interrupt Access ............................... 48
2.4.14.3 Modifying A32 or A24 Base Addresses from VME A16 Space .... 49
2.4.14.4 Changing the VSB Access Region Size from the VMEbus ... 0
2. Removing and Installing the Model 4200/01 Front Panel ......................................... 1
2. .1 Tools Required ............................................................................................... 1
2. .2 Removing the 4200/01 Mezzanine Board .................................................. 1
2. .3 Removing or Installing the Front Panel Board Header ........................... 2
2. .4 Removing the Front Panel ............................................................................ 3
2. . Installing the Front Panel ............................................................................. 3
2. .6 Replacing the Mezzanine Board .................................................................. 4
2.6 Installing MIX Expansion Modules on the 4200/01 .................................................... 4
Chapter 3: peration
3.1 Operating Theory ..............................................................................................................
3.1.1 The VME Interface Controller (VIC068A) ..................................................
3.1.2 The VME Address Controller (VAC068A)................................................. 8
3.1.3 The 68030......................................................................................................... 8
3.1.4 SRAM Allocation ........................................................................................... 9
3.1. The MIX Bus Interface ................................................................................... 9
3.1.6 4200/01 Data Cycles ...................................................................................... 60
3.1.7 Local Bus Arbitration .................................................................................... 61
3.2 Model 4200/01 Memory Maps ........................................................................................ 61
3.2.1 VME Slave Memory Map ............................................................................. 61
3.2.2 68030 Memory Map ....................................................................................... 64
3.2.3 The MIX Control Register ............................................................................. 6
3.2.4 The MIX Flag Register ................................................................................... 67
3.2. The MIX Status Register ............................................................................... 69
3.2.6 Access to the VIC and VAC Registers from the 68030 ............................. 70
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Pentek Models 4200A and 4201A Operating Manual Page 5
Rev.: A.2
Table of Contents (continued)
Page
Chapter 3: peration (continued)
3.3 Modifying the Contents of the Flash EEPROMs .......................................................... 71
3.3.1 Saving Changes to the Address Tables ...................................................... 71
3.3.2 Writing Application Code into the Flash EEPROMs ............................... 74
3.4 Slave Operation ................................................................................................................. 74
3.4.1 The 4200/01 as a VMEbus Slave.................................................................. 7
3.4.2 The 4200/01 as a MIX Bus Slave.................................................................. 7
3. Master Operation............................................................................................................... 76
3. .1 The 4200/01 as a VMEbus Master ............................................................... 76
3. .2 The 4200/01 as a MIX Bus Master ............................................................... 77
3. .2.1 The 4200/01’s MIX Interface as a VMEbus Master ............... 77
3. .2.2 The 4200’s MIX Interface as a VSBus Master ......................... 77
3. .3 The 4200 as a VSBus Master ......................................................................... 78
3. .4 DMA and the Model 4200/01 ...................................................................... 78
3.6 System Controller Operation ........................................................................................... 79
3.6.1 The 4200/01 as a VMEbus System Controller ........................................... 79
3.6.2 The 4200 as a VSBus System Arbiter ........................................................... 79
3.7 Generating Interrupts with the 4200/01 ........................................................................ 79
3.7.1 The 4200/01 as a VMEbus Interrupter ....................................................... 79
3.7.1.1 Interrupting the VMEbus from a MIX Module ..................... 80
3.7.1.2 Interrupting the VMEbus from a 68030 Program.................. 81
3.7.2 The 4200/01 as a MIX Bus Interrupter ....................................................... 81
3.7.2.1 Interrupting the MIX Bus from the VMEbus ......................... 82
3.7.2.2 Interrupting MIX Processor Modules from 68030 Programs .. 82
3.7.2.3 Local Conditions That Will Generate MIX Interrupts .......... 82
3.8 Handling Interrupts to the 4200/01 ............................................................................... 84
3.8.1 The 4200/01 as a VMEbus Interrupt Handler ........................................... 84
3.8.1.1 VMEbus Interrupts to the 68030 .............................................. 84
3.8.1.2 VMEbus Interrupts to the MIX Bus ......................................... 84
3.8.2 The 4200/01 as a MIX Bus Interrupt Handler ........................................... 84
3.8.2.1 MIX Bus Interrupts to the 68030 .............................................. 84
3.8.2.2 MIX Bus Interrupts to the VMEbus ......................................... 8
3.8.3 The 4200 as a VSBus Interrupt Handler ..................................................... 8
3.8.3.1 VSBus Interrupts to the 68030 .................................................. 8
3.8.3.2 VSBus Interrupts to the MIX Bus ............................................. 8
3.9 Additional Features of the Model 4200/01 ................................................................... 8
3.9.1 Using the VAC’s Programmable Timer ..................................................... 8
3.9.2 Using the VAC’s UART ............................................................................... 86
3.9.3 Split Bus Operation........................................................................................ 87
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Page 6 Pentek Models 4200A and 4201A Operating Manual
Rev.: A.2
Table of Contents (continued)
Page
Appendix A: Cypress Semiconductor VIC068A/VAC068A Register Maps and Definitions
A.1 VIC068A Register Map and Definitions ..................................................................... A - 3
A.2 VAC068A Register Map and Definitions .................................................................. A-3
Appendix B: The 4200/01 Distribution Diskette
B.1 Introduction..................................................................................................................... B - 1
B.2 Contents of 4200.zip ....................................................................................................... B -1
B.3 Utility Programs for the Model 4200/01..................................................................... B -
Appendix C: MIX Tutorial
C.0 Introduction..................................................................................................................... C - 1
C.1 MIX Baseboards .............................................................................................................. C-1
C.2 MIX Modules (Expansion Modules) ........................................................................... C - 2
C.3 MIX Baseboard Connector ............................................................................................ C- 4
C.4 MIX Stiffener ................................................................................................................... C - 4
C. Flathead Screws ..............................................................................................................C-4
C.6 First Slot (Nested) Module Installation ....................................................................... C -
C.7 Installing Ejector Handles on the MIX Module Front Panel.................................... C- 6
C.8 MIX Stacking Connector ............................................................................................... C - 7
C.9 MIX Jackscrews ...............................................................................................................C-7
C.10 MIX Spacer Board ........................................................................................................... C-7
C.11 Second Slot Module Installation .................................................................................. C - 8
C.12 Adding a Second Expansion Module .......................................................................... C- 8
C.13 Adding a Third Expansion Module............................................................................. C- 9
C.14 Installing the Assembly into the VMEbus Card Cage ............................................ C-10
C.1 A Glossary of MIX Terms ............................................................................................ C-11
Appendix D: perating Note - A24 Slave Addressing
D.1 Introduction..................................................................................................................... D - 1
D.2 A24 Address Decoding and the VAC068A ................................................................ D - 1
D.3 Case 1: No P2 Connectors ............................................................................................ D - 1
D.4 Case 2: The Bus Master Does Not Drive the P2 Address Lines.............................. D - 2
D. Case 3: The Upper Address Lines are Driven by the Bus Master .......................... D - 2
D.6 Flash EEPROM Address Conflict ................................................................................ D - 2
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Pentek Models 4200A and 4201A Operating Manual Page 7
Rev.: A.2
Chapter 1 - General Information
1.1 Introdu tion
The Pentek Models 4200A and 4201A convert Pentek’s full complement of MIX modules
into standard 6U single-slot VMEbus boards with full bus master capability. The
Model 4200A features three bus interfaces; VME, VSB (VME Subsystem Bus) and MIX.
Master and slave operations are supported by both the VME and MIX interfaces, while
the VSB interface offers master operation only. The Model 4201A is the same as the
Model 4200A, but without the VSB interface.
The MIX Bus is a local daughter card bus that accepts one, two or three MIX daughter
card modules in a stacking arrangement. Each module requires one slot in the VME
card cage.
1.2 Features
The following subsections summarize and briefly describe the features of the Pentek
Model 4200A and Model 4201A VME/MIX Baseboards.
1.2.1 VMEbus and VSB Interfa es
The VMEbus interface is implemented with the Cypress Semiconductor
VIC068A VMEbus Interface Controller (VIC) and the VAC068A VMEbus
Address Controller (VAC) chip set, providing well-defined and fully-
characterized VMEbus signal timing. These devices fully meet the require-
ments of the IEEE VMEbus Specification 1014 Rev C.1.
The VIC/VAC set is designed to be highly compatible with the 68030, which
serves as the initialization and control resource for these devices. The com-
bination of these three elements (68030/VIC/VAC) represents an extremely
popular and standard configuration, found on hundreds of VMEbus prod-
ucts, and available from dozens of manufacturers.
The VME Subsystem Bus (VSB) is a secondary bus utilizing the outer rows of
pins on the VME P2 connector, which are unused in the standard VMEbus
implementation. The Model 4200A operates as a VSB master and interrupt
handler, via the VSB1400A/B chip set from PLX. There is no VSB interface
on the Model 4201A.
1.2.1.1 System Controller
Because of its general purpose architecture, the Model 4200/01A
can serve as a complete VMEbus system controller in the VMEbus
chassis.
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Page 8 Pentek Models 4200A and 4201A Operating Manual
Rev.: A.2
1.2 Features (continued)
1.2.1 VMEbus and VSB Interfa es (continued)
1.2.1.1 System Controller (continued)
Within the 4200/01A, the VIC supports priority and round robin
arbitration schemes; drives the IACK daisy-chain and the Bus
Grant I/O daisy-chain; drives the SYSCLK and SYSRESET lines;
and provides VMEbus arbitration and transfer timeout timers.
1.2.1.2 VMEbus Master Cycles
All phases of VMEbus mastership are supported when access to
the VMEbus is requested by the 68030, the VIC/VAC DMA
controller, or MIX Bus master devices. Additional bus master
features are: data transfers in A32, A24 or A16 address space,
utilizing D32, D16, or D08 data widths; full address modifier
(AM) code generation; bus requests on all four levels; Release on
Request, Release When Done, Release on Clear, Release under
RMC, and Bus Capture and Hold requester capabilities; Indivis-
ible Read-Modify-Write and Multiple-Address cycles; Deadlock
and self-access handling provisions; and Master Write-Posting
(latches data from the local bus and releases it to be free from
VMEbus arbitration delays).
1.2.1.3 VMEbus Slave Cycles
Slave access from the VMEbus is supported in many different
configurations, providing memory mapping of each MIX module,
the local bus memory resources and the VSB. Slave support
features include: data transfers in A32, A24 or A16 address space,
utilizing D32, D16, or D08 data widths; full address modifier
(AM) code handling; Block Transfers, programmable for both
accelerated and non-accelerated modes; programmable Physical
Address Strobe and data acquisition delays; and Slave Write-
Posting (latches data from the VMEbus and releases it to be free
from local bus arbitration delays).
Two separate slave base address registers within the VAC allow
the Model 4200A to respond to two different slave addresses. The
size of data words is separately programmable for the A16 and
A24 address spaces, i. e., it is possible for one slave address to be
programmed for A24/D16 access, and the other for A16/D32.
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Pentek Models 4200A and 4201A Operating Manual Page 9
Rev.: A.2
1.2 Features (continued)
1.2.1 VMEbus and VSB Interfa es (continued)
1.2.1.4 Block Transfers
Both master and slave block transfers are supported with ex-
tended addressing (32-bit incrementing address) provided by the
VAC. Every time a 2 6-byte boundary is crossed, a new Address
Strobe is asserted to maintain VMEbus compliance. Other Block
Transfer-related features include Master block transfers with
local DMA, MOVEM-type block transfers, and Slave transfers in
accelerated or non-accelerated mode.
1.2.1. Interrupt Generation
All seven interrupts levels of the VMEbus can be generated and a
user defined interrupt vector is supported for each level. Inter-
rupts can also be generated to the 68030 for various VMEbus
transfer error conditions including ACFAIL, SYSFAIL, BERR and
bus arbitration timeout.
1.2.1.6 Interrupt Handling
The VIC handles interrupts from the following sources: all seven
levels of the VMEbus; all three MIX modules on the MIX bus; the
VSB interrupt; four interrupts from the two VAC serial ports;
status and control interrupts from the VAC; and seven interrupts
from the 68030. Also supported are edge/level control, polarity
control, and user defined local IPL (Interrupt Priority Level).
1.2.1.7 Local Bus Address Decoder
The VAC decodes nearly all of the address space within the
Model 4200/01A. This provides a very flexible allocation of
memory within the onboard SRAM, Flash EEPROM memories,
the VSB interface, and the MIX interface.
1.2.2 68030 Pro essor
The Model 4200A and Model 4201A feature an onboard 40 MHz 68EC030
processor that acts as the interface controller and DMA engine. A 1 MB
Static RAM (optionally 4 MB) and two 2 6 kB EPROMs service the 68030 via
the local bus. The 68030 has full memory access to the VMEbus, the VSB and
the MIX bus, with 32-bit data and 32-bit address support for all transfers.
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Page 10 Pentek Models 4200A and 4201A Operating Manual
Rev.: A.2
1.2 Features (continued)
1.2.2 68030 Pro essor (continued)
Since the DMA controller within the VIC/VAC chip set can only move data
between the VMEbus and the local bus, data moves between two local bus
resources (e. g., the SRAM and the MIX bus) are handled by the 68030 using
DMA-like routines stored in the User/Configuration EEPROM memory. In
this way, the 68030 acts as a flexible, multi-channel DMA controller. Source
address, destination address, transfer type and block length parameters are
accepted for each DMA channel. Transfers can be initiated by any of the
numerous interrupts processed by the 68030. These include interrupts from
the MIX bus, the VMEbus, the VSB, the serial ports, etc.
1.2.3 MIX Bus Interfa e
This interface provides a bidirectional 32-bit data path between the local bus
and the MIX Bus. Full memory-mapped access to all modules on the MIX
bus is supported from both from the 68030, for DMA transfers, and from the
VMEbus. This allows the MIX modules to appear as VMEbus slave devices.
MIX modules with MIX Bus master capability use the Bus Interface to access
the VMEbus and the VSB with A32 D32 bus master capabilities. For ex-
ample, when combined with the Model 4200A, the Model 42 7 Dual
TMS320C40 Co-Processor MIX module becomes a complete Dual
TMS320C40 Processor VME Master/Slave board, all in a single 6U VME card
cage slot.
The MIX bus can also be used for dedicated high-speed data transfers
between MIX modules. These transfers can be initiated by any MIX module
having MIX bus master capability or by the 68030 acting as a DMA control-
ler. It is even possible to move data between MIX modules by issuing read
and write commands from the VMEbus.
An important feature of the Model 4200/01A is its ability to decouple the
MIX bus from the local bus, allowing each to conduct memory cycles inde-
pendent of the other. Only when access across this interface is required must
one bus arbitrate for the other. With the write-posting support of the VIC/
VAC chip set, transfers between MIX and VME busses are enhanced even
further.
When the MIX and local busses are decoupled, a set of bidirectional registers
is provided in the MIX/local Interface that act like mailbox registers between
the busses. A write from one bus to the transport register occurs without bus
arbitration, and causes a maskable interrupt to the other bus. The other bus
may read this register without arbitrating for the generating bus, and per-
form some appropriate action.
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Pentek Models 4200A and 4201A Operating Manual Page 11
Rev.: A.2
1.2 Features (continued)
1.2.3 MIX Bus Interfa e (continued)
As a MIX Bus Master, the Models 4200A and 4201A are also capable of
handling Interrupts from any expansion modules on the MIX Bus stack.
1.2.4 Memory Resour es
Two different types of memory devices are used in the Model 4200/01A,
Static RAM (SRAM), and Flash Electrically Erasable Programmable ROM
(EEPROM).
1.2.4.1 Static RAM
The local bus serves as the central data path for all transfers
within the unit. A fast 1 MB Static RAM provides zero-wait-
state operation as a stack, and as a general purpose program and
data staging area, for the 68030. The SRAM may optionally be
expanded to 2 MB or 4 MB.
1.2.4.2 Flash EEPROM
There are two 2 6 kB Flash EEPROM memories contained on the
4200/01A. These non-volatile devices can be written to without
removing them from the board. One is used for the dedicated
factory supplied firmware to initialize the board and to support
the VIC/VAC functions.
The second Flash EEPROM is available to the user to support
powerful, custom embedded controller applications. This can
include complex or compound DMA routines, as well as complete
standalone applications.
1.2.5 Dual Serial I/O
The VAC contains a dual, full duplex UART, with programmable baud rate
selections between 300 and 9600 and support both 7 and 8 bit characters with
programmable parity checking and generation. The lines are translated to
RS-232C levels and brought to a pair of front panel DB-2 type connectors.
If the front panel is removed, the serial ports are accessed via a 16-pin dual
inline header on the circuit board.
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Page 12 Pentek Models 4200A and 4201A Operating Manual
Rev.: A.2
1.3 Blo k Diagram
A simplified block diagram of the Pentek Model 4200/01A VME/MIX Baseboard is
presented on the following page. More thorough diagrams and detailed discussion of
the operating characteristics of the board can be found in Chapter 3 of this manual.
1.4 Spe ifi ations
Pro essor:
Type: 68EC030
Clock Speed: 40 MHz
Address Bus Width: 32 Bits
Data Bus Width: 32 Bits
Memory:
SRAM:
Size: 1 MB (2 6k x 32), Optionally expandable to 2 MB ( 12k x 32)
or 4 MB (1M x 32)
Access: 68030, VMEbus Masters, MIX Bus Masters
Flash EEPROM:
User/Configuration PROM:
Size: 2 6 kB (64k x 32)
Access: 68030
Monitor PROM:
Size: 2 6 kB (64k x 32)
Access: 68030, VMEbus Masters, Mix Bus Masters, Serial Ports
VMEbus Interfa e:
Master Fun tions:
Addressing Capabilities: A32, A24 or A16
Data Transfer: D32: Block Transfer (BLT)
Read-Modify-Write(RMW)
Unaligned Transfer (UAT)
D16: Block Transfer (BLT)
Read-Modify-Write (RMW)
D08: Even or Odd Byte Positioning (EO)
Read-Modify-Write (RMW)
Bus Request Levels: All 4 VME Levels (BREQ0 - BREQ3)
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Pentek Models 4200A and 4201A Operating Manual Page 13
Rev.: A.2
Figure 1-1: Pentek Model 4200/4201A - Top Le el Block Diagram
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Page 14 Pentek Models 4200A and 4201A Operating Manual
Rev.: A.2
1.4 Spe ifi ations (continued)
VMEbus Interfa e (continued):
Master Fun tions (continued):
Bus Release Modes: Release on Request (ROR)
Release When Done (RWD)
Release on Clear (ROC)
Release under RMC* control
Bus Capture and Hold (BCAP)
Fair-Access Timeout (FAIR)
Master Write-Posting
Indivisible Multiple-Address Cycles (IMACs)
Address Modifiers: Full Encoding Capability
Interrupt Handling: D08: Odd Byte Positioning
Handles all 7 VME levels (IH 1-7)
Supports Mailbox Interrupts
Slave Fun tions:
Address Spaces: A32, A24 or A16
Data Transfer: D32: Block Transfer (BLT)
Read-Modify-Write(RMW)
Unaligned Transfer (UAT)
D16: Block Transfer (BLT)
Read-Modify-Write (RMW)
D08: Even or Odd Byte Positioning (EO)
Read-Modify-Write (RMW)
Supports Slave Write-Posting
Block Transfer Support: Programmable (DMA, Non-DMA, None)
Address Modifiers: Full Decoding Capability
Interrupt Generation: D08: Odd Byte Positioning
Interrupts on all 7 VME levels (I 1-7)
Release on Acknowledge (ROAK)
Supports Mailbox Interrupts
System Controller Fun tions:
Arbitration: Round-Robin Sequence (RRS)
Prioritized (PRI)
Programmable Timer for Arbitration Timeout
Bus Lines Driven: SYSCLK
SYSRESET
Bus Grant I/O Daisy Chain (all 4 levels)
IACK Daisy Chain
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Pentek Models 4200A and 4201A Operating Manual Page 15
Rev.: A.2
1.4 Spe ifi ations (continued)
VME Subsystem Bus (VSB) Interfa e:
Master, Interrupt Handler
Address Bus Width: 32 Bits
Data Bus Width: 32 Bits
MIX Bus Interfa e: Master/Slave, Interrupt Handler
Address Bus Width: 32 Bits
Data Bus Width: 32 Bits
DMA Transfer Rates:
Bus Master Transfer Path Speed
VIC/VAC VME - SRAM 16 MB/Sec
68030 MIX - SRAM 3 MB/Sec
VSB - MIX* 3 MB/Sec
SRAM - VSB* 3 MB/Sec
* - Single cycle access only
MIX Module Consult the Operating Manual for the MIX
(Upper Master) Module in question (42 4, 42 7 or 4270)
VME Slave Delay (DS* - DTACK*):
SRAM: Single Cycle: 200 nsec
Block Transfer: 100 nsec
MIX: Single Cycle: 300 nsec
Block Transfer: N/A
Serial Ports (Full Duplex RS-232):
Number of Ports: 2
BAUD Rates: (Common to both ports) 300, 600, 1200, 2400, 4800 or
9600. Non-standard rates also supported.
Parity: Odd, Even, None
Stop Bits: 2 on Transmit, 1 on Receive
Buffering: Double on Transmit, Quint on Receive
Interrupt-Driven Operation: Supported
Power: 1A typ. @ + V
Size: Standard 6U VME Board
Depth: 160 mm (6.3 in.)
Height: 233. mm (9.2 in.)
Width: With front panel installed, 0.8 in.
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Page 16 Pentek Models 4200A and 4201A Operating Manual
Rev.: A.2
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Pentek Models 4200A and 4201A Operating Manual Page 17
Rev.: A.2
Chapter 2: Installation, Connections and Setup
2.1 Inspe tion
After unpacking the unit, inspect it carefully for possible damage to connectors or
components. If you discover any damage, please contact Pentek immediately, at the
phone number shown on this manual’s title page. Please save the original shipping
container and packing material, in case re-shipment is required.
2.2 Jumper Settings
On the two following pages are drawings of the three printed circuit boards that com-
prise the Model 4200/01A, showing the locations of the Jumper Blocks referred to in the
sections below. We refer to the larger board, with the VME backplane connectors
(shown in Figure 2-1), as the VME board. The smaller board, which houses the 68030,
its SRAM, and the Model 4200A’s VSB Interface chip set (shown in Figure 2-2), is
known as the Mezzanine board. All the jumper blocks utilized on these boards are of
the 3-pin, single inline, right-angle variety, and are located near the edges of the
boards. This allows access to the Jumper Blocks without removing the Mezzanine board
from the VME board.
Additionally, there are two 6-pin dual inline Jumper Blocks on the Model 4200/01A’s
front panel board, for configuring the connections to the Serial Ports. A drawing of this
board is also shown in Figure 2-2, showing the locations of these Jumper Blocks. Their
functions are also described below.
2.2.1 VMEbus Slot 1 System Controller Jumper - JB1, VME Board
The Model 4200/01A’s VME System Controller functions are enabled by the
installation of a shorting jumper between pins 1 and 2 of Jumper Block JB1
on the VME board. Installing a jumper in this position allows the 4200/01A
to arbitrate requests from VMEbus Masters (the default arbitration mode is
RRS, or Round Robin Sequenced), and to drive the SYSCLOCK and
SYSRESET lines, and the IACK and Bus Grant I/O daisy chains, on the
VMEbus.
To disable the Model 4200/01A’s System Controller functions (i. e., if you
wish to use another device as your Slot 1 System Controller), place a shorting
jumper between pins 2 and 3 of JB1 on the 4200/01A’s VME board. The
factory default settings have the jumper in this position. Remember that
there can be ONE AND ONLY ONE System Controller in any given VME
card cage, and that the controller MUST reside in Slot 1 of the card cage.
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Page 18 Pentek Models 4200A and 4201A Operating Manual
Rev.: A.2
VAC
068A
VIC
068A
J3
JB3
Nylon spacers for mounting
Mezzanine Board
JB
JB2
Mounting Hole for Front
Panel Board Bracket
Figure 2-1: Model 4200/4201A VME board drawing showing jumper bloc and mounting hole locations
MIX
Connector
Pattern
Nylon spacers
for mounting
Mezzanine Board
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Pentek Models 4200A and 4201A Operating Manual Page 19
Rev.: A.2
JB2
JB
JB2
68EC030
J3
VSB
1400B
VSB
1400A
JB5 JB4
Mounting Hole Mounting Hole
JB3JB
Mounting HoleMounting Hole
Bracket
Mounting Hole
Figure 2-2: Model 4200/4201A Mezzanine board (left) and Front Panel board (right) drawings showing
jumper bloc and mounting hole locations. The side of Mezzanine board shown is mounted face down.
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