Pentek 71620 User manual

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Pentek Model 71620 Operating Manual Page 1
Manual Part No: 800.71620 Rev: 2.14 − December 27, 2017
Pentek, Inc.
One Park Way
Upper Saddle River, NJ 07458
(201) 818−5900
http://www.pentek.com
Copyright © 2010−2017
OPERATING MANUAL
MODEL 71620
3−Channel 200 MHz A/D, 2−Channel 800 MHz D/A
Cobalt Family XMC Module
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Page 2 Pentek Model 71620 Operating Manual
Warranty
Pentek warrants that all products manufactured by Pentek conform to published Pentek specifications and are free from defects in mate−
rials and workmanship for a period of one year from the date of delivery when used under normal operating conditions and within the
service conditions for which they were furnished. The obligation of Pentek arising from a warranty claim shall be limited to repairing or
at its option, replacing without charge, any product that in Pentek’s sole opinion proves to be defective within the scope of the warranty.
Pentek must be notified in writing of the defect or nonconformity within the warranty period and the affected product returned to Pentek
within thirty days after discovery of such defect or nonconformity. Buyer shall prepay shipping charges, taxes, duties and insurance for
products returned to Pentek for warranty service. Pentek shall pay for the return of products to buyer except for products returned from
another country.
Pentek shall have no responsibility for any defect or damage caused by improper installation, unauthorized modification, misuse, neglect,
inadequate maintenance, or accident, or for any product that has been repaired or altered by anyone other than Pentek or its authorized
representatives.
The warranty described above is buyer’s sole and exclusive remedy and no other warranty, whether written or oral, is expressed or
implied. Pentek specifically disclaims fitness for a particular purpose. Under no circumstances shall Pentek be liable for any direct, indi−
rect, special, incidental, or consequential damages, expenses, losses or delays (including loss of profits) based on contract, tort, or any
other legal theory.
Copyrights
The contents of this publication are Copyright © 2010−2017, Pentek, Inc. All Rights Reserved. Contents of this publication may not be
reproduced in any form without written permission.
Trademarks
Pentek, Cobalt, GateFlow, and ReadyFlow are registered trademarks or trademarks of Pentek, Inc.
Linux is a registered trademark of Linus B. Torvaids. PowerPC is a registered trademark of International Business Machines Corporation.
Microsoft and Windows are registered trademarks of Microsoft Corporation. PCI, PCI Express, PCIe, and PCI−SIG are trademarks or reg−
istered trademarks of PCI−SIG. VxWorks is a registered trademark of Wind River Systems, Inc. Xilinx and Virtex are registered trade−
marks or trademarks of Xilinx, Inc.
Manual Revision History
Date Revision Comments
6/10 − 5/11 Preliminary Contact Factory for manual revision history.
6/21/11 A Sect 5.14, corrected description of BUSY bit in CDC Control/Status Register, per KBCase 1382.
Release manual Revision A.
7/21/11 A.1 Sect 5.33, added note to NUM BYTES, bits 3−0, for accessing board ID EEPROM.
8/18/11 A.2 Sect 2.7.1, corrected external CLK maximum input to +12 dBm.
10/25/11 A.3 Sect 7.17, corrected RAM Capture Count Register address to 0x30044 in Table 7−17.
11/4/11 A.4 Sect 3.5.3, Sect 5.14, & Sect 5.21, corrected description of CDC reset per KBCase 1391.
12/13/11 A.5 Sect 2.2.2, updated switch SW2 descriptions.
Sect 2.7.2, removed incorrect reference to Option 002.
12/22/11 A.6 Sect 5.34.1, added new EEPROM format for boards shipped in November 2011 or later.
Sect 2.5 & Sect 2.7.4, added Note of input limits for PMC P14 and front panel Sync Bus connectors.
1/16/12 2.0 Version number change only. (Starting January 2012 Pentek upgraded document Version numbering.)
4/20/12 2.1 Sect 1.14 & Sect 2.7.1, corrected external clock input voltage limit to +10 dBm.
5/10/12 2.2 Sect 1.14, deleted Output IF specification for Digital to Analog Upconverter.
11/20/12 2.3 Sect 2.5.1, add XMC P16 connector pin definition table.
4/22/13 2.4 Updated several graphics’ fonts.
5/28/13 2.5 Sect 1.14 & Sect 2.7.1, corrected external clock input frequency maximum to 800 MHz.
8/2/13 2.6 Table 3−20, corrected Min VCCINT address to 0x08094.
9/6/13 2.7 Verified & updated cross−reference links in manual.
2/19/14 2.8 Sect 3.2.2, increased minimum number of clock cycles to 5 for DELAY in ADC Input Linked List.
3/21/14 2.9 Sect 2.2.2, changed switch SW2−5 to OFF, factory use only.
4/21/14 2.10 Sect 1.14, spec update: removed environmental Option 700 − Option 701 is now default.
6/12/14 2.11 Sect 1.14 & Sect 3.5, changed external Sync unit needed to Pentek Model 7893.
9/18/14 2.12 Sect 5.30, changed Timestamp Start Time Register to Write Only.
6/25/15 2.13 Sect 2.7.4, provided Pentek Model numbers for available mating connectors.
12/27/17 2.14 Sect 2.5.2 & Table 2−8, removed references to VMEbus from P14 connector.
Printed in the United States of America.
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Pentek Model 71620 Operating Manual Page 3
Page
Table of Contents
Rev.: 2.14
Chapter 1: Introduction
1.1 General Description............................................................................................................................17
1.2 Features ................................................................................................................................................17
1.3 Block Diagram.....................................................................................................................................18
Figure 1−1: Model 71620 Block Diagram.......................................................................................18
1.4 Principle of Operation........................................................................................................................19
1.5 Analog to Digital Input Conversion ................................................................................................20
1.6 Digital to Analog Output Conversion .............................................................................................20
1.7 FPGA Digital Interfaces .....................................................................................................................20
1.8 FPGA Configurations.........................................................................................................................20
1.9 Memory................................................................................................................................................21
1.10 Timing and Synchronization.............................................................................................................21
1.11 XMC Baseboard Interfaces ................................................................................................................21
1.12 Board Support Software ....................................................................................................................22
1.13 Supporting Documentation...............................................................................................................22
1.14 Specifications.......................................................................................................................................23
Chapter 2: Installation and Connections
2.1 Inspection.............................................................................................................................................29
Figure 2−1: Model 71620 PCB Assembly Drawing, Connector Side .......................................29
2.2 DIP Switch Settings ............................................................................................................................30
Figure 2−2: Model 71620 Main PCB Assembly Drawing, Solder Side....................................30
2.2.1 Switch SW1 − FPGA MGT Clock Operation ................................................................31
Table 2−1: SW1 − FPGA MGT Clock Operation........................................................31
Table 2−2: Aux MGT Clock Frequency − Switches SW1−3:4 ..................................31
Figure 2−3: Model 71620 FPGA MGT Clock Logic ....................................................32
2.2.2 Switch SW2 − FPGA Configuration ...............................................................................33
Table 2−3: SW2 − FPGA Configuration .......................................................................33
Table 2−4: FPGA Configuration Select − Switches SW2−3:4...................................33
2.3 PCB Jumpers........................................................................................................................................34
Figure 2−4: Model 71620 PCB Jumpers, Connector Side............................................................34
Table 2−5: Virtex−6 Program eFUSE Enable − Jumper Block J28 ............................................34
2.4 PCB LEDs.............................................................................................................................................35
Figure 2−5: Model 71620 PCB LEDs, Solder Side........................................................................35
Table 2−6: PCB LED Use ..................................................................................................................35
2.5 Baseboard Connectors........................................................................................................................36
2.5.1 XMC Connectors ...............................................................................................................36
Table 2−7: Option 105 XMC P16 FPGA Pin Connections.........................................36
2.5.2 PMC FPGA Connections (Option 104) ..........................................................................37
Table 2−8: Option 104 PMC P14 FPGA Pin Connections .........................................37
2.6 Installing the Model 71620 on an XMC Baseboard........................................................................38
Figure 2−6: Typical XMC Baseboard − Connectors & Mounting Hardware ........38
Figure 2−7: Baseboard PMC/XMC Connections.........................................................39
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Page 4 Pentek Model 71620 Operating Manual
Page
Table of Contents
Rev.: 2.14
Chapter 2: Installation and Connections (continued)
2.7 Front Panel Connections ................................................................................................................... 40
Figure 2−8: Model 71620 Front Panel............................................................................................40
2.7.1 Clock Input Connector .................................................................................................... 40
2.7.2 Analog Output Connectors ............................................................................................. 41
2.7.3 Analog Input Connectors ................................................................................................ 41
2.7.4 Sync Bus Connector ......................................................................................................... 42
Table 2−9: SYNC/GATE Connector Pins..................................................................... 42
2.8 Front Panel LEDs................................................................................................................................ 43
2.8.1 Link LED ............................................................................................................................ 43
2.8.2 User LED ........................................................................................................................... 43
2.8.3 Master LED ....................................................................................................................... 43
2.8.4 PPS LED ............................................................................................................................. 43
2.8.5 Over Temperature LED ................................................................................................... 43
2.8.6 Clock LED .......................................................................................................................... 43
2.8.7 DAC Underrun LED ........................................................................................................ 43
2.8.8 ADC Overload LEDs ....................................................................................................... 43
Chapter 3: Model 71620 Resource Operation
3.1 Overview ............................................................................................................................................. 45
Figure 3−1: Model 71620 Data Flow...............................................................................................45
3.2 Analog to Digital Input ..................................................................................................................... 46
Figure 3−2: Analog to Digital Input Channel Data Flow .......................................................... 46
3.2.1 ADC Data Packing Formats ............................................................................................ 47
3.2.1.1 Real−only Packed ......................................................................................... 48
Table 3−1: ADC PACK FIFO − Real−only Packed Format................... 48
3.2.1.2 Real−only Unpacked .................................................................................... 48
Table 3−2: ADC PACK FIFO − Real−only Unpacked Format ............. 48
3.2.1.3 I/Q Packed .................................................................................................... 49
Table 3−3: ADC PACK FIFO − I/Q Packed Data Format...................... 49
3.2.1.4 I/Q Unpacked ............................................................................................... 49
Table 3−4: ADC PACK FIFO − I/Q Unpacked Data Format ................ 49
3.2.2 ADC Input Linked List Operation ................................................................................. 50
Table 3−5: ADC Trigger Controller Linked List RAM ............................................. 50
Table 3−6: ADC1 Trigger Controller Linked List RAM ........................................... 52
Table 3−7: ADC1 Trigger Controller Linked List RAM ........................................... 53
3.2.3 ADC DMA Operation ...................................................................................................... 54
Table 3−8: ADC DMA Meta Data Format ................................................................... 54
3.2.4 ADC DMA Linked Lists .................................................................................................. 57
Table 3−9: ADC DMA Linked List RAM.................................................................... 57
Table 3−10: ADC Link Control Word Format............................................................. 58
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Pentek Model 71620 Operating Manual Page 5
Page
Table of Contents
Rev.: 2.14
Chapter 3: Model 71620 Resource Operation (continued)
3.3 Digital To Analog Output .................................................................................................................60
Figure 3−3: Digital to Analog Output Data Flow ........................................................................60
3.3.1 DAC DMA Linked Lists ..................................................................................................61
Table 3−11: DAC DMA Linked List RAM...................................................................61
Table 3−12: DAC Link Control Word Format .............................................................62
3.3.2 DAC Output Linked List Operation ..............................................................................64
Table 3−13: DAC Output Controller Linked List RAM............................................64
Table 3−14: DAC Output Controller Linked List RAM............................................68
Table 3−15: DAC Output Controller Linked List RAM............................................69
Table 3−16: QDRII+ Waveform Storage RAM ...........................................................70
3.3.3 DAC Data Routing and Formats ....................................................................................71
3.3.3.1 Dual Bus Mode − Channel−Packed FIFO .................................................71
Table 3−17: DAC FIFO, Channel−Packed Data Format ........................71
3.3.3.2 Half Rate Bus Mode − Time−Packed FIFO ...............................................72
Table 3−18: DAC FIFO, Time Packed Data Format................................72
3.4 RAM Memory Operation ..................................................................................................................73
Figure 3−4: RAM Memory Module Interfaces.............................................................................73
3.5 Timing and Synchronization.............................................................................................................74
3.5.1 Gates ...................................................................................................................................74
Figure 3−5: Gate Logic Diagram ....................................................................................75
3.5.2 Syncs ...................................................................................................................................76
Figure 3−6: Sync Logic Diagram ....................................................................................76
3.5.3 Clocks .................................................................................................................................77
Figure 3−7: Clock Logic Diagram ..................................................................................77
3.6 Interrupt Operation............................................................................................................................78
Figure 3−8: Interrupt Signal Logic Diagram.................................................................................78
3.6.1 PCIe Interrupts ..................................................................................................................79
3.6.2 Global Interrupts ..............................................................................................................80
3.6.3 ADC Interrupts .................................................................................................................81
3.6.4 DAC Interrupts .................................................................................................................82
3.7 FPGA Resources Operation...............................................................................................................83
3.7.1 FPGA System Monitor .....................................................................................................83
Table 3−19: System Monitor Measurement Ports ......................................................83
Table 3−20: System Monitor Status Register Addresses...........................................84
Table 3−21: System Monitor Control Register Addresses........................................85
3.7.2 I2C Bus Controllers ..........................................................................................................86
3.8 FLASH Memory Operation...............................................................................................................87
Table 3−22: FLASH Memory Map..................................................................................................87
3.9 User Register Address Space ............................................................................................................87
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Page 6 Pentek Model 71620 Operating Manual
Page
Table of Contents
Rev.: 2.14
Chapter 4: Model 71620 Memory Maps
4.1 Overview ............................................................................................................................................. 89
Table 4−1: Model 71620 PCI Memory Map.................................................................................. 89
4.2 Default FPGA Memory Map ............................................................................................................ 90
Table 4−2: Default FPGA Memory Map....................................................................................... 90
Chapter 5: Global Registers
5.1 Overview ............................................................................................................................................. 97
5.2 Link Status Register ........................................................................................................................... 98
Table 5−1: Link Status Register...................................................................................................... 98
5.2.1 MSI ENABLED ................................................................................................................. 99
5.2.2 MAX RD RQST ................................................................................................................. 99
5.2.3 MAX PAYLOAD .............................................................................................................. 99
5.2.4 SEL LINK WIDTH ......................................................................................................... 100
5.2.5 CORE NOM WIDTH ..................................................................................................... 100
5.2.6 SEL LINK RATE ............................................................................................................. 100
5.2.7 CORE NOM SPEED ....................................................................................................... 100
5.2.8 LINK UPCFG CAP ......................................................................................................... 100
5.2.9 PARTNER GEN2 SPRT ................................................................................................. 100
5.2.10 LINK GEN2 CAP ........................................................................................................... 101
5.2.11 LANE RVRSL MODE .................................................................................................... 101
5.2.12 INITIAL LINK WIDTH ................................................................................................. 101
5.3 Interrupt Flag Register .................................................................................................................... 102
Table 5−2: Interrupt Flag Register ............................................................................................... 102
Table 5−3: Interrupt Register Bits................................................................................................ 103
5.4 Interrupt Enable Register ................................................................................................................ 104
Table 5−4: Interrupt Enable Register .......................................................................................... 104
5.5 Byte Swap Register........................................................................................................................... 105
Table 5−5: Byte Swap Register ..................................................................................................... 105
5.6 Interrupt Control Register............................................................................................................... 106
Table 5−6: Interrupt Control Register ......................................................................................... 106
5.7 Global Register Reset Register........................................................................................................ 107
Table 5−7: Global Register Reset Register................................................................................. 107
5.8 Board Identification Register.......................................................................................................... 108
Table 5−8: Board Identification Register.................................................................................... 108
5.9 Daughter Board ID Register ........................................................................................................... 109
Table 5−9: Daughter Board ID Register...................................................................................... 109
5.9.1 FPGA TYPE ..................................................................................................................... 109
5.9.2 FPIO TYPE ....................................................................................................................... 109
5.9.3 MEM CD TYPE ............................................................................................................... 110
5.9.4 MEM AB TYPE ............................................................................................................... 110
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Pentek Model 71620 Operating Manual Page 7
Page
Table of Contents
Rev.: 2.14
Chapter 5: Global Registers (continued)
5.10 FPGA Code Type Register...............................................................................................................111
Table 5−10: FPGA Code Type Register .......................................................................................111
5.10.1 FPGA CODE EXPL .........................................................................................................111
5.10.2 MEM CD CODE ..............................................................................................................111
5.10.3 MEM AB CODE ..............................................................................................................112
5.10.4 FPGA CODE ID ..............................................................................................................112
5.10.5 CODE TYPE .....................................................................................................................112
5.11 FPGA Code Revision Register ........................................................................................................113
Table 5−11: FPGA Code Revision Register ................................................................................113
5.12 FPGA Date Code Register ...............................................................................................................114
Table 5−12: FPGA Date Code Register........................................................................................114
5.13 ICAP Register....................................................................................................................................115
Table 5−13: ICAP Register .............................................................................................................115
5.14 CDC Control/Status Register .........................................................................................................116
Table 5−14: CDC Control/Status Register...................................................................................116
5.14.1 BUSY .................................................................................................................................116
5.14.2 PRGM ...............................................................................................................................117
5.14.3 RESET ...............................................................................................................................117
5.14.4 RST EN .............................................................................................................................118
5.14.5 VCXO STAT ....................................................................................................................118
5.14.6 REF STAT .........................................................................................................................118
5.14.7 LOCK ................................................................................................................................118
5.15 CDC Data Register............................................................................................................................119
Table 5−15: CDC Data Register ....................................................................................................119
5.15.1 CDC Word 0 Register .....................................................................................................120
Table 5−16: CDC Word 0 Register...............................................................................120
5.15.2 CDC Word 1 Register .....................................................................................................121
Table 5−17: CDC Word 1 Register...............................................................................121
5.15.3 CDC Word 2 Register .....................................................................................................122
Table 5−18: CDC Word 2 Register...............................................................................122
5.16 Clock Control/Status Register........................................................................................................123
Table 5−19: Clock Control/Status Register.................................................................................123
5.16.1 CDC RDY .........................................................................................................................123
5.16.2 CDC CLKB/CLKA LOCKED .......................................................................................123
5.16.3 CDC CLKB/CLKA DET ................................................................................................124
5.16.4 FPGA CLKB/CLKA SRC SEL ......................................................................................124
Figure 5−1: CDC/FPGA Clock Logic...........................................................................124
5.16.5 FPGA CLKB/CLKA PWR DWN .................................................................................124
5.17 Sync Bus Control Register 1 ............................................................................................................125
Table 5−20: Sync Bus Control Register 1 ....................................................................................125
5.17.1 SBUS SYNCB DRV INV .................................................................................................126
5.17.2 SBUS GATEB DRV INV .................................................................................................126
5.17.3 SBUS SYNCA DRV INV ................................................................................................126
5.17.4 SBUS GATEA DRV INV ................................................................................................126
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Page 8 Pentek Model 71620 Operating Manual
Page
Table of Contents
Rev.: 2.14
Chapter 5: Global Registers (continued)
5.17 Sync Bus Control Register 1 (continued)
5.17.5 SBUS SYNCB DRV SRC ................................................................................................ 126
5.17.6 SBUS GATEB DRV SRC ................................................................................................ 126
5.17.7 SBUS SYNCA DRV SRC ................................................................................................ 126
5.17.8 SBUS GATEA DRV SRC ................................................................................................ 127
5.17.9 CLK SEL ........................................................................................................................... 127
5.17.10 VCXO OUT DISABLE ................................................................................................... 127
5.17.11 GATEB/SYNCB MSTR ................................................................................................. 127
5.17.12 GATEA/SYNCA MSTR ................................................................................................ 128
5.17.13 CLK MASTER EN .......................................................................................................... 128
5.18 Sync Bus Control Register 2............................................................................................................ 129
Table 5−21: Sync Bus Control Register 2.................................................................................... 129
5.18.1 PPS/SYNC/GATE A/B EDGE .................................................................................... 129
5.18.2 PPS/SYNC/GATE A/B POL ....................................................................................... 130
5.18.3 PPS B RCV SRC .............................................................................................................. 130
5.18.4 SYNC B RCV SRC .......................................................................................................... 130
5.18.5 GATE B RCV SRC .......................................................................................................... 130
5.18.6 PPS A RCV SRC .............................................................................................................. 131
5.18.7 SYNC A RCV SRC .......................................................................................................... 131
5.18.8 GATE A RCV SRC ..........................................................................................................131
5.19 Sync Bus Input Delay Tap Control Register................................................................................. 132
Table 5−22: Sync Bus Input Delay Tap Control Register........................................................ 132
5.19.1 IODELAY CNTRL RDY ................................................................................................ 132
5.19.2 SBUS SYNC B/A IN DLY ............................................................................................. 133
5.19.3 SBUS GATE B/A IN DLY ............................................................................................. 133
5.20 Sync Bus Input Delay Control Register......................................................................................... 134
Table 5−23: Sync Bus Input Delay Control Register................................................................ 134
5.20.1 SBUS SYNC B/A IN DLY ............................................................................................. 134
5.20.2 SBUS GATE B/A IN DLY ............................................................................................. 134
5.21 User LED Register............................................................................................................................ 135
Table 5−24: User LED Register ..................................................................................................... 135
5.22 LED Control Register....................................................................................................................... 136
Table 5−25: LED Control Register................................................................................................ 136
5.22.1 CLK DET LED CTRL ..................................................................................................... 136
5.22.2 ALMn/OT LED DISABLE ............................................................................................137
5.22.3 PPS LED SRC .................................................................................................................. 137
5.22.4 PPS LED DISABLE .........................................................................................................137
5.22.5 USER LED SRC ............................................................................................................... 137
5.22.6 xxx MSTR LED DISABLE .............................................................................................. 138
5.23 Gate A Generate Register................................................................................................................ 139
Table 5−26: Gate A Generate Register ........................................................................................ 139
5.24 Gate B Generate Register................................................................................................................. 139
Table 5−27: Gate B Generate Register......................................................................................... 139
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Pentek Model 71620 Operating Manual Page 9
Page
Table of Contents
Rev.: 2.14
Chapter 5: Global Registers (continued)
5.25 Sync A Generate Register ................................................................................................................140
Table 5−28: Sync A Generate Register.........................................................................................140
5.26 Sync B Generate Register.................................................................................................................141
Table 5−29: Sync B Generate Register.........................................................................................141
5.27 Test Signal and Timestamp Control Register...............................................................................142
Table 5−30: Test Signal and Timestamp Control Register ......................................................142
5.27.1 TS START TIME LOAD .................................................................................................142
5.27.2 TS PPS SIG EN ................................................................................................................142
5.27.3 TS SYNCA RST EN .........................................................................................................143
5.27.4 TS MODULE RST ...........................................................................................................143
5.27.5 SYS MON RST .................................................................................................................143
5.27.6 TEST SIG SYNCB RST EN .............................................................................................143
5.27.7 TEST SIG SYNCA RST EN ............................................................................................143
5.27.8 TEST SIG RST ..................................................................................................................143
5.28 Test Sine A Frequency Control Register........................................................................................144
Table 5−31: Test Sine A Frequency Control Register ...............................................................144
5.29 Test Sine B Frequency Control Register ........................................................................................144
Table 5−32: Test Sine B Frequency Control Register ...............................................................144
5.30 Timestamp Start Time Register ......................................................................................................145
Table 5−33: Timestamp Start Time Register ..............................................................................145
5.31 TWSI Port 1 Control/Status Register.............................................................................................146
Table 5−34: TWSI Port 1 Control/Status Register .....................................................................146
5.31.1 RX FIFO CNT[4:0] ...........................................................................................................147
5.31.2 RX FIFO FULL .................................................................................................................147
5.31.3 RX FIFO EMPTY .............................................................................................................147
5.31.4 TX FIFO FULL .................................................................................................................147
5.31.5 TX FIFO EMPTY .............................................................................................................147
5.31.6 TRNSFR BUSY ................................................................................................................147
5.31.7 TWSI ADDR[6:0] .............................................................................................................148
Table 5−35: TWSI Port 1 Bus Addresses ....................................................................148
5.31.8 START TRNSFR ..............................................................................................................148
5.31.9 DATA DIR .......................................................................................................................148
5.31.10 PORT ENABLE ...............................................................................................................148
5.31.11 NUM BYTES[3:0] ............................................................................................................148
5.32 TWSI Port 1 Data Register...............................................................................................................150
Table 5−36: TWSI Port 1 Data Register .......................................................................................150
5.32.1 Main PCB LM83 Temperature Sensor .........................................................................151
Table 5−37: Main PCB LM83 Programmable Sensors.............................................151
5.32.2 Front Panel Module LM83 Temperature Sensor ........................................................151
Table 5−38: Front Panel PCB LM83 Programmable Sensors..................................151
5.32.3 Memory Module LM73 Temperature Sensors ...........................................................152
5.32.4 Si571 Programmable VCXO ..........................................................................................152
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Page 10 Pentek Model 71620 Operating Manual
Page
Table of Contents
Rev.: 2.14
Chapter 5: Global Registers (continued)
5.33 TWSI Port 2 Control/Status Register ............................................................................................ 153
Table 5−39: TWSI Port 2 Control/Status Register..................................................................... 153
5.33.1 MGA[2:0] ......................................................................................................................... 154
5.33.2 RX FIFO CNT[4:0] .......................................................................................................... 154
5.33.3 RX FIFO FULL ................................................................................................................ 154
5.33.4 RX FIFO EMPTY ............................................................................................................. 154
5.33.5 TX FIFO FULL ................................................................................................................ 154
5.33.6 TX FIFO EMPTY ............................................................................................................. 154
5.33.7 TRNSFR BUSY ................................................................................................................ 154
5.33.8 TWSI ADDR[6:0] ............................................................................................................ 155
5.33.9 START TRNSFR ............................................................................................................. 155
5.33.10 DATA DIR ....................................................................................................................... 155
5.33.11 PORT ENABLE ............................................................................................................... 155
5.33.12 NUM BYTES[3:0] ............................................................................................................ 155
5.34 TWSI Port 2 Data Register .............................................................................................................. 157
Table 5−40: TWSI Port 2 Data Register....................................................................................... 157
5.34.1 Cobalt Serial EEPROM .................................................................................................. 158
Table 5−41: EEPROM Contents (Old Format) .......................................................... 159
Table 5−42: EEPROM Contents (New Format)......................................................... 160
5.35 Global Interrupt Enable Register ................................................................................................... 161
Table 5−43: Global Interrupt Enable Register........................................................................... 161
Table 5−44: Global Interrupt Register Bits ................................................................................ 162
5.36 Global Interrupt Status Register .................................................................................................... 163
Table 5−45: Global Interrupt Status Register ............................................................................ 163
5.37 Global Interrupt Flag Register........................................................................................................ 164
Table 5−46: Global Interrupt Flag Register................................................................................ 164
Chapter 6: Analog to Digital Channel Registers
6.1 Overview ........................................................................................................................................... 165
Figure 6−1: Analog to Digital Input Channel Data Flow ........................................................ 165
6.2 Channel Status/Power Management Registers........................................................................... 166
Table 6−1: Channel Status/Power Management Registers ..................................................... 166
6.2.1 DMA DSBL ...................................................................................................................... 166
6.2.2 MMCM PWR DWN ....................................................................................................... 166
6.2.3 MEM CTRL DSBL .......................................................................................................... 167
6.2.4 ADC PWR DN ................................................................................................................ 167
6.2.5 ACQ TYPE ....................................................................................................................... 167
6.2.6 CHAN PRESENT ........................................................................................................... 167
6.3 ADC Input Delay Tap Control Registers...................................................................................... 168
Table 6−2: ADC Input Delay Tap Control Registers ............................................................... 168
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Pentek Model 71620 Operating Manual Page 11
Page
Table of Contents
Rev.: 2.14
Chapter 6: Analog to Digital Channel Registers (continued)
6.4 ADC Data Control Registers...........................................................................................................169
Table 6−3: ADC Data Control Registers .....................................................................................169
6.4.1 SYNC SEL ........................................................................................................................169
6.4.2 OV LED SEL ....................................................................................................................170
6.4.3 TS SUB EN .......................................................................................................................170
6.4.4 ADC DITHER ..................................................................................................................170
6.4.5 PACK FIFO RST ..............................................................................................................170
6.4.6 USR DAT SEL ..................................................................................................................170
6.4.7 PACK MODE ..................................................................................................................170
6.4.8 DATA SRC .......................................................................................................................171
6.5 ADC Rate Divider Registers ...........................................................................................................172
Table 6−4: ADC Rate Divider Register .......................................................................................172
6.6 ADC Gate/Trigger Control Registers............................................................................................173
Table 6−5: ADC Gate/Trigger Control Registers.......................................................................173
6.6.1 LOC GATE SEL ...............................................................................................................173
6.6.2 TRIG LINKED LIST RST ...............................................................................................174
6.6.3 TIMESTAMP FIFO RST .................................................................................................174
6.6.4 TRIG NUM RST ..............................................................................................................174
6.6.5 PPS LATCH EN ..............................................................................................................174
6.6.6 USR DVAL EN ................................................................................................................174
6.6.7 TRIG CLR .........................................................................................................................175
6.6.8 TRIG HOLD .....................................................................................................................175
6.6.9 GATE TRIG IN EN .........................................................................................................175
6.6.10 TRIG MODE ....................................................................................................................175
6.7 ADC Trigger Gen Linked List Start Pointer Registers ................................................................176
Table 6−6: ADC Trigger Gen Linked List Start Pointer Registers.........................................176
6.8 Local Gate Generate Registers ........................................................................................................177
Table 6−7: Local Gate Generate Registers ..................................................................................177
6.9 RAM Control Registers....................................................................................................................178
Table 6−8: RAM Control Registers ..............................................................................................178
6.9.1 RAM READ EN ..............................................................................................................178
6.9.2 RAM PATH EN ..............................................................................................................178
6.9.3 RAM RST .........................................................................................................................179
6.9.4 MEM CTLR RST .............................................................................................................179
6.10 Input DC Offset Registers................................................................................................................180
Table 6−9: Input DC Offset Registers .........................................................................................180
6.11 Input Gain Trim Registers...............................................................................................................181
Table 6−10: Input Gain Trim Registers.......................................................................................181
6.12 ADC DMA Control Registers .........................................................................................................182
Table 6−11: ADC DMA Control Registers..................................................................................182
6.12.1 BYTE SWAP .....................................................................................................................182
6.12.2 DMA AT ...........................................................................................................................183
6.12.3 DMA TC ...........................................................................................................................183
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Page 12 Pentek Model 71620 Operating Manual
Page
Table of Contents
Rev.: 2.14
Chapter 6: Analog to Digital Channel Registers (continued)
6.12 ADC DMA Control Registers (continued)
6.12.4 DMA ATTR1 ................................................................................................................... 183
6.12.5 DMA ATTR0 ................................................................................................................... 183
6.12.6 DMA ABORT .................................................................................................................. 183
6.12.7 DMA IN FIFO RST ......................................................................................................... 184
6.12.8 DMA RST ........................................................................................................................ 184
6.12.9 DMA ADV ....................................................................................................................... 184
6.13 ADC Interrupt Enable Registers .................................................................................................... 185
Table 6−12: ADC Interrupt Enable Registers ............................................................................ 185
Table 6−13: ADC Interrupt Register Bits.................................................................................... 186
6.14 ADC Interrupt Flag Registers......................................................................................................... 187
Table 6−14: ADC Interrupt Flag Registers ................................................................................. 187
6.15 ADC Interrupt Status Registers...................................................................................................... 188
Table 6−15: ADC Interrupt Status Registers.............................................................................. 188
6.16 IDelay and Clock Status Registers ................................................................................................. 189
Table 6−16: IDelay and Clock Status Registers......................................................................... 189
6.16.1 MEM CLK FB STOPPED ............................................................................................... 189
6.16.2 MEM CLK IN STOPPED ...............................................................................................189
6.16.3 MEM MMCM LOCK ..................................................................................................... 189
6.16.4 MEM IODLY CTRL RDY .............................................................................................. 190
6.16.5 FPGA CLKA NOT DET ................................................................................................. 190
Figure 6−2: CDC/FPGA ADC Clock Logic ................................................................ 190
6.16.6 CDC CLKA LOCK ......................................................................................................... 190
6.16.7 ADC IODLY CTRL RDY ............................................................................................... 190
6.17 RAM Controller Status Registers................................................................................................... 191
Table 6−17: RAM Controller Status Registers........................................................................... 191
6.17.1 RAM FIFO FULL ............................................................................................................ 191
6.17.2 RAM FIFO AFL .............................................................................................................. 191
6.17.3 RAM FIFO AEM ............................................................................................................. 192
6.17.4 RAM FIFO EMP .............................................................................................................. 192
6.17.5 DDR DET ......................................................................................................................... 192
6.17.6 DDR PHY INIT DONE .................................................................................................. 192
6.17.7 QDR DET ......................................................................................................................... 192
6.17.8 QDR CAL CMPLT ......................................................................................................... 192
6.18 RAM FIFO Count Registers............................................................................................................ 193
Table 6−18: RAM FIFO Count Registers .................................................................................... 193
6.19 ADC DMA Status Registers............................................................................................................ 194
Table 6−19: ADC DMA Status Registers.................................................................................... 194
6.19.1 WAITING FOR ADV ..................................................................................................... 194
6.19.2 ABORT IN PROGRESS .................................................................................................. 194
6.19.3 NEXT LINK ..................................................................................................................... 194
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Pentek Model 71620 Operating Manual Page 13
Page
Table of Contents
Rev.: 2.14
Chapter 6: Analog to Digital Channel Registers (continued)
6.20 Data Rate Detection Control Registers ..........................................................................................195
Table 6−20: Data Rate Detection Control Registers..................................................................195
6.20.1 DATA RATE SYNC RST EN .........................................................................................195
6.20.2 DATA RATE RST ...........................................................................................................195
6.20.3 CLR DATA RATE PEAK ...............................................................................................195
6.20.4 MON CLK PERIOD ........................................................................................................196
6.21 Data Rate Detection Value Registers .............................................................................................197
Table 6−21: Data Rate Detection Value Registers.....................................................................197
6.22 Peak Data Rate Detection Value Registers....................................................................................198
Table 6−22: Peak Data Rate Detection Value Registers...........................................................198
Chapter 7: Digital to Analog Channel Registers
7.1 Overview............................................................................................................................................199
Figure 7−1: Digital to Analog Output Data Flow ......................................................................199
7.2 Channel Status/Power Management Register.............................................................................200
Table 7−1: Channel Status/Power Management Register........................................................200
7.2.1 DMA DSBL ......................................................................................................................200
7.2.2 MMCM PWR DWN .......................................................................................................200
7.2.3 MEM CTRL DSBL ...........................................................................................................201
7.2.4 ACQ TYPE .......................................................................................................................201
7.2.5 CHAN PRESENT ............................................................................................................201
7.3 Output Delay Tap Control Register...............................................................................................202
Table 7−2: Output Delay Tap Control Register.........................................................................202
7.4 DAC Data Control Register.............................................................................................................203
Table 7−3: DAC Data Control Register .......................................................................................203
7.4.1 SYNC SEL ........................................................................................................................203
7.4.2 UR LED EN ......................................................................................................................203
7.4.3 SYNC OUT EN ................................................................................................................204
7.4.4 DAC RST ..........................................................................................................................204
7.4.5 OUT FIFO RST ................................................................................................................204
7.4.6 DATA SRC .......................................................................................................................204
7.5 DAC Rate Divider Register .............................................................................................................205
Table 7−4: DAC Rate Divider Register .......................................................................................205
7.6 DAC Gate/Trigger Control Register .............................................................................................206
Table 7−5: DAC Gate/Trigger Control Register ........................................................................206
7.6.1 OUT CNTRL LINKED LIST RST ..................................................................................206
7.6.2 TRIG CLR .........................................................................................................................207
7.6.3 TRIG HOLD .....................................................................................................................207
7.6.4 GATE TRIG IN EN .........................................................................................................207
7.6.5 TRIG MODE ....................................................................................................................207
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Page 14 Pentek Model 71620 Operating Manual
Page
Table of Contents
Rev.: 2.14
Chapter 7: Digital to Analog Channel Registers (continued)
7.7 Output Controller Linked List Start Pointer Register................................................................. 208
Table 7−6: Output Controller Linked List Start Pointer Register.......................................... 208
7.8 RAM Capture Start Address Register ........................................................................................... 209
Table 7−7: RAM Capture Start Address Register ..................................................................... 209
7.9 RAM Control Register ..................................................................................................................... 210
Table 7−8: RAM Control Register................................................................................................ 210
7.9.1 RAM CAPT ADDR LD .................................................................................................. 210
7.9.2 DDR3 DATA DIR ........................................................................................................... 210
7.9.3 RAM READ EN .............................................................................................................. 210
7.9.4 RAM PATH EN ..............................................................................................................211
7.9.5 RAM RST ......................................................................................................................... 211
7.9.6 DATA REPACK RST ..................................................................................................... 211
7.9.7 MEM CTLR RST .............................................................................................................211
7.10 Output Gate Delay Register............................................................................................................ 212
Table 7−9: Output Gate Delay Register...................................................................................... 212
7.11 DAC DMA Control Register........................................................................................................... 213
Table 7−10: DAC DMA Control Register................................................................................... 213
7.11.1 BYTE SWAP .................................................................................................................... 213
7.11.2 DMA AT .......................................................................................................................... 214
7.11.3 DMA TC .......................................................................................................................... 214
7.11.4 DMA ATTR1 ................................................................................................................... 214
7.11.5 DMA ATTR0 ................................................................................................................... 214
7.11.6 DMA ABORT .................................................................................................................. 214
7.11.7 DMA RST ........................................................................................................................ 215
7.11.8 DMA ADV ....................................................................................................................... 215
7.12 DAC Interrupt Enable Register...................................................................................................... 216
Table 7−11: DAC Interrupt Enable Register .............................................................................. 216
Table 7−12: DAC Interrupt Register Bits.................................................................................... 217
7.13 DAC Interrupt Flag Register .......................................................................................................... 218
Table 7−13: DAC Interrupt Flag Register................................................................................... 218
7.14 DAC Interrupt Status Register ....................................................................................................... 219
Table 7−14: DAC Interrupt Status Register ............................................................................... 219
7.15 ODelay and Clock Status Register................................................................................................. 220
Table 7−15: ODelay and Clock Status Register......................................................................... 220
7.15.1 MEM CLK FB STOP ....................................................................................................... 220
7.15.2 MEM CLK IN STOP ....................................................................................................... 220
7.15.3 MEM MMCM LOCK ..................................................................................................... 220
7.15.4 MEM IODLY CTRL RDY .............................................................................................. 221
7.15.5 FPGA CLKB NOT DET ................................................................................................. 221
Figure 7−2: CDC/FPGA DAC Clock Logic ................................................................ 221
7.15.6 CDC CLKB LOCK .......................................................................................................... 221
7.15.7 DAC IODLY CTRL RDY ............................................................................................... 221
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Pentek Model 71620 Operating Manual Page 15
Page
Table of Contents
Rev.: 2.14
Chapter 7: Digital to Analog Channel Registers (continued)
7.16 RAM Controller Status Register .....................................................................................................222
Table 7−16: RAM Controller Status Register .............................................................................222
7.16.1 REPACK NOT EMP .......................................................................................................222
7.16.2 DDR DET .........................................................................................................................222
7.16.3 DDR PHY INIT DONE ..................................................................................................223
7.16.4 QDR DET .........................................................................................................................223
7.16.5 QDR CAL CMPLT ..........................................................................................................223
7.17 RAM Capture Count Register.........................................................................................................224
Table 7−17: RAM Capture Count Register .................................................................................224
7.18 DAC DMA Status Register..............................................................................................................225
Table 7−18: DAC DMA Status Register ......................................................................................225
7.18.1 WAITING FOR ADV .....................................................................................................225
7.18.2 ABORT IN PROGRESS ..................................................................................................225
7.18.3 ALL DATA RCVD ..........................................................................................................226
7.18.4 NEXT LINK .....................................................................................................................226
7.19 DAC Serial Address Register..........................................................................................................227
Table 7−19: DAC Serial Address Register ..................................................................................227
7.19.1 SERIAL BUSY ..................................................................................................................227
7.19.2 SER ADDR[4:0] ...............................................................................................................227
Table 7−20: DAC5688 Register Addresses..................................................................................228
7.20 DAC Serial Data Register ................................................................................................................229
Table 7−21: DAC Serial Data Register.........................................................................................229
7.21 Data Rate Detection Control Register............................................................................................230
Table 7−22: Data Rate Detection Control Register....................................................................230
7.21.1 DATA RATE SYNC RST EN .........................................................................................230
7.21.2 DATA RATE RST ...........................................................................................................230
7.21.3 CLR DATA RATE PEAK ...............................................................................................230
7.21.4 MON CLK PERIOD ........................................................................................................230
7.22 Data Rate Detection Value Register...............................................................................................231
Table 7−23: Data Rate Detection Value Register.......................................................................231
7.23 Peak Data Rate Detection Value Register .....................................................................................232
Table 7−24: Peak Data Rate Detection Value Register.............................................................232
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Page 16 Pentek Model 71620 Operating Manual
Page
Table of Contents
Rev.: 2.14
Appendix A: PCI Configuration Space Registers
A.1 Introduction .......................................................................................................................................... 1
A.2 PCI Configuration Space Registers.................................................................................................... 1
Table A−1: PCI Configuration Space Header (Type 00h) ........................................................... 1
Table A−2: PCI Base Address Registers ......................................................................................... 2
Appendix B: Sample 71620 Applications
B.1 Introduction .......................................................................................................................................... 1
B.2 Using Triggered Acquisition of ADC Data ......................................................................................2
B.2.1 Scenario 1 ............................................................................................................................. 2
B.2.2 Scenario 2 ............................................................................................................................. 3
B.3 Using the ADC DMA Engine ............................................................................................................. 4
B.3.1 Scenario 1 ............................................................................................................................. 5
B.3.2 Scenario 2 ............................................................................................................................. 8
B.3.3 Scenario 3 ........................................................................................................................... 10
B.4 Using the DAC DMA Engine and Linked List Output Controller ............................................. 13
B.4.1 Scenario 1 ........................................................................................................................... 13
B.4.2 Scenario 2 ........................................................................................................................... 16
B.4.3 Scenario 3 ........................................................................................................................... 18
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Pentek Model 71620 Operating Manual Page 17
Rev.: 2.14
Chapter 1: Introduction
1.1 General Description
Pentek’s Cobalt®Family Model 71620 is a multichannel, high−speed data converter
suitable for connection to HF or IF ports of a communications or radar system. It
includes three 200−MHz, 16−bit A/D converters and two 800−MHz D/A upconverters.
The 71620 is compatible with the VITA 42.0 XMC format and supports PCI Express®
(PCIe®) Gen 1 or 2 as a native interface.
The 71620 XMC module can be attached directly to any digital signal processing (DSP)
baseboard equipped with an XMC expansion site, or to an XMC carrier/adaptor, such
as the Pentek Model 7806 XMC PCI Express carrier.
NOTE: This 71620 Operating Manual applies to all Pentek Cobalt products that
include Pentek’s Model 71620 XMC, including the Model 78620 PCIe board
and the Model 53620 VPX board.
1.2 Features
• Three 200−MHz 16−bit A/D converters
• Two 800−MSPS 16−bit D/A converters
• Xilinx®Virtex®−6 FPGA
• Up to 32 MB of QDRII+ SRAM or 2 GB of DDR3 SDRAM
• Clock synthesizer can create different clock rates for A/D and D/A processing
• LVPECL clock/sync bus for multimodule synchronization
• PCI Express (Gen 1 or 2) interface up to x8 wide
• VITA 42.0 XMC compatible with switched fabric interfaces
• LVDS connections to the Virtex−6 FPGA for custom I/O
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Page 18 Pentek Model 71620 Operating Manual
Rev.: 2.14
1.3 Block Diagram
The following is a simplified block diagram of the Model 71620 module.
Figure 1−1: Model 71620 Block Diagram
Clock/Sync/
PPS/Gate
TIMING
CONTROL
VCXO
Virtex-6 FPGA
QDRII+
SRAM
8 MB
QDRII+
SRAM
8 MB
16 16
IN 1
RF In IN 2 RF In
200MHz
16-BITA/D 200MHz 16-BITA/D
RF
XFORMER
16 16
RF
XFORMER
IN 3
RF In
200MHz
16-BITA/D
16
RF
XFORMER
TTL Sync/PPS
TTL Gate/Trig
Sample Clk A
Sample Clk B
GateA/D
Gate D/A
Sync A/D / PPS
Sync D/A / PPS
Sample Clk /
Reference Clk In
A/D Timing Bus
XMC P15PMC P14
(Option 104) XMC P16 (Option 105)
GTX
x4
GTX GTX
PCIe
x4
FLASH
64 MB
16
PMC Baseboard/Carrier Connections
20
pair
LVDS
OUT 1
RFOut
800MHz
16-BIT D/A
RF
XFORMER
OUT 2
RFOut
800MHz
16-BIT D/A
32
RF
XFORMER
DIGITALUPCONVERTER
D/ATiming Bus
DDR3
SDRAM
512MB
DDR3
SDRAM
512MB
QDRII+
SRAM
8 MB
QDRII+
SRAM
8 MB
16 16
DDR3
SDRAM
512MB
DDR3
SDRAM
512MB
16 16 16 16
Option 150
Option 155
MemoryBanksA/B
Option 160
Option 165
MemoryBanksC/D
FPGA
I/O VITA 42.x
x8
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Pentek Model 71620 Operating Manual Page 19
Rev.: 2.14
1.4 Principle of Operation
The Model 71620 is an A/D module suitable for direct connection to HF or IF ports of a
communications or radar system. Using the popular XMC module format, it includes
three A/D converters and two D/A converters.
The 71620 is compatible with VITA 42 XMC carrier boards. This emerging standard
provides separate serial data links between the XMC and the carrier. These links sup−
port Serial RapidIO, PCI Express, and Aurora protocols and provide a dedicated high−
speed streaming data path.
The 71620 features a Xilinx Virtex−6 FPGA for signal interfaces and processing. The
FPGA is pre−configured to provide signal acquisition buffering functions. This FPGA
also provides board interfaces including PCIe and XMC. Custom I/O connections are
provided to the FPGA through the optional PMC P14 connector (Option 104). Custom
gigabit serial interfaces may be implemented through the optional XMC P16 connector
(Option 105).
Three 16−bit A/D converters provide data to the FPGA, where the data can be format−
ted, processed, or routed to board resources. Two D/A converters include both inter−
polation filters and an upconverter stage capable of producing baseband I & Q and
quadrature modulation analog output.
The 71620 includes up to 32 MBytes of QDRII+ SRAM, or 2 GBytes of DDR3 SDRAM.
This memory is controlled by the FPGA and is organized as two or four banks,
depending on the 71620 options ordered. Separate banks (separate address and data
per bank) allow simultaneous access to all banks. This memory can be used as data
capture, as buffer memory when transferring data between board resources or to off−
board resources, or as a memory resource for custom FPGA applications.
The 71620 includes an onboard VCXO and a programmable clock synthesizer for
clocking, but can also accept external clocks through front panel connectors. The 71620
is equipped with an LVPECL front panel sync bus that allows synchronizing A/D and
D/A processing on multiple modules.
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