Peritek VCT-V User manual

VCT-V, VCU-V, VCD-V
GRAPHICS BOARDS
USER'S MANUAL
Copyright (c) 1995 by
Peritek Corporation
5550 Redwood Road
Oakland, CA 94619
[phone]
FAX [phone]
email: [email protected]
Release 2.3
April 19, 1995
Applies to:
VCT-V FAB REV 4 and up
VCU-V FAB REV 4 and up
VCD-V FAB REV 2 and up

Peritek

Peritek

Table of Contents
Introduction......................................................................................................................i-1
The Organization of This Manual ................................................................................................i-1
Getting Help.................................................................................................................................i-2
Manual Revisions.........................................................................................................................i-2
Notices .........................................................................................................................................i-3
Conventions Used In This Manual...............................................................................................i-4
Chapter 1 General Information .......................................................................................1-1
1.1 Introduction...........................................................................................................................1-1
1.2 Functional Description..........................................................................................................1-2
Special Features of the VCU-V......................................................................................1-3
Special Features of the VCT-V......................................................................................1-3
Special Features of the VCD-V......................................................................................1-3
TMS 34020 Graphics Processor ....................................................................................1-3
TMS 34082 Floating Point Coprocessor.......................................................................1-4
Video RAM....................................................................................................................1-4
34020 Processor Memory (DRAM and PROM)............................................................1-5
Display Features.............................................................................................................1-5
VMEbus Interface..........................................................................................................1-6
Peripheral Support .........................................................................................................1-7
1.3 Additional References...........................................................................................................1-8
1.4 General Specifications...........................................................................................................1-9
1.5 Monitor Requirements...........................................................................................................1-16
1.6 Configuration Information.....................................................................................................1-16
Chapter 2 Installing Your Peritek Graphics Board.........................................................2-1
2.1 Introduction...........................................................................................................................2-1
2.2 Unpacking Your Board .........................................................................................................2-2
2.3 VMEbus Installation .............................................................................................................2-3
2.3.1 Default Interrupt Settings on Peritek Video Boards.............................................2-3
2.3.2 Checking Board Addresses..................................................................................2-4
2.3.3 Installing the Graphics Board...............................................................................2-5
Figure 2-1 Example VMEbus Backplane ......................................................2-6
2.3.4 What's Next?........................................................................................................2-7
2.3.5 Connecting the Mouse, Keyboard, and Console..................................................2-8
2.3.6 Checking your Display.........................................................................................2-9
Figure 2-2 Jumper Locations for the VCT-V and VCU-V........................................................2-10
Figure 2-3 Jumper Locations for the VCD-V............................................................................2-11
2.4 Option Selection....................................................................................................................2-12
2.4.1 CSR Addresses.....................................................................................................2-12
2.4.2 Interrupt Grant Receive/Acknowledge.................................................................2-13
2.4.3 Interrupt Priority..................................................................................................2-14

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Peritek

Peritek
2.4.4 Flash EEPROM....................................................................................................2-15
2.4.5 Autoboot Enable ..................................................................................................2-15
VCD Autoboot Enable.....................................................................................2-15
VCT-V and VCU-V Autoboot Enable.............................................................2-15
2.4.6 DRAM and VRAM Size......................................................................................2-16
2.4.7 Master Pixel Clock Oscillator Frequency ............................................................2-17
2.4.8 Interlaced Operation and VCU-V Slow Mode.....................................................2-18
2.4.9 BT482 Output Level (VCD-V/T - special order only).........................................2-18
2.4.10 Selecting PTERM Options.................................................................................2-19
2.4.11 Selecting Serial I/O Options...............................................................................2-20
2.5 Connections to the VCU-V, VCT-V, and VCD-V................................................................2-22
2.5.1 Console, Mouse, Trackball, and Keyboard Connectors.......................................2-23
2.5.1a Console...............................................................................................................2-23
2.5.1b Mouse and Trackball..........................................................................................2-24
2.5.1c Serial and PC Keyboards....................................................................................2-26
2.5.2 Video Connector..................................................................................................2-27
2.5.3 High Speed Data Port (HSP)................................................................................2-28
2.5.4 8-bit SCSI Port (VCT-V and VCU-V).................................................................2-29
2.5.5 Digital Video Connector (VCD-V only)..............................................................2-30
Chapter 3 Software Summary.........................................................................................3-1
3.1 Introduction...........................................................................................................................3-1
3.2 Software Availability by Platform and OS............................................................................3-2
3.3 Write Posting.........................................................................................................................3-3
3.4 PX Windows Server..............................................................................................................3-4
3.5 Graphics Subroutine Package................................................................................................3-5
3.6 PTERM Terminal Emulator..................................................................................................3-8
3.7 Software Development Package............................................................................................3-9
Features of the 34020 Development Tools ....................................................................3-10
3.8 Ancillary Programs................................................................................................................3-11
3.8.1 Initialization Tables .............................................................................................3-11
3.8.2 Software Installation Examples............................................................................3-11
3.8.3 VCnVINT ............................................................................................................3-12
3.8.4 VCnVTST............................................................................................................3-12
3.8.5 VCnVLD..............................................................................................................3-14
3.8.6 VCnVWT.............................................................................................................3-14
3.8.7 VCnVHLT ...........................................................................................................3-14
3.8.8 VCnVGO.............................................................................................................3-14
3.8.9 VCnVOFF............................................................................................................3-15
3.8.10 VCnVDMP ........................................................................................................3-15
3.8.11 TIDTSK.............................................................................................................3-15
Chapter 4 Theory of Operation.......................................................................................4-1
4.1 Introduction...........................................................................................................................4-1
4.2 System Architecture ..............................................................................................................4-2
VMEbus Interface..........................................................................................................4-2
Control Registers ...........................................................................................................4-2

Peritek
34020/VMEbus Host Interface ......................................................................................4-3
34020 Functional Unit ...................................................................................................4-3
34020 Data and Address Buses......................................................................................4-3
4.3 Graphics Board Clock Sources..............................................................................................4-4
Phase Locked Loop (PLL) Clock...................................................................................4-4
34020 Video and Processor Clock Synchronization......................................................4-5
4.4 VMEbus Interface.................................................................................................................4-5
Address Decoding..........................................................................................................4-5
Data Bus Transceivers and the Byte Swapper................................................................4-6
4.5 VMEbus Interrupt Controller................................................................................................4-7
4.6 System Arbitration ................................................................................................................4-7
Control Register Decoding (CSRREQ)..........................................................................4-8
Line Buffer Decoding (IOREQ).....................................................................................4-8
34020 Host Interface Arbitrator.....................................................................................4-9
VMEbus Block Mode....................................................................................................4-9
4.7 Display Memory....................................................................................................................4-9
VCD-V and VCU-V Pixel Size......................................................................................4-10
VCT-V Pixel Size..........................................................................................................4-10
VCD-V Display Memory Size.......................................................................................4-10
VCU-V Display Memory Size.......................................................................................4-10
VCT-V Display Memory Size........................................................................................4-11
4.8 System Memory.....................................................................................................................4-11
SIMM Sockets ...............................................................................................................4-11
Flash EEPROM..............................................................................................................4-11
4.9 Programmed Logic Devices..................................................................................................4-12
AMD MACH Field Programmable Gate Arrays (FPGA)..............................................4-12
PAL22V10 Field Programmable Gate Array (FPGA)...................................................4-12
Chapter 5 Programming On-board Devices and Memories............................................5-1
5.1 Introduction...........................................................................................................................5-1
5.2 VMEbus and Control Registers.............................................................................................5-3
5.2.1 Control/Status Register (CSR).............................................................................5-4
5.2.2 Line Address Register (LAR) ..............................................................................5-6
5.2.3 A32 Address Map and the XARADR Address Match Register...........................5-8
5.2.4 A16/A24 Address Map and DBRADR Address Match Register.........................5-9
5.2.5 VECADR Interrupt Vector Address Register ......................................................5-10
5.2.7 VMEbus Block Transfers (BLT) .........................................................................5-11
5.2.8 Device Register Access........................................................................................5-11
5.3 TMS 34020 Graphics Systems Processor..............................................................................5-14
5.3.1 34082 Floating Point Coprocessor.......................................................................5-15
5.3.2 Writemask Register..............................................................................................5-15
5.3.3 VRAM Color Register and Block Fill Special Function......................................5-16
5.3.4 Memory Types and Sizes.....................................................................................5-17
5.3.5 Byte Ordering and the Hardware Byte Swapper..................................................5-17
5.3.5a VMEbus and 34020 Byte Order Mapping .........................................................5-18
5.3.5b Example Code for Software Byte Swapping......................................................5-19

Peritek
5.3.5c The Hardware Byte Swapper .............................................................................5-19
5.3.6 Virtual Memory, Page Faults, and Autoincrement Registers...............................5-20
5.3.7 34020 Memory and Device Addresses.................................................................5-20
5.3.8 Sample Address Calculations...............................................................................5-22
5.4 Initialization Tables...............................................................................................................5-27
5.4.1 Application Note: Tweaking 34020 Initialization Parameters .............................5-31
Request for Timing Table................................................................................5-34
5.5 Vertical and Horizontal Zoom...............................................................................................5-35
Vertical Zoom................................................................................................................5-35
Horizontal Zoom............................................................................................................5-35
5.5.1 ICS1562 Type Horizontal Zoom Register ...........................................................5-36
5.5.2 VCD-V/A6 Type ICS1562 Version Horizontal Zoom Register...........................5-37
5.5.3 VCD-V/A6/D8 Type ICS1562 Version Horizontal Zoom Register.....................5-38
5.5.4 Horizontal Zoom Control Register (Non-ICS1562 VCD-V's).............................5-39
5.6 BT463 - Color Map Controller for the VCT-V.....................................................................5-43
5.7 BT468 - Color Map Controller for the VCU-V.....................................................................5-47
5.8 BT459 - Color Map Controller for the VCD-V.....................................................................5-50
5.9 BT482 - Color Map Controller for the VCD-V.....................................................................5-53
5.10 VCD-V Digital Lookup Table (DLUT) ..............................................................................5-57
5.11 Hardware Cursors................................................................................................................5-61
5.12 Serial I/O Ports (DUART)...................................................................................................5-64
5.13 SCSI Port.............................................................................................................................5-66
5.14 PC Keyboard Controller (8242PC) .....................................................................................5-69
5.15 High Speed Data Port (HSP)...............................................................................................5-69
5.16 Graphics Board Interrupts...................................................................................................5-72
5.17 Flash EEPROM and Serial EEPROM.................................................................................5-73
Chapter 6 Troubleshooting .............................................................................................6-1
6.1 Introduction...........................................................................................................................6-1
6.2 Selecting an Address Range for your Board..........................................................................6-2
Memory Map Example ..................................................................................................6-4
6.3 Does this board talk at all?....................................................................................................6-5
6.4 General Procedures ...............................................................................................................6-7
6.6 Maintenance, Warranty, and Service.....................................................................................6-9
Maintenance...................................................................................................................6-9
Warranty ........................................................................................................................6-9
Return Policy .................................................................................................................6-9
Out of Warranty Service ................................................................................................6-9

Peritek

Introduction-1
Introduction
This introductory chapter contains information about the organization of
this manual, how to get technical support, and the typographical
conventions used throughout the manual.
The Organization of This Manual
This manual provides information about how to configure, install, and
program the Peritek 34020-based VMEbus graphics controllers. Products
covered include the VCU-V ultra-high resolution controller, the VCT-V
24-bit true-color controller, and the VCD-V analog/digital controller. The
boards can be covered in one manual because their feature set is largely
the same, and the software is identical.
This manual is broken down into six chapters:
Chapter 1: Overview of the Peritek graphics boards
Chapter 2: Installing Peritek graphics boards
Chapter 3: Summary of Peritek's Software Products
Chapter 4: Theory of Operation
Chapter 5: Programming On-board Devices and Memories
Chapter 6: Troubleshooting
Chapter 1 provides interesting background material about Peritek graphics
boards. Understanding the information in the chapter, however, is not
essential for the hardware or software installation.
If you want to perform the installation as quickly as possible, start with
Chapter 2. If you have problems installing the hardware, refer to Chapter 6
for help.

Peritek
Introduction-2
Getting Help
This installation manual gives specific steps to take to install your Peritek
graphics board. There are, however, variables specific to your computer
configuration and monitor that this manual cannot address. Normally, the
default values given in this manual will work. If you have trouble
installing or configuring your system, first read Chapter 6,
"Troubleshooting". If this information does not enable you to solve your
problems, do one of the following:
1) call Peritek technical support at [phone],
2) fax your questions to [phone],
3) or send E-mail to [email protected].
If your problem is monitor related, Peritek technical support will need
detailed information about your monitor.
Manual Revisions
Revision 2.0 January 11, 1995 First Word for Windows 2.0 Master
Revision 2.1 March 27, 1995 Compensate for WFW bug which
yielded incorrect Table of Contents
and Index page numbers, fix minor
factual errors in Chapter 1.
Revision 2.2 April 6, 1995 Fixed cursor address error in Ch. 5.
Revision 2.3 April 19, 1995 Fixed some format errors. Changed
the pagination style.

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Introduction-3
Notices
Information contained in this manual is disclosed in confidence and may
not be duplicated in full or in part by any person without prior approval of
Peritek Corporation. Its sole purpose is to provide the user with adequately
detailed documentation to effectively install and operate the equipment
supplied. The use of this document for any other purpose is specifically
prohibited.
The information in this document is subject to change without notice. The
specifications of the VCU-V, VCD-V, VCT-V, and other components
described in this manual are subject to change without notice. Although it
regrets them, Peritek Corporation assumes no responsibility for any errors
or omissions that may occur in this manual.
Peritek Corporation assumes no responsibility for the use or reliability of
software or hardware that is not supplied by Peritek, or which has not been
installed in accordance with this manual.
PX Windows and Peritek are trademarks of Peritek Corporation. The
products, HP-UX, OS-9, pSOSystem, SunOS, OpenVMS, VAXeln,
Ultrix, VMEexec, V/68 SVR3, V/88 SVR3, and VxWorks are registered
trademarks of Hewlett-Packard, Microware, Integrated Systems, Sun,
DEC, DEC, DEC, Motorola, Motorola, Motorola, and Wind River,
respectively.
Copyright (c) 1994 by Peritek Corporation

Peritek
Introduction-4
Conventions Used In This Manual
The following list summarizes the conventions used throughout this
manual.
Code
fragments Code fragments, file, directory or path names and
user/computer dialogs in the manual are presented in the
courier typeface.
Commands or
program names Commands, or the names of executable programs, except those in code fragments, are in bold.
System prompts
and commands Commands in code fragments are preceded by the system prompt, a percentage sign (%), the standard prompt in UNIX's
C shell, a dollar sign ($), the OS-9 prompt, or the hash-mark
(#), the standard UNIX prompt for the Super-User.
Note Note boxes contain information either specific to one or more
platforms, or interesting, background information that is not
essential to the installation.
Caution Caution boxes warn you about actions that can cause damage
to your computer or its software.
Warning! Warning! boxes warn you about actions that can cause
bodily or emotional harm.
Keyboard usage <CR> stands for the key on your keyboard labeled
“RETURN” or “ENTER”

General Information 1-1
Chapter 1
General Information
1.1 Introduction
This chapter provides an overview of the VCT-V, VCD-V, and VCU-V
graphics controllers. Additional sections contain a bibliography,
specifications, monitor requirements, and common configurations.
This is summary information, and is not critical to the one who wishes to
press on to the installation procedures, which are contained in Chapter 2.

Peritek
1-2 General Information
1.2 Functional Description
The Peritek VCD-V, VCT-V and VCU-V are based on the second
generation TMS 34020 32-bit Graphics System Processor (GSP). The
boards offer a high degree of on-board intelligence and functionality, as
well as a straightforward frame buffer interface.
The boards are differentiated chiefly by the bits/pixel of the primary
display memory and the video output sections. The VCD-V and VCU-V
have 8 bits/pixel in the primary plane and the VCT-V has 24-bits. The
VCU-V and VCT-V have only analog RGB outputs and the VCD-V offers
both analog and digital.
The common feature set of the VCU-V, VCT-V and VCD-V includes:
 
 40 MHz 34020
 Optional 34082 Floating Point Unit (FPU)
 4 RS-232 serial I/O ports
 PC Keyboard
 4 Kb serial EEPROM
 up to 2 MB autoboot Flash PROM
 up to 32 MB 34020 memory
 Optional multiple display pages
 Hardware pan, zoom, and scroll
 Hardware bitmapped cursors,
 4 bit overlay
 SIMMs for display and 34020 memory
 PLL controlled pixel clock
 genlock support for system wide synchronization
 analog RGB video output
 Up to 72 Hz display refresh rate
 Optional 32-bit High Speed Data port
 Optional autoboot simple console terminal emulator
 BiCMOS bus transceivers and AMD MACH FPGAs
(for low power consumption)
 Single 6U VMEbus board
 Graphics Subroutine Package
 X11R6 X Window System Server

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General Information 1-3
Special Features of the VCU-V
The VCU-V has an 8-bit primary screen, an optional 8-bit SCSI port, and
up to two pages of 1600 x 1280 display. Programmable screen resolution
ranges from 640 x 480 pixels up to better than 1600 x 1280 with refresh
rates between 60 and 72 Hz vertical and 31 to 85 KHz horizontal refresh
rates non-interlaced.
Special Features of the VCT-V
The VCT-V supports displays up to 1280 x 1024, has a true color (24-bit)
primary screen, an optional 8-bit SCSI port, and up to four pages of 1280 x
1024 display. Programmable screen resolution ranges from 640 x 480
pixels up to 1280 x 1024 with refresh rates between 30 and 72 Hz vertical
and 15.7 to 73 KHz horizontal refresh rates, non-interlaced or non-
interlaced, including NTSC sync compatible 640 x 483.
Special Features of the VCD-V
The VCD-V supports displays up to 1280 x 1024, has an 8-bit primary
screen, both analog and digital (flat panel) outputs (digital is limitied to
1024 x 768), simultaneous analog and dital operation (with VGA timing
compatible panels) and up to two pages of 1280 x 1024 display.
Programmable screen resolution ranges from 640 x 480 pixels up to 1280
x 1024 with refresh rates between 30 and 72 Hz vertical and 15.7 to 73
KHz horizontal refresh rates, non-interlaced or non-interlaced, including
NTSC sync compatible 640 x 483.
The VCT and VCU are also available in DEC compatible Q-Bus and
TURBOchannel versions.
TMS 34020 Graphics Processor
The TMS 34020 is a CMOS 32-bit processor with hardware support for
graphics operations such as PIXBLT and curve-drawing algorithms.
Included is a complete set of general purpose instructions with addressing
modes tuned to high level languages. In addition to addressing a 512 MB
external memory range, the 34020 contains 30 general purpose 32-bit
registers, stack pointer, and a 512 byte LRU instruction cache. On chip
functions include 64 programmable registers used for CRT timing, I/O
control, and instruction parameters. The 34020 can receive interrupts from
the the VMEbus, serial I/O, and SCSI.

Peritek
1-4 General Information
The 34020 mediates all host accesses to display and processor memory
and control registers through a byte addressable 32 bit interface port. Bus
transceivers between the 34020 bus and VMEbus support D16 and D32
data transfers for the VMEbus.
The 34020 features single-cycle execution of general purpose instructions
and most common integer arithmetic and Boolean operations from
instruction cache. A 32-bit barrel shifter supports single cycle shift and
rotation for 1 to 32 bits.
The 34020 graphics processing hardware supports pixel and pixel-array
processing. It incorporates two and three operand raster operations with
Boolean and arithmetic operations, XY addressing, window clipping and
checking, 1 to n bits/pixel transforms, transparency, and plane masking.
Operations on single pixels (PIXT instruction) or two-dimensional arrays
(PIXBLT) are supported.
TMS 34082 Floating Point Coprocessor
For floating point intensive applications, a socket is provided for a 34082
FPU coprocessor. It conforms to the IEEE floating point standard 754-
1985 for binary floating point single or double precision addition,
subtraction, multiplication, division, square root, and comparison. In
addition, it offers 32-bit integer arithmetic, logical comparisons, and shifts.
Complex operations for graphics support include: matrix operations (1 x 3,
3 x 3, 1 x 4, and 4 x 4), backface testing, polygon elimination and clipping,
viewport scaling and conversion, 2D and 3D linear interpolation, 2D
window compare, 3D volume compare, 2 plane clipping (X, Y, Z), 2 plane
color clipping (R, G, B, I), 2D and 3D cubic splines, 3 x 3 convolution,
vector operations (add, subtract, dot and cross products, magnitude,
scaling, normalization and reflection), polynomial expansion,
multiply/accumulate, and 1D and 2D min/max.
Video RAM
The display memories use advanced 2 Mbit (256K x 8) 2-port Video RAM
(VRAM) technology, which gives approximately 95% memory availability
to the 34020 and host processors. A writemask register supports write
protection of bit planes.
The 34020 supports the VRAM accelerated functions such a block write
and fill with special VFILL and VBLT instructions. These can be used to
quickly replicate one and two dimensional patterns in memory, at up to 16

Peritek
General Information 1-5
times the single pixel rate. On the VCD-V and VCU-V, up to sixteen 8-bit
pixels can written in each 100 ns page mode cycle, resulting in a 160
Mpixel/sec VFILL time. The VCT-V, which has 32-bit pixels, has a 40
Mpixel/sec VFILL time.
34020 Processor Memory (DRAM and PROM)
The 34020 has its own "system" memory, which is independent of the
video memory. However, it does share a common address space with the
display memory and can thus be used for program store or off-screen
display data. The standard size is 1 MB of 0 wait state DRAM, and is
expandable to 32 MB.
There are four 32-pin PLCC sockets which support up to 2 MB (using
29F020 devices) of 0 wait state Flash PROM. Jumpers can be installed
which cause the 34020 to automatically start executing from PROM on
power-up. An additional 512 byte serial EEPROM can be installed which
can be used by an PROM-based program to store information necessary at
power-up (such as initialization data). PROM sets can be ordered from
Peritek which include a simple console terminal emulator combined with
the graphics subroutine package or X11R6 X Windows server.
Display Features
All boards support binary vertical zoom (1, 2, 4, 8, 16, 32), horizontal
zoom (except some VCD-Vs), multi-pixel horizontal pan and vertical
smooth scroll.
For the VCD-V and VCU-V, the display memory data is directed to the
analog monitor via a Brooktree RAMDAC color map control chip which
provides a programmable 24 bit wide color map (8 bits each red, green,
and blue). The 8-bit pixel is used as an index into the lookup table, giving
256 colors out of a palette of 16.7 Million. A two bit cursor with a 64 x 64
x 2 bit map function is also included on chip.
For the VCT-V, the display memory data is directed to the analog monitor
via a Brooktree BT463 color map control chip which provides a
programmable 24 bit wide color map (8 bits each red, green, and blue).
The 24-bit pixel is used as an index into the lookup table, giving a full
16.7 Million colors. A two bit cursor with a 64 x 64 x 2 bit map function is
also included, but incorporated in separate BT431 cursor chips.
For all boards, additional color map entries are provided for the overlay
screen and cursors. Any plane can be blanked or blinked. The analog Red,

Peritek
1-6 General Information
Green, and Blue signals from the RAMDAC are connected to a monitor
such as the Peritek CVM-19/E-7.
On the VCD-V (only) the display memory data is also directed to a
proprietary Digital LookUp Table (DLUT) which provides a
programmable 8-bit wide map. Depending on how the VCD-V is
configured, 1, 4, or 8 bit monochrome or 8-bit color (3 bits red, 3 bits
green, and 2 bits blue) can be supported. The VCL-V, available in May
1995, will support expanded 12 to 24 bit color map options. The eight
bit pixel is used as an index into the lookup table, giving 256 colors out of
a palette of 16.7 Million. A two bit cursor with a 64 x 64 x 2 bit map
function is also included. Additional color map entries are provided for the
overlay screen and cursors. Contact Peritek for information on what panels
are supported.
VMEbus Interface
The VMEbus host interface accesses Peritek graphics board memory and
on-board devices through four control registers and a 1 KB line buffer
which are located in VMEbus A16 space. The line buffer can also appear
in A24 space.
The CSR contains device interrupt enables, line buffer response enable,
and 34020 hardware reset. The LAR is a 16 bit register which maps a
portion of the address space of the graphics board into a 1 KB line buffer.
Two additional registers include programmable line buffer address,
interrupt vector address and programmable extended address (A32)
decoder. Access to the board through the A16 space provides a "lowest
common denominator" access mode which allows the board to be
compatible with any host CPU. In an A16 VMEbus system it is necessary
to "window" into on-board memory because it is so large (maximum
memory capacity on the board is more than 48 MB!) The 1 KB window is
actually an efficient way of doing this.
The graphics boards also have an 64 MB window in A32 VMEbus address
space which allows direct access to all on-board memory.
VMEbus D32 block transfers are supported for A16/A24 and A32 address
spaces, which allows up to 256 bytes to be transferred at high speed over
the VMEbus. Another performance feature for the boards is a hardware
byte swapper. When enabled, four 1KB buffers are mapped to the board
which provide unswapped, byte, word, and long swaps, respectively.
The board has a VMEbus interrupt controller which supports a vectored
interrupt from the 34020.