Philips PDIUSBD12 User manual

Philips Semiconductors
Interconnectivity
_______________________________________________________________________________________________
Philips Semiconductors - Asia Product Innovation Centre
Visit http://www.flexiusb.com
1 September 1998
PDIUSBD12 Evaluation Board (PC Kit)
User’s Manual
Rev. 2.1

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PDIUSBD12 Evaluation Board (PC Kit) User’s Manual Rev. 2.1
_______________________________________________________________________________________________
Philips Semiconductors - Asia Product Innovation Centre
Visit http://www.flexiusb.com
This is a legal agreement between you (either an individual or an entity) and Philips Semiconductors.
By accepting this product, you indicate your agreement to the disclaimer specified as follows:
DISCLAIMER
PRODUCT IS DEEMED ACCEPTED BY RECIPIENT. THE PRODUCT IS PROVIDED
“AS IS” WITHOUT WARRANTY OF ANY KIND. TO THE MAXIMUM EXTENT
PERMITTED BY APPLICABLE LAW, PHILIPS SEMICONDUCTORS FURTHER
DISCLAIMS ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANT ABILITY, FITNESS FOR A PARTICULAR
PURPOSE, AND NONINFRINGEMENT. THE ENTIRE RISK ARISING OUT OF THE
USE OR PERFORMANCE OF THE PRODUCT AND DOCUMENTATION REMAINS
WITH THE RECIPIENT. TO THE MAXIMUM EXTENT PERMITTED BY
APPLICABLE LAW, IN NO EVENT SHALL PHILIPS SEMICONDUCTORS OR ITS
SUPPLIERS BE LIABLE FOR ANY CONSEQUENTIAL, INCIDENTAL, DIRECT,
INDIRECT, SPECIAL, PUNITIVE, OR OTHER DAMAGES WHATSOEVER
(INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS
PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR
OTHER PECUNIARY LOSS) ARISING OUT OF THIS AGREEMENT OR THE USE OF
OR INABILITY TO USE THE PRODUCT, EVEN IF PHILIPS SEMICONDUCTORS HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

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PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1
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TABLE OF CONTENTS
DISCLAIMER .............................................................................................................2
TABLE OF CONTENTS.............................................................................................3
INSTALLATION OF PDIUSBD12 EVALUATION BOARD........................................4
Introduction....................................................................................................................................................4
System Requirements.....................................................................................................................................4
Installation......................................................................................................................................................5
Jumper’s setting on PDIUSBD12 ISA bridging board...................................................................................5
Location of key components on the PDIUSBD12 evaluation board. ..............................................................6
Installation of firmware, INF and driver........................................................................................................7
Using the Host Applet ....................................................................................................................................7
HARDWARE DESCRIPTION.....................................................................................9
Block Diagram................................................................................................................................................9
I/O Mapping...................................................................................................................................................9
Connectors....................................................................................................................................................10
PAL Equations.............................................................................................................................................11
Address and command decoder...................................................................................................................11
Schematics....................................................................................................................................................12
Schematics for PDIUSBD12 evaluation board ............................................................................................12
Schematic for PDIUSBD12 ISA bridging board..........................................................................................13
Bill of Materials............................................................................................................................................14
Bill of materials of the PDIUSBD12 evaluation board.................................................................................14
Bill of materials of the PDIUSBD12 ISA bridging board.............................................................................14

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PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1
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INSTALLATION OF PDIUSBD12 EVALUATION BOARD
Introduction
The PDIUSBD12 evaluation kit uses 2 PC as a complete USB development environment, a host PC
with USB host capability and a device PC running PDIUSBD12’s firmware. The PDIUSBD12 ISA
bridging board is plugged inside the device PC and connects to the evaluation board using a 25-wire
cable. So the device PC behaves as a big USB device.
Features evaluation of PDIUSBD12, firmware and product prototype development can be easily done
with this setup, without the resource limitation of a micro-controller. Customers can also connect the
evaluation board to their own CPU and bus through the 25-wire cable for final product development.
The firmware is carefully developed for high rate data transmission and is written in C, that supports
Borland Turbo C for x86 and Keil C51 for 8031 currently. Supporting to other CPU platforms will be
available soon.
System Requirements
1. PDIUSBD12 evaluation board and ISA bridging board;
2. 25-wire shielding data switch cable;
3. Host PC with USB motherboard or add-on card;
4. Microsoft Windows 98 or Windows NT 5.0 Beta 2;
5. Device PC running Microsoft DOS 6.x;
6. PDIUSBD12 evaluation diskette.
For firmware development:
1. X86 CPU platform: Borland Turbo C++ 3.0 or above;
2. 8031: Keil C51 4.0 or above.
Mouse
D12
Host PC with USB host Controller
Mouse
Device PC with PDIUSBD12 ISA Bridging Board
25-Wire Cable
USB Cable
PDIUSBD12 Evaluation Board
PDIUSBD12 Evaluation Disk
D12TEST.EXE
D12TEST.SYS
D12TEST.INF
D12FW.EXE

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PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1
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Installation
Jumper’s setting on PDIUSBD12 ISA bridging board
The PDIUSBD12 ISA bridging board is plugged inside the device PC. It will occupy I/O, IRQ and DMA
resources of the device PC. To avoid possible conflicts in settings, we suggest removal of all the
unnecessary cards from the device PC. Sound card and network card may cause conflict in IRQ and
DMA setting.
Switch S1 sets the base I/O address for the D12 evaluation board. Default base address is 0x368.
The D12 evaluation board occupies 8 I/O locations. A0 to A2 are decoded on the D12 evaluation
board. Switch S1 sets the address decoding of A3 to A9. Please notice that a switch ‘ON’ is logic ‘0’.
SW(n) 12345678
Address XA3 A4 A5 A6 A7 A8 A9
Default OFF OFF ON OFF OFF ON OFF OFF
Jumpers JP1 and JP2 set the IRQ number for the D12 evaluation board. Default setting is IRQ5 or
JP1 is shorted.
IRQ Number IRQ5 IRQ7
Jumper’s Setting JP1 JP2
Default ON OFF
Jumpers JP3 to JP6 set the DMA number for the D12 evaluation board. Default setting is DMA3 or
JP4 and JP6 are shorted. Please note that a respective pair of jumpers is needed to set a particular
DMA channel.
DMA Number DMA1 DMA3
Jumper’s Setting JP3, JP5 JP4, JP6
Default OFF, OFF ON, ON
J2
ON
S1
1 8
JP1 JP2 JP3 JP4
JP5 JP6

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PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1
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Possible conflict table:
IRQ or DMA
Number Possible Conflict
IRQ5 Creative SoundBlaster™ and compatible sound cards always occupy
this IRQ by default. If this kind of sound card is installed, you should
check its settings or remove it.
Some network cards may also use this IRQ.
IRQ7 Used by parallel port by default. May cause printing problem on
device PC.
DMA1 Creative SoundBlaster™ and compatible sound cards always occupy
this DMA by default. If this kind of sound card is installed, you should
check its settings or remove it.
DMA3 No conflict.
Location of key components on the PDIUSBD12 evaluation board.
See the table below for the list of connectors.
Connector Descriptions
J1 USB upstream connector
J2 DB25 data bus connector
J3 Extension board connector
See the table below for the list of switch and LEDs.
Name Descriptions
S1, S2, S3, S4 Test switches
D1 GoodLink™ LED
D2, D3, D4, D5 Test LEDs
J2 J3
J1
S1
D1
D5 D4 D3 D2
S2S3S4

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PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1
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Installation of firmware, INF and driver
The firmware, D12FW.EXE, runs on the device PC under DOS mode. When D12FW starts, it lights up
test LEDs on the evaluation board for 1 second. This means that the I/O address setting is correct.
And the evaluation board is disconnected and re-connected to USB by SoftConnectTM. If this is the
first time that the evaluation board is connected to host PC, host OS Device Manager will prompt
installation of INF and driver. Select the location of D12TEST.INF and D12TEST.SYS and complete
installation procedure.
Some useful key command is supported when the firmware is running.
Key Operation
ESC Disconnect USB and quit PDIUSBD12 firmware.
ENTER Reconnect USB using SoftConnectTM.
iDisplay firmware status information.
vSwitch on/off verbose mode, normally turned off for faster operation.
Using the Host Applet
The test applet, D12TEST.EXE, exercises all PDIUSBD12 endpoints. Testing of control endpoints can
be further done by standard USB Chapter 9 test programs.
The operation of each endpoint is designed according to its nature that is supported in PDIUSBD12.
Generic in and generic out endpoints has max packet size of 16 bytes and supports I/O access only.
So they are suitable for small size and low rate data transfer like keyboard and logic controls. The
main endpoints have max packet size of 64 bytes or 128 bytes with double buffering and DMA
support. So they are suitable for high data rate, large size data transfer.

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PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1
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See the table below for the description of endpoints operations on PDIUSBD12 evaluation board.
Endpoint
Number Endpoint Type Operations
1Generic
In This pipe is defined as Interrupt In pipe. The PDIUSBD12 evaluation board sends key press/release data packet to the host when test keys
are pressed or released. The firmware uses I/O accesses on this
endpoint.
1Generic
Out This pipe is defined as Interrupt Out pipe. Data packet received from host is interpreted as LED control and the D12 evaluation board
firmware will light up the corresponding LED. The firmware uses I/O
accesses on this endpoint.
2Main In
Main Out These pipes are defined as Bulk In/Out endpoints. Test applet and the PDIUSBD12 evaluation board supports 3 test modes: loop-back mode,
print mode and scan mode. The firmware uses DMA for data transfer
on these endpoints.
Main endpoints support 3 different test modes:
1. Scan mode: The PDIUSBD12 evaluation board acts like a scanner. It sends data packets to the
host PC as fast as possible. This mode is used to evaluate the maximal Bulk In transfer rate.
2. Print mode: The PDIUSBD12 evaluation board acts like a printer. It receives data packets from
the host PC as fast as possible. This mode is used to evaluate the maximal Bulk Out transfer rate.
3. Loop back mode: In this mode, the PDIUSBD12 evaluation board receives data packets on Main
Out endpoint and sends them back to the host PC on Main In endpoint. This mode is used to test
the data integrity of transfers.
The “Buffer Size” setting on the test applet is determined by the firmware and hardware ability of the
evaluation board. For PC kit, the maximal size is limited to 64000; On USB-EPP kit, this is limited to
16384.
The “Repeat Times” for loop-back test controls the numbers of iterations of loop-back, which is useful
for debugging. “-1” means it is infinite.

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PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1
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HARDWARE DESCRIPTION
Block Diagram
Above block diagram shows 5 main components on the PDIUSBD12 evaluation board. Beside bus
transceiver, address/command decoder and PDIUSBD12, a general input port and a general output
port are included in the design. These input and output ports are designed for test purposes, such as
test switches and test LEDs. They also act as glue logic to adapt the PDIUSBD12 to the ISA bus. For
example, ISA interrupt is edge triggered, but PDIUSBD12 interrupt is level triggered. The MSB of the
general output port is used as interrupt enable to convert level triggered interrupt to edge triggered.
I/O Mapping
PDIUSBD12 evaluation board uses 8 I/O addresses:
Offset Usage
0D12 data register, R/W
1D12 command register, W only
2General input port, R only
3General output port, W only
4 to 7 Reserved for expansion board
USB Host Controller
USB Host Controller
Driver
USBD
D12 Sample Driver
D12TEST.SYS
D12 Sample Applet
D12TEST.EXE
PDIUSBD12
Bi-direction
Bus
Transceiver
Command
and Address
Decoder
General
Output port
General
Input port
Test
Key
Test
LED
25
Pin
I/F
25
Pin
I/F
ISA
Slot
DIP
Switches
and
Jumpers
25
Pin
I/F
CPU,
Memory,
and DMA
Controller
USB Host PC
D12 Evaluation Board
USB Device PC
Customer's System
25 Pin Interface
1. VCC, GND
2. D0 - D7
3. ADDRESS ENABLE
4. IOW, IOR, IRQ, RESET
5. DREQ, DACK, EOT
On USB host side, a
sample application program
D12TEST.EXE and a
general purpose minidriver
D12TEST.SYS are
provided.
On device side, sample firmware
D12FW.EXE is provided for
running on device PC. The
firmware is written in C for easily
portable to other CPU platforms.
D12 ISA Bridging Board
System Block
Diagram of D12
Evaluation Kit

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Bit description for general input port:
Bit Usage
0Key S1, ‘0’ for pressed
1Key S2, ‘0’ for pressed
2Key S3, ‘0’ for pressed
3Key S4, ‘0’ for pressed
4D12 GoodLinkTM pin state
5USB bus power state, ‘1’ for USB VBUS present
6D12 SUSPEND pin state
7D12 INT_N pin state
Bit description for general output port:
Bit Usage
0LED D2, ‘1’ lights up LED
1LED D3, ‘1’ lights up LED
2LED D4, ‘1’ lights up LED
3LED D5, ‘1’ lights up LED
4Reserved
5Reserved
6Suspend control, ‘1’ forces D12 SUSPEND pin low
7Interrupt enable, ‘1’ enables interrupt
Connectors
25 wire connector for PDIUSBD12 evaluation board:
Pin Type Description
1POWER VCC
2POWER GND
3I/O DATA7
4I/O Zero Wait State
5I/O DATA6
6I/O Reserved
7I/O DATA5
8OCLKOUT: This line is connected to PDIUSBD12 CLKOUT pin.
9I/O DATA4
10 I-AD_EN: This line is the decoder output for address decoding A3 to
A9. This signal is active low when PDIUSBD12 evaluation board I/O
address is selected.
11 I/O DATA3
12 IRESET: This line is used to reset or initialize system logic upon
power-up and is active high.
13 I/O DATA2
14 I-IOW: This command line instructs an I/O device to read the data on
the data bus. It may be driven by the processor or the DMA controller.
This signal is active low.
15 I/O DATA1
16 I-IOR: This command line instructs an I/O device to drive its data onto
the data bus. It may be driven by the processor or the DMA controller.
This signal is active low.

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17 I/O DATA0
18 IT/C, Terminal Count: This line provides a pulse when terminal count
for any DMA channel is reached. This signal is active high.
19 IADDR2
20 I-DACK: This line is used to acknowledge DMA request and is active
low.
21 IADDR1
22 ODRQ: This line is asynchronous channel request used by peripheral
devices to gain DMA service. A DMA request is generated by bringing
DRQ line to an active high.
23 IADDR0
24 OIRQ: This line is raising edge triggered. An interrupt request is
generated by raising this line high and hold until it is acknowledged by
the processor.
25 POWER GND
PAL Equations
Address and command decoder
/** Inputs **/
Pin 1 = ADDR2;
Pin 2 = ADDR1;
Pin 3 = ADDR0;
Pin 4 = !IOW;
Pin 5 = !IOR;
Pin 6 = !DACK;
Pin 7 = !AD_EN;
Pin 8 = RESET;
Pin 9 = INT_N;
Pin 11 = INT_EN;
/** Outputs **/
Pin 12 = IRQ;
Pin 13 = RESET_N;
Pin 14 = RD_N;
Pin 15 = WAIT;
Pin 16 = !CS_D12;
Pin 17 = !WR_273;
Pin 18 = !RD_244;
Pin 19 = !DIR_245;
/** Logic Equations **/
!DIR_245 = (!AD_EN & !DACK) # !IOR # RESET;
!RD_244 = !AD_EN # !(!ADDR2 & ADDR1 & !ADDR0) # !IOR;
!WR_273 = !AD_EN # !(!ADDR2 & ADDR1 & ADDR0) # !IOW;
!CS_D12 = !AD_EN # !(!ADDR2 & !ADDR1) # (!IOW & !IOR);
RESET_N = !RESET;
IRQ = !INT_N & INT_EN;
WAIT.OE = CS_D12;
WAIT = RESET;
RD_N = !IOR;

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PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1
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Schematics
Schematics for PDIUSBD12 evaluation board
D12-EVAL-200 2.00
D12 EVALUATION BOARD
A
1 1Thursday, April 23, 1998
Title
Size DocumentNumber Rev
Date: Sheet of
VCC VCC
VCC
VCC
VCC
V_BUS
VCC
V_BUS
VCC
V_BUS
VCC
Shell to GND
* OSC1 is optional replacement
for Y1, C5 and C6.
DATA[0..7]
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
ADDR2
ADDR1
ADDR0
ADDR2
ADDR1
ADDR0
-IOW
-IOR
-DACK
-AD_EN
-DIR_245
IRQ
IRQ
DRQ
-DACK
-IOR
-IOW
RESET
-AD_EN
-IOR
-IOW
DRQ
-DACK
ADDR0
RESET RESET_N
SUSPEND
T/C
XTAL2
XTAL1
ADDR0
ADDR1
ADDR2
-IOR
-IOW
-AD_EN
INT_EN
-WR_EVAL
D1
D6
D7
D0
D7
D2
D0
D1
D5
D4
D4
D3
CLKOUT
D7
D3
D1
D2
D5
D5
D6
D1
D6
D7
CLKOUT
D2
D7
D3
D0
D4
D8D6
D3
D5
D4
D2
D0
D6
D5
D0
INT_N
INT_N
D[0..7]
-CS_D12
-CS_D12
-RD_EVAL
D1
D2
D3
D4
INT_N
ZERO_WAIT
RESET_N
U2
74LS245
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
G
19
DIR
1
B1 18
B2 17
B3 16
B4 15
B5 14
B6 13
B7 12
B8 11
R4
4.7K
C3
0.1 C2
4.7TANT
+
D2
RED
R12
470
D3
RED
R13
470
D4
RED
R14
470
D5
RED
R15
470
S1
R7
10K R8 10K R9 10K R10 10K
R5
4.7K
R1
470
D1
GREEN
R11
1K
R16
1M
Y1 6MHz
C6
22P
C5
47P
J3
CON20A
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
J1
UP_CONN
VBUS
1
D-
2
D+
3
GND
4
SHIELD
5
R2
22 1%
R3
22 1%
C9
0.1 C10 0.1 C11 0.1 C12 0.1
C7
10 TANT
+
L1
Ferrite Bead
C1
4.7TANT
+
U4A
74LS05
1 2
U4B
74LS05
3 4
U4C
74LS05
5 6
U4D
74LS05
9 8
U4E
74LS05
11 10
C8
0.1
U6
74HCT273
D1
3
D2
4
D3
7
D4
8
D5
13
D6
14
D7
17
D8
18
CLK
11
CLR
1
Q1 2
Q2 5
Q3 6
Q4 9
Q5 12
Q6 15
Q7 16
Q8 19
L2
Ferrite Bead
C16
0.1
U1 PDIUSBD12
DATA0
1
DATA1
2
DATA2
3
DATA3
4
GND
5
DATA4
6
DATA5
7
DATA6
8
DATA7
9
ALE
10
CS_N
11
SUSPEND
12
CLKOUT
13
INT_N
14 RD_N 15
WR_N 16
DMREQ 17
DMACK_N 18
EOT_N 19
RESET_N 20
GL_N 21
XTAL1 22
XTAL2 23
VCC 24
D- 25
D+ 26
VOUT3.3 27
A0 28
U5
16L8
I1
1
I2
2
I3
3
I4
4
I5
5
I6
6
I7
7
I8
8
I9
9
I10
11
O1 19
O2 18
O3 17
O4 16
O5 15
O6 14
O7 13
O8 12
U3
74HCT244
1A1 2
1A2 4
1A3 6
1A4 8
2A1 11
2A2 13
2A3 15
2A4 17
1G 1
2G 19
1Y1
18
1Y2
16
1Y3
14
1Y4
12
2Y1
9
2Y2
7
2Y3
5
2Y4
3
S2
S3
S4
U4F
74LS05
13 12
C14
0.1
S5
BUSPOWERED
J2
DB25
1
3
5
7
9
11
13
15
17
19
21
23
25
2
4
6
8
10
12
14
16
18
20
22
24
C15
1000P
OSC1
N
1
G
4O5
V8
C13
470P,Ceramic

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Schematic for PDIUSBD12 ISA bridging board
D12-ISA-200 2.00
D12 ISA BRIDGING BOARD
A
1 1Tuesday, February 24, 1998
Title
Size DocumentNumber Rev
Date: Sheet of
VCC
VCC
VCC
VCC
VCC VCC
VCC
VCC
Shell to GND
DATA[0..7]
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7 DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
IRQ
DRQ
-DACK
ADDR[0..2]
ADDR2
ADDR1
ADDR0
ADDR0
ADDR1
ADDR2
IRQ5
IRQ7
DRQ1
DRQ3
-DACK1
-DACK3
IRQ7
IRQ5
DRQ1
-DACK1
DRQ3
-DACK3
T/C
RESET
-IOW
-IOR
T/C
-IOR
-IOW
RESET
-AD_EN
GND
GND
GND
+5V
+5V
-AD_EN
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
AEN
I/O CH CK
I/O CH RDY
ADDR19
ADDR18
ADDR17
ADDR16
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
IRQ2
-5V
DRQ2
-12V
ZERO_WAIT
+12V
-MEMW
-MEMR
-DACK0
CLOCK
IRQ6
IRQ4
IRQ3
-DACK2
ALE
OSC
ZERO_WAIT
J1
CONAT62
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
U1
74HCT688
P0
2P1
4P2
6P3
8P4
11 P5
13 P6
15 P7
17 Q0
3Q1
5Q2
7Q3
9Q4
12 Q5
14 Q6
16 Q7
18 G
1
P=Q 19
S1
SW DIP-8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
JP1
JP2
JP3
JP4
JP5
JP6
C1
0.1
C2
4.7u
+
C3
4.7u
+
C5
0.1
C4
0.1
R1
10K
J2
DB25
1
3
5
7
9
11
13
15
17
19
21
23
25
2
4
6
8
10
12
14
16
18
20
22
24
RP1
20K
C1
12 23 34 45 56 67 78

Interconnectivity Page 14 of 14
PDIUSBD12 Evaluation Board (PC Kit) User’s Manual REV. 2.1
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Philips Semiconductors - Asia Product Innovation Centre
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Bill of Materials
Bill of materials of the PDIUSBD12 evaluation board
Item Quantity Reference Part
1 2 C2,C1 4.7 TANT
2 8 C3,C8,C9,C10,C11,C12,C14,C16 0.1
3 1 C5 47P
4 1 C6 22P
5 1 C7 10 TANT
6 1 C13 470P, Ceramic
7 1 C15 1000P
8 1 D1 GREEN
9 4 D2,D3,D4,D5 RED
10 1 J1 UP_CONN
11 1 J2 DB25
12 1 J3 CON20A
13 2 L1,L2 Ferrite Bead
14 1 OSC1 Crystal Oscillator
15 5 R1,R12,R13,R14,R15 470
16 2 R2,R3 22 1%
17 2 R4,R5 4.7K
18 4 R7,R8,R9,R10 10K
19 1 R11 1K
20 1 R16 1M
21 4 S1,S2,S3,S4 SW PUSHBUTTON
22 1 S5 BUS POWERED
23 1 U1 PDIUSBD12
24 1 U2 74LS245
25 1 U3 74HCT244
26 1 U4 74LS05
27 1 U5 16L8
28 1 U6 74HCT273
29 1 Y1 6MHz
Bill of materials of the PDIUSBD12 ISA bridging board
Item Quantity Reference Part
1 3 C1,C4,C5 0.1
2 2 C2,C3 4.7u
3 6 JP1,JP2,JP3,JP4,JP5,JP6 JUMPER
4 1 J1 CON AT62
5 1 J2 DB25
6 1 RP1 20K
7 1 R1 10K
8 1 S1 SW DIP-8
9 1 U1 74HCT688