Pleora Technologies iPort NTx-Pro Installation instructions

NTx-Pro
Hardware Guide

...proven performance

These products are not intended for use in life support appliances, devices, or systems where malfunction of these products can reasonably
be expected to result in personal injury. Pleora Technologies Inc. (Pleora) customers using or selling these products for use in such applica-
tions do so at their own risk and agree to indemnify Pleora for any damages resulting from such improper use or sale.
Copyright © 2010 Pleora Technologies Inc. All information provided in this manual is believed to be accurate and reliable. No responsibility
is assumed by Pleora for its use. Pleora reserves the right to make changes to this information without notice. Redistribution of this manual
in whole or in part, by any means, is prohibited without obtaining prior permission from Pleora.
Document Number: EX001-010-0001, Version 1.0, 10/21/10

Contents
NTx-Pro: iPORT .........................................................................................................................3
Introduction ................................................................................................................................................. 3
Model Numbers .......................................................................................................................................................4
Summary of Features ..............................................................................................................................................5
Related Documents .................................................................................................................................................6
Connector Summary: OEM: NTx-Pro ......................................................................................7
NTx-Pro Connectors and LEDs ...............................................................................................................................8
Overview: Connector Names ...................................................................................................9
User Circuitry Connectors ........................................................................................................................... 9
Ethernet Connector ...............................................................................................................................................10
JTAG Connector ...................................................................................................................................................10
Power Connector ..................................................................................................................................................10
Connector: JTAG: 2x5-pin Header.........................................................................................11
Components .............................................................................................................................................. 11
JTAG Header Layout ............................................................................................................................................11
Connector: J2 JTAG Connector - Detail ................................................................................................................12
Connector: Ethernet................................................................................................................13
Components .............................................................................................................................................. 13
Pinouts ...................................................................................................................................................... 14
Connector: Power ...................................................................................................................15
Components .............................................................................................................................................. 15
Pinouts ...................................................................................................................................................... 15
Connector: User Circuitry: 2x 50-pin FFC/FPC ....................................................................17
Components .............................................................................................................................................. 17
Pinout Orientation .................................................................................................................................................17
2 x 50-Pin FFC/FPC Layout ...................................................................................................................... 18
Connector Names: J5 Connector - Detail ..............................................................................................................18
Connector Names: J4 Connector - Detail ..............................................................................................................20
Signal Names: (J5) 50-Pin FFC/FPC - Detail ........................................................................................................22
Signal Names: (J4) 50-Pin FFC/FPC - Detail ........................................................................................................23
FPGA Selection Pins .....................................................................................................................................24
Mechanical: OEM: NTx-Pro ....................................................................................................25
Notes for the Circuit Board ....................................................................................................................................28
Pixel Bus Timing .....................................................................................................................29
Overview ................................................................................................................................................... 29
Camera Link Signals ................................................................................................................................. 29
Case 1: FVAL and LVAL are Level-sensitive ........................................................................................................30
Case 2: FVAL and LVAL are Edge-sensitive ........................................................................................................30
Case 3: FVAL is Edge-sensitive and LVAL is Level-sensitive ...............................................................................30
Timing Values for All Cases ..................................................................................................................................31
Serial Port: Bulk Interface: UART, USRT, and I2C ...............................................................33
Bulk Interface: UART ................................................................................................................................ 33
Bulk Interface: USRT ................................................................................................................................ 33
Bulk Interface: I2C ..................................................................................................................................... 35
Read and Write Methods ......................................................................................................................................35
eBUS SDK Suite ............................................................................................................................................35

Serial Port: Standard-Bandwidth: UART...............................................................................37
Signals ...................................................................................................................................................... 37
Timing for UART ....................................................................................................................................... 37
Power Requirements...............................................................................................................39
Signal Names ............................................................................................................................................ 39
Input Power Signals ..............................................................................................................................................39
Output Power Signals ...........................................................................................................................................40
Power Consumption ..............................................................................................................................................41
User Circuitry Power .............................................................................................................................................41
Status LEDs: Overview...........................................................................................................43
Location of LEDs ....................................................................................................................................... 43
FPGA Configuration LED .......................................................................................................................... 43
Network Activity LED ................................................................................................................................. 44
Network Connection Speed LED .............................................................................................................. 44
FPGA Programming LED .......................................................................................................................... 44
Camera Link Pixel Bus Definitions ........................................................................................45
Pixel Bus Definitions ................................................................................................................................. 45
YUV Color Bit Assignments ..................................................................................................................................46

3
Copyright © 2010 Pleora Technologies Inc.
NTx-Pro: iPORT
Introduction
Pleora’s iPORT NTx-Pro IP engine is a compact, low-power video transmitter that gives OEMs and
systems integrators a fast, low-risk way to add real-time video connectivity to almost any system or
camera. It is ideal for performance-oriented applications in the military, medical, manufacturing, and
security sectors.
The IP engine efficiently converts video data to IP packets at GigE's full, 1-Gb/s throughput rate. The
packetized video is then sent with low, consistent latency over a GigE network or link to receiving
software or hardware.
The NTx-Pro IP engine complies fully with the GigE Vision®and GenICam™ standards, ensuring
seamless interoperation in multi-vendor deployments.
The IP engine leverages Ethernet’s flexible networking capabilities; for example, multicasting. It can be
connected through one or more switches to a range of other system elements – for example, cameras,
computers, displays, controllers and encoders – in meshed real-time video networks.
A sophisticated on-board PLC (Programmable Logic Controller) allows users to precisely measure,
synchronize, and control the operation of other elements.
In addition to the OEM board, the technology in the NTx-Pro IP engine is available in a comprehensive
IP (intellectual property) package that includes an IP core, the reference design for a board assembly, an
evaluation kit, and expert design review services.
As an element of Pleora’s networked video connectivity solutions, the iPORT NTx-Pro IP engine is
offered with field-proven PC software:
•theeBUSTM-SDK, a feature-rich toolkit that provides the building blocks needed to quickly
and easily design high-performance video applications that consume minimal CPU resources;
and,
•theAutoGEVTM XML generation tool, a unique GenICam XML management utility for
creating GenICam compliant devices.
For more information, visit http://www.pleora.com/products/ntx_pro.php

4 NTx-Pro: iPORT
Copyright © 2010 Pleora Technologies Inc.
Model Numbers
The iPORT NTx-Pro IP engine is offered with the model numbers shown in the illustration below.
PT 01 -PB 0IP 01 -32 B G
NTx-Pro Product Code
Pleora Technologies
Reserved
Speed
01: 1 GigE
Video Interface
PB: Pixel Bus
Protocol
G: GigE Vision Protocol
Package
B: OEM Board
DRAM Memory
32: 32 MBytes
Product Variant
Base Platform
IP: iPORT NTx-Pro
The standard OEM board assembly model for the NTx-Pro IP Engine is identified by part number
PT01-PB0IP01-32BG.

5
Copyright © 2010 Pleora Technologies Inc.
Summary of Features
The table below provides a summary of features and options available in the NTx-Pro IP engine.
NTx-Pro IP Engine Feature Summary
NTx-Pro
Hardware
User Circuitry Interface Pixel Bus
FPGA Altera Cyclone IIIa
EP3C40U484
Image Buffer 16-bit wide
32 MB DDR2 RAM
Persistent Memory 16-bit wide 8 MB parallel FLASH
Inputs/Outputs
GPIO Inputs 4 x 2.5V LVTTL
GPIO Outputs 4 x 2.5V LVTTL
Camera Control Outputs 4 x 3.3V LVTTL/LVCMOS
Programmable Logic Controller (PLC)
Pulse Generators (timers) 4
Rescaler (16-bit) 1
Delayer 1
General Purpose Counters 1
Input Debouncing Yes
Timestamp Generator Yes
Timestamp Trigger Yes
Software Controlled I/O 4
Host Interrupts Yes
Network
Gigabit Ethernet Yes
Zero-loss packet resend Yes
Ethernet Bandwidth 1 Gb/s
Unicast Yes
Multicast Yes
BOOTP Yes
DHCP Yes
Other Features
Serial Ports (UART) 1 x 2.5V LVTTL
1 x 3.3V LVTTL/LVCMOS
Bulk Interface (USRT, UART, I2C) 1 x 2.5V LVTTL
PHY Broadcom BCM5461
Power Connector 2-pin, 0.100” header
Ethernet Connector RJ45 with embedded magnetics
FPGA External Static Memory 16-bit wide 2 MB SRAM
Clock Generator Included
Boundary Scan Chain FPGA and PHY
Frame Grabber
Number of Data Channels 1 (Std)
Up to 4 (Opt)b

6 NTx-Pro: iPORT
Copyright © 2010 Pleora Technologies Inc.
Related Documents
The NTx-Pro Hardware Guide is complemented by these Pleora Technologies publications:
• iPORT Programmable Logic Controller Reference Guide
• iPORT eBUS SDK Quick Start Guide
Video Input LVTTL, LVCMOS
Progressive Scan Yes
Area Scan Yes
Line Scan Yes
Color RGBb
Bayer
YUV 4:2:2
Monochrome Yes
Data Output Formats Grayscale
Bayer
RGB
YUV 4:2:2
Pixel Depth (bits) 8, 10, 12, 14, 16, 24
32 (Opt)b
Pixel Clock Min: 1 MHz
Max: 90 MHz
Taps per Data Channel 1
2c
4 (Opt)b
Image Width (pixels)dMin: 8
Default: 640
Max: 16,376
Increment: 8
Image Height (pixels) Min: 1
Default: 480
Max: 16,383
Increment: 1
Windowing Yes
Decimation No
Tap Reconstruction Optionalb
Data Port Mapping Yes
Pixel Shifting Yes
Pixel Inversion Yes
Recording/Playback Yes
a. Refer to the Altera application note AN447 for information about interfacing Altera Cyclone 3 devices with 3.3V/
2.5V LVTTL/LVCMOS I/O systems (http://www.altera.com/literature/an/an447.pdf).
b. NRE or other charges may apply. Contact Pleora Technologies.
d. Default values in the XML file. Other values are possible.
NTx-Pro IP Engine Feature Summary
NTx-Pro