Pro-Log STD 7000 User manual

STD 7000
7801
808SA
Processor Card
USER'S MANUAL

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USER'S MANUAL
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7801 USER'S MANUAL
TABLE OF CONTENTS
SECTION
1
2
3
4
5
6
7
APPENDIX A
B
C
TITLE
INTRODUCTION
THE STD BUS
STD BUS Summary
7801 Pin Ut i 1i za t ion
Control
Bus Signal Table
Processor Status Codes
7801 SPECIFICATIONS
Power Requirements
Drive
Capability and Loading
Clock
Generator
Timing and Waveforms
Mechanical
Environmental
80SSA ARCHITECTURE AND INSTRUCTION SET
SOSSA Programming Model
SOSO/SOSSA/Z80 Compatibility
808SA vs S08S Characteristics
STO Instruction Mnemonics
Instruction Cross-Reference Table
SOSSA Instruction Set
Interrupts
PROGRAM INSTRUCTION TIMING
Introduction
WAIT States
DMA Mode
Instruction Timing Table
Programmed Timing Example
MEMORY AND I/O MAPPING AND CONTROL
Memory Addressing
12K-Byte Onboard
Memory
Input/Output Port Addressing
Onboard Serial I/O Lines
PROGRAM AND HARDWARE DEBUGGING
Microprocessor Logic State Analysis
Instruction Dia9no~tic Tables
M82S System Analyzer
7801 STRAPPING OPTIONS
SCHEMATIC AND ASSEMBLY DIAGRAMS
MS2S SYSTEM ANALYZER DATA SHEET
PRO-LOG
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SECTION ONE
PRODUCT OVERVIEW
SOSSA PROCESSOR CARD
This card combines a buffered and fully expandable
808SA microprocessor withonboard RAM and
PROM sockets.
The
7801 includes 1K byte of RAM with sockets for
up to 4K. and sockets for up to 8K bytes of ROM or
EPROM. An STO BUS system using the 7801 card
can be expanded to full 808SA
memory and I/O':
capability The 7801 STO BUS interface may be
disabled
for OMA •
FEATURES
• 80SSA Processor
• 4096 bytes RAM capacity onboard
• 1024 bytes RAM included (211 4L type)
• 8192 bytes ROM capacity onboard (2716 type)
• 3 State Address, Data, Control Buses
•
• Power-on·reset or pushbutton reset input
• Five interrupts
• Serial 1/0 lines
• All lC~s.-socket.ct
• Single +5V operation
.7801: 6_25 MHz crystal, 320ns time states
.7801-1: 6_ 144MHz crystal, 325.5ns time states
• External clock input option
.. M.RO-
INTRa"
IUMO-
WAITRO'
CNTRl.
(IXT CLKI
J1
INTIRRUPT
AND SIR.AL.
',0 ACCESS
",OCIISOR
IOI5A
DATA IUS
ADORIIS
loSTATI
IUS IU,.,'RS
loSTATt
IUS IU"U
,.
7101
SHADING INOICATIS SOCKETS ONU
'INDICATES ACTIVI LOW l.OGIC
FIGURE ONE: 7801 BLOCK DIAGRAM
DATA IUS
(00007)
AOORISS IUS
(AOoA1S'
~l..o<!.\IC."
MIMRO-
lORa-
WR'
MCSYNC-
INTAK'
IIUSAIC'
STATUS O'
STATUS l'
STSRn_TO
M'MlX'
10UIt·
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FOAM NO. 101905

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SECTION TWO - THE STO BUS
The STO BUS standardizes the physical and electrical aspects of modular a-bit
microprocessor card systems, providing a dedicated, orderly interconnect scheme.
The STO BUS is dedicated to internal communication and power distribution between
cards, with all external communication made via I/O connectors which are suitable
to the app1 ication. The standardized pinout and 56-pin connector lends itself
to a bussed motherboard that allows any card to work in any slot.
As the system processor and primary system control card, the 7801 is responsible
for maintaining the signal functionality defined by the STO BUS standard.
A complete copy of the STO BUS standard is contained in the SERIES 7000 STO BUS
TECHNICAL MANUAL, available from Pro Log Corporation, 2411 Garden Road, Monterey,
California 93940.
STO BUS Summary
The 56-pin STO BUS is organized into five functional groups of backplane signals:
1. Logic Power
Bus pins
1-6
2. Oata
Bus
pins
7-14
3. Address
Bus pins
15-30
4.
Control Bus pins
31-52
5.
Aux i 1ary Power pins
53-56
Figure , shows the organization and pinout of the STO BUS with mnemonic function
and signal flow relative to the 7801 Processor card:
COMPONENT SIDE CIRCUIT SIDE
PIN
MNEMONIC
SIGNAL
DESCRIPTION PIN MNEMONIC
SIGNAL
DESCRIPTION
FLOW FLOW
LOGIC
1
·SV In
+S Volts DC (Bussed) 2
·SV
In
·S Volts DC Bussed)
POWER 3
G~O
In Digital Ground (Bussed) 4 GNO In Digital Grol.;~C Bussed)
BUS 5 -5V -S Volts DC 6 -5V -5 Volts DC
7
03 InlOut
Low Order Data Bus 8
07
InlOut
High Order ::Ja:a Bus
DATA
9
02 InlOut
Low Order Data Bus
10
06
InlOut
High Order Ca:a Bus
BUS
11 01 InlOut
Low Order Data Bus 12
OS
InlOut
High Order Cata Bus
13
DO
InlOut Low Order Data Bus
14 04 InlOut
High Order Ca~a Bus
15
A7
Out
Low Order Address Bus
16
A15
Out
High Order A-:dress Bus
17
A6
Out
Low Order Address Bus
18
Al ..
Out
High Order Ao:lo:lress Bus
19
AS
Out
Low Order Address Bus
20
A13
Out
High Order AIjClress Bus
ADDRESS
21
A4
Out
Low Order Address Bus
22
A12 Out
High Order AOdress Bus
BUS
23
A3
Out
Low Order Address Bus
24
All
Out
High Order Address Bus
25
A2
Out
Low Order Address Bus
26
A10 Out High
Order Address Bus
27
Al Out
Low Order Address Bus
28
A9
Out
High Order Address Bus
29
AO
Out
Low Order Address Bus
30
A8 Out
High Order Adljress Bus
31
WR·
Out
Write to Memory or I/O
32
RD·
Out
Read to Memory or I. 0
33
lORa·
Out
I/O Address Select
34
MEMRO-
Out
Memory Address Select
35
10EXp·
Out
110 ExpanSion
36
MEMEX·
'Out
Memory ExpanSIon
37
REFRESH· Refresh
Timing
38
MCSYNC·
Out
CPU MaChIne Cycle Sync
CONTROL
39
STATUS 1·
Out
CPU Status
'.
40
STATUS O·
Out CPU Status
BUS
41
BUSAK"
Out
Bus Acknowledge
42
BUSRO·
In Bus ReQuest
43
INTAKo
Out
Interrupt Acknowledge
44
INTRO"
In Interrupt ReOuest
45
WAITRO" In Walt ReQuest
46
NMIRO'
In
Non-MaskaOI~ Interrupt
47 SYSRESET"
Out
System Reset 48
PBRESET' In Push Button
~eset
49
CLOCK"
Out
Clock from Processor 50
CNTRl·
In AUX TimIng
51
peo
Out
Priority Chain Out
52
PCI In PriorIty Cha,'"
In
POWER
53
AUXGNO
AUX Ground (BUSSed)
54
AUXGND
AUX Grouna 8'.Jssea)
BUS
55
AUX+V
AUX POSitive (-12 Volts DC) 56
AUX-V
AUX NegatIve -'2 Volts DC,
·Low L.evet Active Indicator
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STO BUS Pin Utilization by 7801
Since the STO BUS standard does not specify timing or require that all available
pins be used, the timing and signal allocation assumes many of the characteristics
of the microprocessor type used. The characteristics of the 7801 are dictated by
its 8085A microprocessor, with LSTTL buffering added to enhance the card's drive
capability., The b~ffers decrease memory and I/O access time slightly.
The allocation of STO BUS lines for the 7801 is given below.
1. Logic Power Bus:
+5V (pins 1,2) and Logic Ground (Pins 3,4) supply operating
power to the 7801. Pins 5 and 6 are open.
2. Data Bus:
Pins 7 through 14 form an 8-bit bidirectional 3-state data bus as
shown in Figure 2 High level active data flows between the 7801 and its
peripheral cards over this bus. When the 7801 fetches data from its onboard
memory sockets, this data also appears on the STD Data Bus.
With
the exception of Direct Memory Access (DMA) operations, the 7801 controls the
direction of data flow with its I1EHRQ,r" 10RQi" RD"" WR'':, and INTAK~r, control
signal outputs~ Peripheral cards are required to release the data bus to the
high impedance state except when addressed and directed to drive the'data bus
by the 7801. Note that the low-order address bits (AO-A7) are multiplexed on the
Data Bus.; AO-A7 appear on 00-07 while MCSYNC* is active. The 7801 releases the
Data Bus when BUSAK* is active in response to BUSRQ*, as in DMA operations.
3. Address Bus: Pins 15 through 30 form a l6-bit 3-state address bus as shown in
Figure 2 . The 7801 drives high level active l6-bit memory addresses over
these lines, and 8-bit I/O port addresses over the eight low-order address
1 ines (AO through A7 on pins 15, 17, 19, 21, 23, 25, 27 and 29).
The 7801 releases the Address Bus when BUSAK* is active in response to BUSRQ~~,
as in DMA operations.
4. Control Bus: Pins 31 through 52 provide control signals for memory, I/O,
interrupt, and fundamental system operations. Figure 3 summarizes these
signals and shows how they are derived from 8085A signals.
The 7801 releases the Control Bus during BUSAK* in response to BUSRQ*, except
for the following output signals: MEHEX,;',, 10EXPi" BUSAK;'" CLOCK'~', PCO.
5. Auxilary Power Bus: Pins 53 through 56 are not used by the 7801 and are
electrically openc
The 7801' meets all of the signal requirements of the STD BUS standard. Detailed
timing information and specifications are in Section 3. I
PRO-LOG
CORPORATION
FORM NO. 101905
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:MNEMOt-J IC
PIN
IN/OUT
FUNCTION
IHOW DERIVED, 808SA
NAME
iWR
!
31
Out#
Write to memory or I/O I
[WR1;]
:RD*
I
32
Out#
Read from memory or I/O
[RD*]
IORQ1
33
OUT#
AO-A7 hold valid I/O address
[IO/M*]*
MEMRQ";
I
34
OUT#
AO-A15 hold valid memory [IO/M*]
i
address
,
I
10EXP*
35
OUT
I/O expans~on control User-removabl~
ground
MEMEX*
36
OUT
Memory expansion control User-removable ground
REFRESH~':
37
-: (Not used) I E1ect
rica 11y open
MCSYNCr;
38
OUT#
One transition per machine
[ALE] *
cycle; undecoded status
STATUS
1*
39
OUT#
Undecoded status;
Note 1
[S 1] *
STATUS
0".
40 OUT#
ndecoded status, Note 1
[SO] *
..
I
BUSAK*
:
41
OUT Acknowledges BUSRQ*
i [HLDA] *
I
;BUSRQ*
42 IN
Bus request (DMA); synchronous I [HOLD]*
.
processor halt and 3-state l
! !
;
driver disable
I
..... - -- ... ---- . ..---
iI NTAKr~
:
43
OUT# ! Acknow 1edges I NTRQ* and rep1 ace~[ I NTA;'~]
e i
(MEMRQ* . RD*) to read
i ! :
interrupt vector
IINTRQ*
I 44
:
IN
Maskable interrupt request
[I NTR]'':
WAITRQ*
45
IN Synchronous processor ha 1t [ROll ~
NMIRQ* 46
IN Nonmaskab1e interrupt request
j [TRAP] 1;
SYSRESET~':
! 47
OUT# System power-on and pushbutton ;[RST]*
reset one-shot output
I
PBRESET~I;
48
IN Pushbutton reset input
:[R~': ]
CLOCK;':
49
OUT Time State tlock
(1 /2 cry s ta 1 I
[CLOCK] * -
user optional
,-
frequency) i jumper connection
CNTRL~';
50
IN
External
clock input (2 times
:~1
- user optional
jumper
Time State Clock frequency) 1
connection
i --i
-
~
IPC I /PCO
52/51
IN/OUT Priority
chain
INote ~
*
Low 1eve1 active
# Output
buffer disabled when BUSAK* active
[]
Denotes equivalent Bo8SA signal
name
NOTES:
t.
See Figure
4
for status
information.
2. Trace on 7801
connects PCI
to PCO to
maintain chain continuity.
FIGURE
3 :
7801 CONTROL BUS SIGNALS
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7801 Processor Status: MCSYNC*, STATUS 0*, STATUS 1* Signals
MCSYNC*, STATUS 0*, and STATVS 1* signals provide encoded status information
which is peculiar to the 808SA microprocessor. These signals are useful for
displaying processor status in logic sign~l analyzers, and can be used to drive
certain peripheral chips and systems designed to work with the 808SA specifically.
The use of these signals is not recommended in systems where microprocessor
device-type independence is a design goal.
MCSYNC* serves a dual function. Its leading edge denotes the approximate start
of a machine cycle (Section 3 ). Counting the MCSYNC* transitions allows a
logic signal analyzer to select a specific machine cycle within a mUlti-cycle
instruction for analysis.
The lagging edge of MCSYNC* occurs when a stable memory line address or I/O port
address is present on the sro Data Bus. The 808SA device mu1.tiplexes jots low order
address lines (AO-A7) during time state TI; -tne address information is followed by
data in subseq~ent time states within the machine ~ycle. The lagging (rising) edge
of MCSYNC* is used on the 7801 to latch thp low order address.
MCSYNC* is equivalent to the 80SSA's ALE (Address Latch Enable) output signal.
STATUS 0* and STATUS 1", can be decoded externa 11 y to i dent i fy the type of
machine cycle in progress as shown in Figure 4:
SEE NOTE I
MACHINE CYCLE TYPE :STATUS 0*
STATUS
I'~ ,MEMRQ'" IORQi;! RDi, ; It/R,'t \ I NTAKi:
2
3
NOTES: I.
2.
3.
4.
I Read instruction opcode 0 o
I
Read memory except opcode 1
Wr i te in memory
Acknowledge INTRQ*
Acknowl edge NM I RQ": and
interrupts S.5,6.5,7.5
Bus idle during ADP (Add
to H,L pair) instruction
HALT instruction
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FIGURE 4: MACHINE CYCLE STATUS SIGNALS
I 0 I 1 j 0 I 1 I 1
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1
1
!
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1,
I
*low active: Active = a
Inactive = 1
o
The states shown for MEMRQ": and fORQi, during interrupt acknowledge cycles are
those produced by the 808SA dev ice. For the ear lie r 8085, the MEMRQi: and 10RQ":
states are reversed.
The Data Bus is idle during the second and third machine cycles machine cycles
for the ADP ins t ruc t ion (I rrte1 mnemon i cis DAD). No MCSYNC* CAlE~") signa 1 is
generated during these cycles. ((808SA only).
Processor pins 10/M*, RD*, WR* are in the high impedance state.
Timing for STATUS 0* and STATUS 1* is similar to Address Bus timing (Section 3).
For additional information, refer to the 808SA manufacturer's literature.
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SECTION 3 - 7801 SPECIFICATIONS
Power Requirements
! RECOMMENDED OPERATING LIMITS i
ABSOLUTE NONOPERATING LIMITS I
MIN MAX UNITS
I
PARAMETER I MIN TVP MAX
0
5.50
I
Volts
!
Vcc (Note 1) 4.75 5.00 5.25 I
!
Ampere
!
lice (Note 2) : 11.00 1.40 I
FIGURE 5: 7801 POWER SUPPLY SPECIFICATION
NOTES: 1. In order to guarantee correct operation, the
following power supply considerations apply:
a. Vcc rise must be monotonic, rising from
+0.50 Volt to +4.75 Volts in 10 ms or
less.
b. If Vcc drops below +4.75 Volts at any
time it must be returned to less than
+0.50 Volt before restoration to the
specified operating range.
2. Icc specification assumes that all EPROM and
RAM sockets on the 7801 are loaded. Subtract
75 rnA per 2716 EPROM and SOmA per 2114L RAM
for each device not used. (typical values)
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Both the 8085A and 2114L devices require 10 milliseconds minimum after initial
power-on for stabilization of internal bias oscillators. The 780l's power-on
reset one-shot provides adequate stabilization delay, only if Vcc risetime is
less than 10 milliseconds.
Drive Capability and Loading
The 780)IS
STD BUS Edge Connector Pin List (Figure 6 ) and Serial I/O and
Interrupt Socket Jl (Figure 7 ) give input loading and output drive capability
in LSTTL loads as defined by the SERIES 7000 TECHNICAL MANUAL.
In general, input lines and disabled 3-state outputs present 5 LSTIL loads maximum
(one LSTTL or MOS input plus 4.7K pullup resistor). Output 1 ines can drive
a minimum of 50 LSTIL loads. Pins which are unspecified in Figures 6 and 7
are electrically open.
Exceptions to· the general loading rules are:
PRO-LOG
FORM NO. 101905
a. WAITRQ* input, which is 15 LSTTL loads.
b. PBRESET* input, which is 1 uF typical in
parallel with 2 LSTTL loads •
c. CLOCK* output, which can drive 10 LSTTL loads.
d. PCI and PCO, which are connected to each other but to nothing
else on the 7801.
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