RCA Spectra 70 Installation guide

5iFlE'_
I
RADIO CORPORATION OF AMERICA • ELECTRONIC DATA PROCESSING
~RADIO
SYSTEM
7C25i
TRAINING MANUAL
CORPORATION
70-25-801 o F
AMERICA

The information contained herein
is subject to change without notice.
Revisions may be issued to advise
of such changes and/or additions.
First Printing: December, 1964
Second Printing: January, 1965

TABLE OF CONTENTS
Page
General Description . . . . • • • • • . . . • . • . • • . • . • . . • • • . • • • • • . • . . • • • • . • . . . . • • . • . . 1
High-Speed Memory • • . • . . . • • • • . • . • • . • . • . • . • . • . . • • • . • • . • • • . • • • • • • . . . • • • • • • 3
Introduction .••..•.•••...•.•....•.•.••.•..•••..•..••••••..••••••.•.. 3
HSM Addressing ..••••••..•.•••••.••.••.•.•.•.•..•.••.•..••.•••...•.. 3
Hexadecimal Numbering System • . . • • • . • . . • . • . . • • • . • . • • • • . • • • • . . • • • . . • • • • • • 4
Exercise .••••••......•.•.•.•.••••••.•.•.••••••.•••••••••..•.•..••• 5
Data and Instruction Format ........•.•.••.•••••.•.•..•.•••••..•.•.••••...•• 6
Data Formats . . . . • . • . • . • . • • • • • . • . • • . • • • • • • • • • • • • . • . • • • • • • • • • • . • • • • . • 6
Unpacked Format .•.•..•••••••••.•.•••••••.••••.••••.••••.••.••••.••• 6
Edited Format .•.•...••••••......•..•..•••..•.•..•.•.•••.•.•.••.•••• 6
Machine Instruction Format •.•...••.••••••••...••.••.•.••.•.•.••....•••• 7
Exercise .•••.•..•.•..••..••••••••••••.••••••••.•..•.••••••..••••.• 7
Interrupt .••..•.•..•••.•.••.••••.••••.•.....••.•••..••••••.•.••.••.•.• 9
Introduction ••.•.•.•..•••....•.•.•..•..•..•.•.....••.•.••..••••..•.. 9
Programming States. . . • . • • • . • • . • . • . • . • . • • • . • • • • . • • . • . • • . • • • • • • . • • • • • • • 9
Processing State . . . . . . . . • . . . . . . • . . . . • • • . • . • . . • . . . . . . . . . . . • . . . . . . . • . • • 9
Interrupt State • . • . • . • • • . . . • . . . . . . • • • • • • . • . • . . • • . • • . . • • • • . • • . . . • • • • • . • 9
Types of Interrupt . • • . • • . . . . . . . • . • . • . . . . • . . . . . . . . . . . • • • • • • . • . . • . . • . . . • 9
I/O Interrupt •. . . • • • . . • • • • • • . • . • . • • . • • • • • . . • . • . . . . . . • • . • . • . • . • . . • . • • 9
Operation Code Trap .•...•••••.•.•.•••••••........•..••.....•........• 10
Arithmetic Overflow and Divide Exception . . . . . • . • . . . . . • . • . . . . . . . • . . . . . . . . . . . . 10
Elapsed Timer Interrupt. . . . . . • . • . . . • . . . . . . . . . • . • . . . . • . . . • • • • • . . . . . . . • . . 11
Inhibiting Interrupt •••..•••.••.•..•.•..••....•...•....•.•••......•.... 11
Exercise ...•....•.............•.................•......•...•....•. 11
Summary of Interrupt Logic ..•..•..•.•...•...•.•......••.•....•..•...... 12
Elapsed Time Clock. • • • • . • • • • • • • . • • • . • • • . . • . • . • . • • • . • • • . • • • • • • . . . • . • • • • . . 13
Introduction to the RCA 70/25 Assembly Language . ..• • • • . • . • • • . • . • • • . • • • . • . . • • . • • • 14
Format Requirements •••.•.•••.•.•••.•.•••...•••.••••.•••.••.•..••••.. 14
Addressing . . • • • • . • • . • • • • . • • • . . • • • . • . • . • • • • • . • . . • . • • • . • • • • • • . • • • . • • • 14
Self-Defining Values •••••.••••.•••••.•.•.•••.••.••••.•••••••••.•..•.•. 16
Expressions • . • • • . • . • • • • • • • . . • • • . . . • . • . • . • . • • • • • . . • . • • • • • • • • • . • • • • . . 16
Implied Lengths ..........•.•.•.....•..•...•.•......•.•.•...•.....•.• 17
Assembler Controlling Codes •.••.•••..••••••••.•...•••.••••...••••..•••. 17
Define Storage (DS) .•.•.•.••..•.•.•••••••.•.••••.••••••••.•..•.•.•• 18
Origin Code (ORG) • . • . . . • . • . • . . • • . • • . . . . . . . • • . . • . • . • • . . • . . • . . . . . . • • 18
Constant Definition (DC) ...•.•.•...•.••.••.•.....••... 0 • • • • • • • • • • • • • • 18
Program Linking Codes (ENTRY and EXTRH) .•.•.•........ 0 • • • • • • • • • • • • • • • 19
Run and Segment Controlling Codes (START, END, CSECT) . . . . . . . . . . . . . . . . • . . 20
Equate Code (EQU) ....•....•.........•........•..•.....•.......••• 21
Base Register Controlling Codes (USING, DROP) .........•.................. 21
Extended Mnemonic Instructions . • . . . • . • . • . • • . . • . • . . . . . . . . . . . • . . • • . • . . . • 21
Exercise .....•.•.•.•.......•...•......•.........•................. 22

TABLE OF CONTENTS (Continued)
Instruction Complement
Data Movement Instructions
Move Character (MVC)
Exercises ....
Packing and Unpacking Data (PACK and UNPK).
Exercises .....
Decimal Arithmetic Instructions
Decimal Add (AP) and Subtract (SP)
Decimal Multiply (MP) . . . . . . .
Decimal Divide (DP) ........ .
Exercises ............. .
Data Editing Instruction (ED)
Examples ..
Exercises ...... .
Comparison and Branching Instructions
Compare Logical (C LC) .
Compare Decimal (CP)
Branch on Condition (BC)
Branch and Link (BAL) .
Branch on Count (BCT) .
Set P2 Register (STP2) .
Exercises
Load and Store Instructions
Load Multiple (LM) .
Store Multiple (STM) . .
Binary Arithmetic Instructions .
Binary Add (AB) and Subtract (SB) .
Exercise ....
Logical Instructions
Logical And (NC) .
Logical Or (OC)
Exclusive Or (XC)
Use of Logicals
Test Under Mask Instruction (TM). .
Data Translation, Translate (TR)
InputlOutput .. . . . . . . . . . .
Introduction. . . . . . . . . .
Read Instructions (RDF) and (RDR)
Writing Data (WR) and (WRE) .
Controlling Peripheral Devices
Error Recognition . . . . . . .
Flow Chart of Basic II 0 Logic. .
Standard Device Byte .....
Sensing Exceptional Conditions
Peripheral Unit Sense Bytes
Summary of 1/0 Logic ..
Example of 110 Coding .
Exercise ........ .
ii
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FOREWORD
70/25 TRAINING MANUAL
This manual is designed for use in formal training programs which
mayvaryinlengthfrom about 15 classroom hours (with appropriate
outside assignments and work sessions) to 45 hours or more,
depending upon the experience of the student. People with good and
recent programming experience may find the text helpful in
self-study.
Principal references which should be used in either formal or
self-study situations are:
1. 70/25 Assembly Manual
2. 70/25 System Reference Manual
iii

GENERAL DESCRIPTION
INTRODUCTION
The RCA 70/25 is the intermediate member of the
Spectra 70 Data Processing series. It is a powerful
small-to-medium scale data processor. Equipped
with communications gear, the 70/25 has high-speed,
high-volume message switching or remote processing
capabilitie s.
70/25 PROCESSOR
The RCA 70/25 Processor is a general-purpose,
stored program, digital machine that includes High-
Speed Magnetic Core Memory, Program Control, and
the appropriate Input/Output logic for the Spectra 70
Systems standard Interface Unit.
HIGH-SPEED MEMORY
The High-Speed Memory (HSM) is a magnetic core
device that provides storage and work area for pro-
grams and data. The memory capacity is either
16,384, 32,768, or 65,536 bytes. A byte is the
smallest addressable unit in memory, and consists
of eight information bits and a parity bit. Each byte
location maybe accessed with a 16-bit binary address
consisting of two parts: a displacement carried in an
instruction, and a base address stored in a general
register. The sum of the two form an effective mem-
0ry address.
The Memory Cycle is 1. 5 microseconds, which is
the time it takes to transfer four bytes from HSM to
a memory register and to regenerate the bytes
in storage.
PROGRAM CONTROL
The Program Control executes the instructions of
the program stored in the HSM. An instruction can
be interpreted and executed by the Program Control
only after it has been brought out of HSM. The
process of interpreting and placing the components
of the instruction in the proper registers is called
staticizing. An instruction is first staticized and
then executed by the Program Control logic.
AUTOMATIC INTERRUPT
The RCA 70/25 can staticize and execute all instruc-
tions in one of two programming states; the Proces-
sing State and the Interrupt State. The Processing;
State is the normal mode of operation. A condition
that causes interrupt will transfer the computer to
the Interrupt State. Interrupt is mechanized in the
70/25 hardware. It automatically senses the pres-
ence of interrupt conditions, and transfers control to
the Interrupt State.
INSTRUCTION COMPLEMENT
The RCA 70/25 Order Code consists of thirty-one
instructions which can be divided into four classeso
1. DATA HANDLING
The data-handling instructions allow for the move-
ment of data fields within HSM. Data may be moved
without changing format or it can be packed, unpacked
or edited for printing during the movement. A Trans-
late instruction facilitates code conversion and data
validation.
2. ARITHMETIC INSTRUCTIONS
This set includes Decimal Add, Subtract, Multiply
and Divide instructions, as well as Binary Add and
Subtract operations. It also incorporates the ability
to perform Boolean Operations on bit structures.
3. DECISION AND CONTROL
The decision and control instructions allow for the
comparing of both Decimal and Binary fields, and
the branching to a location in HSM according to a
Condition Code Indicator. Also included are Branch
and Link and Branch-Qn-Count instructions that
simplify subroutine linkage, and control of iterative
coding.
4. INPUT/OUTPUT
Read and Write instructions transfer data between
the processor and all peripheral equipment on-line
to the 70/25. Included are the necessary instructions
to control the devices and to recognize and recover
from error conditions.
INSTRUCTION FORMAT
There are three basic instruction formats in the
70/25; six-byte, four-byte, and a two-byte instruc-
tion. The first byte of every instruction is the
operation code. Depending on the instruction, the
remaining byte~ refer to field lengths, register and
storage addresses, or contain peripheral device
identification.
DATA FORMAT
The basic unit of storage is the byte, which can

represent, in the unpacked format, one alphabetic
or numeric character, or two numeric digits in the
packed format. Data is represented in HSM in the
Extended Binary-Coded-Decimal Interchange Code
(EBCDIC) .
INPUT /OUTPUT
The RCA 70/25 communicates with peripheral
devices through eight I/O channels.
2
Each peripheral device contains its own control
electronics in order to transmit to the processor
the status of the device, and any error conditions
generated by an I/O command.
Each channel is a separate simultaneous mode, allow-
ing execution overlap with other channels and the
processor. An II 0 termination interrupt is included
in the system to facilitate efficient use of these
powerful overlap capabilities.

HIGH-SPEED MEMORY
INTRODUCTION
The RCA 70/25 magnetic core High-Speed Memory
(HSM) may consist of one, two or four memory
planes. Each plane contains 16,384(10) byte locations
(4 x 64 x 64 bytes). The byte is the smallest addres-
sable unit in memory, and is made up of eight
information bits and a parity bit.
BYTE
Bit Identification
P 27 26 25 24 23
22
21
20
Bit (X = 0 or 1) X X X X X X X X X
Four bytes of HSM may be transferred to a memory
register and regenerated in memory within 1.5
microseconds. These four bytes are moved side by
side or in parallel.
MEMORY REGISTER
0
1
HSM
2
3
To save processing time, the memory access hard-
ware moves instructions and data in four byte units
whenever possible, returning to a byte after byte
or serial transfer when necessary to stay within
limits defined by a specific operation. These four
byte units are called words. The first four bytes
of memory, locations 0, 1, 2, and 3, constitute the
first word. The second begins with location 4, and
the third with 8, etc. Even Word boundary is the
term used to describe the initial byte of each word;
locations 0, 4, 8, etc. The addresses contained in
several 70/25 instructions must begin at even-word
boundaries (see page 41).
HSM ADDRESSING
The address of each byte location is expressed as
a binary number. Sixteen bits are required to ad-
dress the highest location of a four plane system
(65,536).
3
Examples:
BINARY ADDRESS
215
214
2
13
212
211
2
10
29 28
27
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 1 0
0 0 0 0 1 1 1 1 1
0 1 0 0 0 0 0 0 1
1 1 1 1 1 1 1 1 1
26 25
24
23
0 0 1 1
1 1 0 1
1 1 0 1
1 1 1 1
0 0 0 0
1 1 1 1
22 21 20
0 0 1
1 0 1
1 1 1
1 1 I 0
0 o I0
1 1 1
DECIMAL
EQUIVALENT
25
109
879
4.094
16.512
65,535
The first example shows the binary representation
of HSM location 25. The conversion to decimal re-
quires the adding of the 2n value of all bits that are
one (1).
BINARY
DECIMAL EQUIVALENT
20 1
23 8
24
16
-25
Within the 70/25 instruction format two bytes, 16
bits, are allocated for each memory address.
1 st ADDRESS 2nd ADDRESS
An address is divided into two parts: (1) a displace-
ment of 12 bits contained in the instruction, and (2)
a base address which is pre-stored in one of the
fifteen General Registers.
The most significant four bits of each address, the
Bl or B2 fields, designate the General Register
containing the associated base address.
B FIELD
0001 (2) - General Register 1
1000(2) - General Register 8
1111(2) -
General- Register 15
0000(2) - No base address
Assume that General Register One contains
40,000(10) .

OP M
147 (16)
F(16)
0001(2) 4000(10)
When an instruction is staticized the displacement
is added to the base address. The absolute sum of
the two is called the effective address, and is the
address value actually used in execution. In the
example above,
the displacement,
is added to the base address in
register 1,
resulting in an effective address
of
4000(10)
40000(10)
44000(10)
This technique makes it unnecessary to carry lengthy
addresses within instructions. Each displacement
is a fixed length of 12 bits. However, since the 16
least significant bits of general registers may be used
for base address values, it is possible to access
locations which require 13, 14, 15, or 16 bit
addresses.
This addressing concept is a necessary feature in
larger members of the Spectra 70 series where ad-
dresses may exceed 16-bit lengths.
The maximum value of a displacement is 4095(10)'
r-,--
2,048 1.024
512 256
128
211 2
10
29 28 27
r----
1 1 1 1 1
. --
64 32 16
8 4 2
26 25
24 23 22 21
1 1 1 1 1 1
1
DECIMAL VALUE
-~
2° POWER OF TWO
1
BINARY ADDRESS
2
4
8
16
32
64
128
256
512
1024
2048
4095
When addressing locations between 0000(10) and
4095(10)' no base address need be associated with
a displacement. The 12-bit address carried in the
D1 or D2 fields becomes a direct address when the
value 0000(2) is placed in the corresponding B1 and
B2 fields.
HEXADECIMAL NUMBERING SYSTEM
The binary system, although efficient for the 70/25,
is not a convenient notation for the programmer. The
hexadecimal numbering system, which operates on
the base sixteen, is a convenient method to express
the binary representation of HSM addresses.
The decimal system is a numbering system based
upon the number ten. It uses ten single symbols
(0-9) to represent the basic digits. By a system of
positional notation that indicates multiplication by
4
powers of the base, any value can be expressed. The
hexadecimal system requires sixteen symbols to ex-
press its basic digits. The alphabetic letters A
through F have been assigned to represent the decimal
values 10 through 15 in order to maintain single
symbols for the digital values of the hexadecimal
system.
Each symbol in the hexadecimal system can be
expressed by four bits in the binary system. There-
fore, two hexadecimal marks are required to repre-
sent a byte, and four hexadecimal marks can express
an HSM address.
HEXADECIMAL
BINARY
DECIMAL
0
0000
0
1 0001 1
2
0010
2
3 0011 3
4
0100
4
5 0101 5
6
0110
6
7 0111 7
8 1000
8
9
1001
9
A
1010
10
B 1011 11
C
1100 12
D 1101
I
13
E
1110
I
14
F
1111
I
15
Conversion of Hexadecimal to Decimal
The decimal number 472 represents:
4 x 100 + 7 x 10 + 2 x 1 = (472)10
The binary number (101101)2 can be converted
to its decimal equivalence by:
1 x 25 + 0 x 24 + 1 x 23 + 1 x 22 + 0 x
21
32 + 0 + 8 + 4 + 0
+ 1 x 20
+ 1 = (45)10
A
hexadecimal number is converted to a decimal
value by multiplying the hexadecimal characters
by the appropriate value of 1G
n.

Examples:
1. Convert (1024)16 to Decimal
1 x 16
3 + 0 x
16
2 + 2 x
16
1 + 4 x
16
0
4096 + o + 32 + 4 = (4132)10
2. Convert (3AFj16 to Decimal
3 x 16
2 +
10 x 16
1 +
15 x 16
0
3 x 256 +
10 x 16 + 15 x 1
768 +
160 + 15 = (943)10
The first example shows the hexadecimal address
(I024h6 which has a decimal value of (4132)10. The
actual machine (binary) address is:
0001000000100100
Each hexadecimal character can be represented by
four bits. Therefore, hexadecimal is converted to
binary by replacing each hexadecimal character with
its binary value.
(0001000000100100)2 = 4096 + 32 + 4 (4132)10
The second example shows that the hexadecimal ad-
dress 3AF has a decimal value of 943.
Exercise:
1. A byte consists of __ information bits and
a ___ bit, and is the ___ addressable unit in
the 70/25 HSM.
5
2. An effective HSM address is the absolute sum
of a and a ___ _
3. Base address values are stored in . The
___ and! or fields of an instruction
specify which base address will be used to com-
pute an effective address.
4. The decimal value of a displacement may not
exceed ___ _
5. Convert following hexadecimal numbers to
binary:
a. A4E8(16)
b. E82C(16)
c. 3D71(16)
6. Convert following hexadecimal numbers to
decimal:
a. B5F9(16)
b. F93D(16)
7. Convert following binary numbers to hexa-
decimal:
a. 1100011000001010(2)
b. 0000101001001110(2)
c. 0010110001100000(2)
8. Convert following decimal numbers to hexa-
decimal:
a. 55067(10)
b. 7007(10)

DATA AND INSTRUCTION FORMAT
DATA FORMATS
When representing data, a byte may store a single
character (unpacked format), or two numeric digits
(packed format).
UNPACKED FORMAT
A byte in the unpacked format uses all eight bits to
represent one alphabetic or numeric character. This
format, for example is required for the storage of
any characters that are to appear on any type of dis-
play output such as the Printer or Typewriter.
Some of the more commonly used characters, and
the hexadecimal representation of their bytes are as
indicated in the tables below.
ALPHABETIC NUMERIC
Char.
Hex. Char. Hex. Char. Hex. Char. Hex.
0 FO
A
Cl
J
Dl 1
Fl
B
C2 K
D2 S E2 2 F2
C C3 L
D3
T E3 3 F3
D C4 M
D4
U E4 4 F4
E
C5
N
D5
V E5 5 F5
F
C6 0
D6
W E6 6 F6
G
C7 P
D7 X E7 7 F7
H C8 Q
D8
y E8 8 F8
I C9 R
D9 Z E9 9 F9
SPECIAL CHARACTERS
Char.
Hex.
Char. Hex.
BLANK
EO
- (Minus
60
. (Period)
4B
/ Hyphen)
61
<
4C
, (Comma)
6B
( 4D % 6C
+
4E
# 7B
& 50 @ 7C
$
5B
t (Quote)
7D
* 5C = 7E
) 5D
Space
40
A decimal numeric field in unpacked format is
assumed to contain a sign in the high-order four bits
of the right most byte. All other bytes, in the zone
portion, will have the four high-order bits a value of
all ones (11112 ),
However, the decimal numeric field must be packed
before it may be used as an operand in a decimal
arithmetic operation.
6
PACKED DATA FORMAT
In packed data format, one byte stores two decimal
digits except for the rightmost byte which contains the
sign in the four low-order bits.
The following example shows the same field in un-
packed and packed format. Each location represents
a byte shown in hexadecimal format.
UNPACKED
PACKED
1 FO 1 F3 1 F1 I F6 1 F2 1 F1 I 80 I
103 I
16
1 21 1 OS I
It should be noted (as in the example above) that when
either packing or unpacking a field the rightmo st byte
has its zone and numeric portions reversed.
SIGN RECOGNITION
In decimal arithmetic operations the sign of a field
is recognized as positive ifthe sign position contains:
(1) All one bits (1111)2
(2) Qriftherightmostbitisa(0}z Le., (1010)2'
(1110)2'
If the sign has a low-order bit of (1) 2' and at least
one of the remaining bits is (0) 2' it is considered
negative.
Mter a decimal arithmetic operation the sign of the
result is one of the following:
(1100)2 for positive
(1101)2 for negative
Thus, in preparing source card input for numeric
data fields, the user may follow existing procedures,
L e., for a negative field an overpunch of the minus
(11 punch) in the least significant position generates
a zone portion of (11012 ),
EDITED FORMAT
A packed numeric field may be placed in edited
format with a single EDIT instruction (see page 33).
A field in edited form is unpacked and contains neces-
sary edit symbols.
01 01 I 23
48
+
I- 1- 1 0 1 1 2 3 4 1
-I

MACHINE INSTRUCTION FORMAT
The 70/25 instruction format is variable in length.
An instruction may contain either two, four, or six
bytes.
The first byte of each instruction is an operation code.
The format of the second byte varies from one in-
struction to the next. In some instructions it is used
as a binary length counter (L). In others , the byte is
divided into two length counters of four bits each
(Ll' L2). In still others, it is used to hold a mask
(M), or one or more General Register numbers (R),
(R1
-R
3
). The second byte of a I/O command con-
tains a trunk and device designation.
The third and fourth bytes hold the address displace-
ment (D) and the number of the General Register (B)
which contains the base address to be associated
with that displacement.
3rd byte 4th byte
In a two-address instruction the fifth and sixth bytes
constitute the Band D field of the second address.
The machine formats and the type of instructions
using each format are shown below:
SIX-BYTE INSTRUCTIONS
Binary Arithmetic
Decimal Arithmetic
Decimal Comparison
Packing and Unpacking
Data Movement
Logical Operations (And, Or, Excl. Or)
Logical Comparison
Data Editing
Input/ Output
7
FOUR-BYTE INSTRUCTIONS
IGN:
lop 81M41IG~IB241D2 121
1 op 81 R:IIG~I B241 D2 121
Conditional and Unconditional Branch
Test Under Mask
Set P2 Register
Load Multiple
Store Multiple
These bits are not used (ignored) by the
instruction.
TWO- BYTE INSTRUCTIONS
Halt
Input/Output (Post Status)
True and False Exercise
T F 1. Data Edited for display purposes may
be in packed format.
T F 2. A numeric field in unpacked format is
assumed to contain an (F)16 in the high
order four bytes of each byte.
T F 3. When packing or unpacking a field, the
rightmost byte has its zone and numeric
portions reversed.

T F 4.
The values (1101)2 and (1001)2 are valid
T F 6.
Each displacement field accommodates
negati ve signs. a 12 bit address.
T F
5. The Bl or B2 fields of machine instruc-
T F 7.
An instruction is
variable
in length;
tion format contain the HSM address of either two, three, four, or six bytes.
a general register.
8

INTERRUPT
INTRODUCTION
An interrupt facility provides an automatic means for
the detection of exceptional conditions, and a method
for an immediate program response. The function
of sensing for exceptional conditions and the auto-
matic transfer of control to software has been
mechanized in the RCA 70/25 hardware. Combining
software with the hardware interrupt makes it
unnecessary to halt the computer when an error
develops, and eliminate s program sensing of external
demands. This system allows the user to program a
response independently of his production processing.
PROGRAMMING STATES
All instructions are executed in one of two states:
(1) the Processing State (P1) , or (2) the Interrupt
State (P2). The Processing State is the normal mode
of operation. An interrupt causes the computer to
transfer from the Processing State to the Interrupt
State where it remains until instructed to return to
the original Processing State.
PROCESSING STATE
During the execution of instructions in the P1 state
the address of the next instruction to be executed is
stored in the P1 counter (reserved HSM forty (28)16
and forty-one (29)16'
BYTE (40)10 BYTE (41)10
121512141213121212111210129128127126125124123122121120 I
PI COUNTER
Each time an instruction is staticized in the P1 state
the contents of the P1 counter is updated to contain
the address of the next instruction. All thirty-one
instructions may be executed in the P1 state. The
computer remains in this state until an interrupt
occurs.
INTERRUPT STATE
When an exceptional condition is detected, and an
interrupt initiated, the hardware transfers control
to the instruction whose address is stored in the P2
counter (reserved HSM forty-four (2C)16 and forty-
five (2D)16)'
BYTE (44)10
P2 COUNTER
9
The system is now in the Interrupt State. Each time
an instruction is staticized the contents of the P2
counter is updated to contain the address of the next
instruction to be executed. All thirty-one instruc-
tions may be executed in the P2 state, and the com-
puter remains in this state until a STPP2 instruction
(see page 39) is executed. The STPP2 instruction
resets the P2 counter to its original value, and
returns Control to Pl. The Interrupt State is not
interruptable. Any interrupt attempted will be
"PENDING" until the computer returns to the Process
State.
Interrupt occurs only after the termination of an
instruction. Therefore, when the system returns
to the Process after interrupt, the P1 counter holds
the address of the instruction that immediately fol-
lows the point where interrupt took place. This
automatic linkage permits the user to disregard
interrupt considerations when programming his
process.
TYPES OF INTERRUPT
There are four conditions that can interrupt the
Processing State:
1. I/O Device (Manual or Termination)
2. Operation Code Trap
3. Arithmetic Overflow or Divide Exception
4. Elapsed Timer Overflow
1/0 INTERRUPT
An interrupt occurs after the termination of each
Input/Output Command. A termination interrupt
indicates one of two possible terminating conditions:
1. The I/O instruction was not completed success-
fully (ERROR). In this case, the Secondary
Indicator bit in the Standard Device Byte is (1) 2
(see page 53).
2. The channel and device that executed the instruc-
tion is now free, and ready to receive the next
command (NORMAL TERMINATION). In this
event, the 26 bit of the Standard Device Byte is
set to (1)2' (see page 53).
The purpose of normal termination interrupt is to
notify system software that an I/O channel is avail-
able. With this knowledge, the software can use

efficiently the overlap capabilities of a system con-
taining eight I/O Channels.
A communications device request, or a request for
control by the operator at the console typewriter also
generates an I/O Interrupt. Console request inter-
ruption is distinguished by the fact that the 27 bit of
the Standard Device Byte is set to (1)2'
Prior to entering the P2 state, the computer auto-
matically:
1. Stores the state ofthe Condition Code Indicator,
The present value ofthe Condition Code is stored
in the 20 -21 bits of the reserved HSM location
forty-three (2Bh6'
~~
The Condition Code Indicator is then set to (00) 2'
2. Stores the identification (Trunk and Device
Number) of the interrupting device in the
reserved HSM location forty-seven (2Fh6' The
Device Number is stored in the 20- 23 bits, and
the Trunk Number is stored in the 24 - 27 bits.
BYTE (47)10
127
126 125124123\ 22\ 21 120
~~
Trunk
Number
Device
Number
3. Stores the Standard Device Byte for the Inter-
rupting device in the reserved HSM location
forty-six (2Eh6'
See page 53 for a desc ription of the Standard Device
Byte.
The P2 counter contains the address of the first in-
struction of a routine to be executed when interrupt
occurs. This routine tests the Condition Code (with
a Branch On Condition instruction). A setting of
(00) 2 indicates that interrupt had been caused by an
I/O device. The Trunk and Device Number have been
stored in a reserved area of HSM, allowing the
routine to identify the device that caused the interrupt.
For example, if the Console Typewriter is Device
one on Trunk three, and the Interrupt button had
been depressed, then HSM location forty-seven would
contain:
Trunk
3
Device
1
10
OPERATION CODE TRAP
If an instruction is staticized in which the Operation
code is not one of the thirty-one legitimate codes, an
interrupt is initiated. This interrupt is called an
Operation Code Trap.
Prior to entering the P2 state, the computer auto-
matically:
1. Stores the state of the Condition Code Indicator
in the 20 -21 bits oflocation forty-three (2Bh 6'
2. Stores the illegal operation code that caused the
interrupt in the reserved HSM location forty-
two (2A)16'
BYTE (42)10
The two high-order bits of the Operation Code in-
dicate the length of the instruction.
00
01
or 10
11
two-byte instruction
four-byte instruction
six-byte instruction
3. Sets the Condition Code to (01)2' The interrupt
routine tests the Condition Code. A setting of
(01)2 indicates that the interrupt was caused by
an illegal operation code in the instruction pre-
viously staticized in the PI state. Depending on
the situation, the illegal operation could actually
be an error, or an intentional interrupt. In the
latter case, the interrupt could simulate an in-
struction that is not part of the 70/25 order code.
For example, the 70/45 operation code (4E)16
for Convert Decimal would cause an interrupt
on the 70/25. However, the decimal conversion
could be simulated by instructions in the P2
state.
ARITHMETIC OVERFLOW AND DIVIDE EXCEPTION
A carry out of the high-order position of the first
operand during the execution of an Add Decimal
(FAh6 or a Subtract Decimal (FBh6 instruction
causes interrupt. If the operands of a Divide Decimal
(FD)16 operation are not properly edited, an inter-
rupt occ urs .
Hardware stores the state of the Condition Code in
the 20 -21 bits of reserved location forty-three
(2Bh6' and resets the code to (10)2' before trans-
ferring to the Interrupt State.

ELAPSED TIMER INTERRUPT
General Register Zero serves as an elapsed time
clock. Every 16-2/3 milliseconds (using 60 cycle
power) the power supply generates a (1) 2 bit that is
added to the contents of Register Zero. When the
register overflows, interrupt takes place. The time
intervals between interrupts is controlled by the
value pre-stored in the register (see page 13).
Before transfer to the P2 state, the current setting
of the Condition Code is stored in the 20 - 21 bits of
reserved location forty-three (2Bh6' and the code
reset to (11)2'
INHIBITING INTERRUPT
All interrupts except the Operation Code Trap may
be inhibited. Reserved HSM location forty-nine
(31)16 allows the user to inhibit interrupt on all or
selected I/O channels. The user places a mask into
the eight rightmost bit positions of the reserved loca-
tion. The bit positions, (2
0
-2
7
), correspond to the
eight I/O channels, 0-7. A (1)2 bit permits interrupt
and a (0)2 bit inhibits it.
LOCATION 49 (31)16
A
mask of 10010110 allows channels one, two, four
and seven to interrupt, and inhibits interrupt from
channels zero, three, five, and six.
If an interrupt on an I/O channel is inhibited, the
channel remains busy until a Post Status instruction,
addressed to that channel, is executed (see page 53).
Three bit positions (22_2°) in reserved location
forty-eight (30) 16 allow the user to inhibit the Elapsed
Timer, Arithmetic Overflow, and MULTIPLEX
CHANNEL interrupts.
21 =Overflow
22=Timer
2
0co
Multiplex Channel
A mask of 101 in the 22_20 allows Timer and Multi-
plex interrupt, but inhibits interrupt caused by
arithmetic overflow or divide exception.
INTERRUPT PRIORITIES
Op Code Trap - immediate
I/O 1
Elapsed Timer 2
Overflow and
Divide Exception 3
11
Exercise:
T F 1. Only fifteen of the thirty-one 70/25 in-
structions can be executed in the
Interrupt State.
T F 2. The main program is executed in the
Processing State.
T F 3. The Processing State is not inter-
ruptible.
T F 4. The Interrupt State is not interruptable.
T F 5. The Condition Code is stored prior to
changing states.
T F 6. The Condition Code is always set to 00
prior to going into the P2 state.
T F 7. The two program counters are stored
in the reserved area of memory.
T F 8. The Processing State uses only one
counter to indicate the address of the
next instruction.
T F 9. The PI counter is destroyed by the
interrupt.
T F 10. The computer remains in the P2 state
until another interrupt occurs.
T F 11. The operation code is stored on an
Operation Code Trap.
T F 12. The Standard Device Byte is stored on
an Operation Code Trap.
T F 13. Interrupt from any r/o device is the
only interrupt that can be inhibited.
14. Describe the use of HSM location 49.
15. Describe two uses of the Operation Code
Trap.
16. Write the masks necessary to inhibit all
possible interrupts. Where must they
be stored?
17. Describe what is stored in reserved
memory when each of the four types of
interrupt takes place.

SUMMARY OF 70/25 INTERRUPT LOGIC
Instruction
Op Code Trap
Store:
1. CC in HSM 43
2. Op Code in HSM 42
Arith. Overflow
Store CC
in
HSM 43
Interrupt
Indicator
Set?
Yes
I/O or
Op Code Trap?
Neither
Arithmetic
Overflow or
Elapsed Timer?
Transfer
to
Interrupt State
Identify Interrupt
(CC Setting) and
Process
Accordingly
STP2
Register
Return to Processing State
12
No
I/O
Instruction
Interrupt
"Pending!!
Interrupt
Inhibi ted By
Mask?
HSM 49
No
Yes
Store:
1. CC in HSM 43
2. TK and DV# in HSM 47
3. Stand. DV. Byte in HSM 48
Set CC
to
(00)2
r
HARDWARE
PROGRAMMING
1

ELAPSED TIME CLOCK
The least significant 24 bits of Register Zero, the
first General Register, may serve as an elapsed time
clock. The 70/25 power supply generates a (1)2 bit
every 16-2/3 milliseconds (60 cycle power). This
bit is added to the contents of Register Zero. When
register overflow develops, an interrupt is initiated
(see page 11). The programmer may control the
time interval between these interrupts by the selec-
tion of the value stored in the register.
A (1) 2 is added to the low order bit of the register
as follows:
50 CYCLE POWER 60 CYCLE POWER
1 ADD EVERY 20 MILLISECONDS 1 ADD EVERY 16-2/3 MILLISECONDS
50 ADDS EVERY SECOND 60 ADDS EVERY SECOND
3000 ADDS EVERY MINUTE 3600 ADDS EVERY MINUTE
180000 ADDS EVERY HOUR 216000 ADDS EVERY HOUR
If the Timer is set to a value of all one bits
(16,777,215>10' the first add causes overflow. If
the Timer contains all zeros, overflow will take
place approximately 93 hours later, using 50 cycle
power, or 77 hours later using 60 cycle power.
The number of adds required to clock off more
meaningful time intervals are indicated below:
60 CYC LE POWER
16-2/3 MILLISECONDS
1 SECOND
30 SECONDS
1 MINUTE
30 MINUTES
1 HOUR
1 ADD
60 ADDS
1800 ADDS
3600 ADDS
108,000 ADDS
216,000 ADDS
13
The overflow value of the 24 bit Timer is
16,777,216
10
. Let us assume we wish to generate
an interrupt every minute. By subtracting 360010'
the number of adds executed in a minute, from the
overflow value, we can determine the amount to be
stored in the register.
16,777,216(10)
3,600(10)
16,773,616(10)
to
FFF1EF(16)
It should be remembered that the timer contents is
reduced to zero at the point of overflow. As long as
the initial value is added to the register contents be-
fore the computer returns to the Processing State,
no time loss results.
Regi ster Zero may not be used for general storage
purposes. Even though interrupt has been inhibited
(the 22 bit of reserved HSM location 48 is (0)2), the
addition of (1) 2 bits to the register contents continues.
Exercise:
If we want interrupt after 5 minutes and 30 seconds,
what value should be stored in register zero?

INTRODUCTION TO THE RCA 70/25
ASSEMBLY LANGUAGE
FORMAT REQUIREMENTS
The RCA 70/25 Assembly is an automatic program-
ming system designed to translate a symbolic
machine-oriented program into a machine-coded
program for subsequent execution on the RCA 70/25
system. The source language consists of one-line
statements written on the RCA Spectra 70 Assembly
Program Form. Each single-line statement per-
forms one of the following functions:
1. Generates an object program instruction.
2. Allocates data areas or constants.
3. Notifies the assembler to perform a specific
function.
OPERATION FIELD
Every statement, except a line used solely for an
output listing comment, must have an entry in the
OPERATION field (Cols. 10-14) specifying one of
the above three functions.
NAME FIELD
The NAME field (Cols. 1-6 only) may be used when
it is desired to symbolically identify the leftmost
location of the field generated by the statement. The
NAME entry symbol must consist of at least one
alphabetic (A-Z) character followed by any combina-
tion of alphabetic and/or numeric (0-9) characters
that do not exceed a total of six characters. The
only exception to the symbol entry above is that an
asterisk may appear in Col. 1 if the statement line
is to be used for an output listing comment.
OPERAND FIELD
The OPERAND field has entries as required by the
OPERATION field. Thus, if the OPERATION field
specifies that a constant is being defined, the
OPERAND field entry is the value of the constant.
If an instruction Operation Code appears, the
OPERAND field must follow the prescribed format
for that particular instruction.
COMMENTS FIELD
A comment may appear in any statement line fol-
lowing the OPERAND entry. It must be separated
from the required OPERAND entry by at least one
blank column. The entire statement line (to Col. 71)
may be used for a comment if an asterisk appears
in Column 1.
14
IDENTIFICATION FIELD
The contents of the IDENTIFICATION field has two
functions. In the START statement, the first four
positions, columns 73-76, may contain a name to be
assigned to the object program. If the last four
positions, columns, 77-80, are numeric, the contents
is used as the initial setting ofthe Assembly sequence
counter. If not numeric, the counter starts at all
zeros. Each object instruction has a sequence
number either derived from the value in columns
77-80 or from zeros.
ADDRESSING
A symbolic name is the most frequently used means
of addressing and referencing a location. When a
symbol has been used in the NAME field to define a
location, it may be referenced as frequently as de-
sired in the OPERAND field. The value assigned is
the address of the left end of the data field or in-
struction on the 'NAMEd' line of assembly coding.
As stated previously, the symbol may be any com-
bination of the alphabetics (A-Z) or numerics (0-9).
There are two restrictions: (1) no name may exceed
six characters, (2) the first character must be al-
phabetic.
The following are examples of valid and invalid
symbols:
VALID
Al
STKNKI
C
INI
INVALID
OPN
BEGINERR
IA
IN.I
(Space invalid character)
(Too many characters)
(First character not alphabetic)
(Period invalid character)
The Assembler builds a table containing all the
symbolics that appear in the name field. A specific
HSM address is assigned to each symbolic. The
LOCATION COUNTER, a program counter main-
tained by the Assembler, generates these addresses
and makes assignments. Assume a routine is to
begin at HSM location 2000.