Sharp MZ-350C User manual

MZ-3500
SERVICEMANUAL
CODE: OOZMZ 3500SM/E
rC
PERSONALCOMPUTER
MODEL
MZ-350C
CONTENTS
1. Specifications 1
2. Software(Memory) Configuration 7
3.CPUand memory 12
4.CRT display 25
5.MFD Interface 52
6. R232CInterface 72
7. PrinterInterface 7g
8. OtherInterface 81
9. Power Circuit discription 37
10. KeyboardControllerCircuit discription QQ
11. Seif checkfunctions 94
12.IPL flow chart 103
13. Circuit diagram & P.W.B
Parts list & Guide
SHARP CORPORATION

M Z 3500
1.SPECIFICATIONS
1-1. Specification ofthe main unit (Model35XX)
Outline
1) High speed processing usingmulti-CPU
2) Built-in mini floppy disk
3) Built-in printer interface and RS232Cserialinterface
4) Connection ofuptotwo Videodisplav >nits (separate graphicdisplay or overlaid display possible ontwo individualcolor
monitor units)
5) Permits theuseof StandardCP/M
Model3530 incluse a singledouble-side,doubledensity mini floppy
disk and64KB RAM.
Model MZ3540 hastwo double-side,density mini floppy disks and
64KB RAM.
LSI
DISPLAY
MFD
Other I/F
Other
functions
Software
Accessories
CPU
MEMORY
I/O
MZ353X
MZ354X
Light pen
Keyboard
Printer
RS232C
Multi-CPUprocessing
ROM
RAM
Custom LSI
GDC
FDC
RIO
SIO
TIMER
CLOCK
Screen structure
Elements
Attribute
Colors
I/F
One double-side.
double density
floppy disk
Two double-side,
double density
floppy disks
IPL
C,G
For main CPU
For sub-CPU
Shared RAM
VIDEO
RAM
Memorymapper
Screen Controller
CRT Controller
Floppy diskController
Parallel I/O port
Serial I/O port
Counter
Clock
Model3531includes a single double-side,
doubledensity mini floppy disk and128KB.
Model3541 hastwo double-side,double
density mini floppy disks, and128KB.
Z80Amicroprocessor x 2
8K Byte ROM
8K Byte ROM
64KBit DRAM x 16 Chips or8 Chips
16KBit SRAM x 4 Chips
16KBit SRAM x 1 Chip
16KBit SRAM x 1 chip
4KBit SRAM x 2 Chips
TH SP6102R001
CSP-1 SP6102C002
CSP-2 SP6102C003
MPD7220
pPD765
8255
8251
8253
/JPD1990AC
80 characters x 25 lines. 80x 20,40x 25.or40x 20
8x 16,8x8
Reverse, blink, line (horizontal, Vertical)
8 colors on eachCharacter and backgroundcolor
2 channels(applicableCRT: 640x 400, 640x 200, B/Wor color).
256 bytes/sector, 16 sectors/track, 80 tracks/disk
Built-in interface for optional MFD.
Oedicatedkeyboard
Centronicsinterface
No protocol. asynchronus mode, 110to 9600 bps,half-duplex
Speaker (500mW)Battery backup Clock HALT SW Speaker volumecontrol
FDOS
CP/M
BASIC
Utilities
Basic CP/M
ExpandedCP/M
High class compatible with PC3200BASIC,supplemented and graphic
control commands
Expanded RS232C, GPIB, and GPIO
BACKUP, INIT, COPY,DEBUG. KILLALL
Intstruction Manual
master floppy disk
power cord
O

M Z 3500
1-2. MZ-1K01 (Keyboard) specification
Outline
Specification
MZ1K02:U.S.keyboard(ASCII) MZ1K03: U.K.keyboard(ISO).
MZ1K04:Germankeyboard MZ1K05: Frenchkeyboard
LSI, IC
Keys (98)
Interfacing cables
Other
Cabinet
KeyboardController
CMOSIC
Sculpture key
Alphanumeric keys
Modeswitch
61
1
80C49 or 8749
4049x2,4514
Mechanicalcontactkey, with life of 10,000,000 operations.
Tenkey 15
Function keys 6 Definablekeys 10
For datatransfer with theCPU (serial) and power supply (transmission under 15,000 baud)
Use of coiled cable with 8-pin DIN plug
Repeat function
Indicators (4 LED's)
Molded
Size (Wx H
Automatic repeat occurs 0.64secondsafter
.... , 2 Two-keyrollover
contmuousdepression ofthe same key.
POWER, Alphanumeric keys
Color
xL)
Office gray
467x 35x 190
Weight | About 1 .5kg (3.3 Ib)
Keyboard layout
Refer tothe page 7 IN "CIRCUIT DIAGRAM"
1-3. MZ-1U02
Outline
Specifications
Expansion unit forthe MZ-3500 series CPU, which canbe attached tothe rearside ofthe main unit.
Optional boards are plugged intothe expansion box.
The expansion box will accomodate upto four Option boards.
Number of slots: 4 slots
Slot connector: 60-pin edge connector x 4
Area ofthe slotinserting option board: 140.5 x 140
Slot for Option and slot number
MZ-1R06
(expansionRAM)
SFDI/F
ExpansionRS232C
GPIO
GPIB
(IEEE I/F)
Slot 1
O
O
o
o
Slot2
o
o
o
0
Slot 3
O
O
o
o
Slot 4
O
0
o
0
-2-

MZ3500
Expansion unit
Screw (2)
Screw (1)
1-4.MZ-IR03
Outline
Specifications
Optionalboard used graphicdisplay functions with the Model-3500 series CPU. It includes32KB of RAM.
Itis inserted through the slot onthe front panel ofthePU.
The MZ-1U02expansion boxisnot required.
LSI
Graphic functions
(Color must be
specified for each
dot.when the color
video unit isin use)
Software
GDC Graphic Controller
Basic (buit-in)
vinrn RAM -
Expansion
(optional)
-~-___WDEO RAM
640x 200
green monitor
640x 200
color monitor
640 x 400
green monitor
640x 400
color monitor
BASIC graphic control Statements
MPD7220
16KDRAM x 16 (32KB)
16KDRAM x 32 (64KB)
32KB
(basic)
640x 200 dots
Two screens
______ — - ~
640x 400 dots
One screen
___—
SDISP
ODISP
CHANCEDISP
GCOLOR
CLS
PSET
PRESET
LINE
GTABLE
CIRCLE
PAINT
GINPUT
GDISP
GPRINT
GREAD
GENTER
GCURSOR
GSCROL
SYMBOL
SCALE
96KB
(maximumexpansion)
640x 200 dots
Six screens
640x 200 dots
Two screens
640x 400 dots
Three screens
640x 400 dots
One screen
Screen designation fortwo videounits.
Oesignation of Output screen.
Modedesignation
Graphic pattern designation
Cleared bythe colorspecified.
Dotset
Oot reset
Line creation
Tablecreation
Circlecreation
Paintover
Input of graphicpattern
Display of graphicpattern
Output of graphicpattern on printer
Read of coordinates
Input of pattern within the specified area
Graphic Cursor Positiondesignation
Graphic screen scrolling
Graphic symboldisplaying
Seren scle-down designation
(
-3-

M Z 3500
1-6. MZ-1R06
Outline
Specifications
Optionalboard for memoryexpantion ofthe MZ-3500 sries CPU.withthis Option the mainmemory(RAM) canbe expanded
uptoa maximum of256KB.
This Optionplug into the expantion boxin slot 1or3.
LSI
Memory and user
area
Basic
Expansion
64KDRAM x 8 (64KB)
64KDRAM x8 (128KB)
Total capacity of
the main CPURAM
BASIC
(RAM
BASE)
SYSTEM
AREA
USER
AREA
Main CPU only
128KB
•57KB
80KB
Useof MZ-1R06
192KB
-
128KB
Using eight 64K RAM's
on theMZ-1R06
256KB
-
208KB
- 4 -

MZ3500
1-7. MZ-1D07
Outline
Specifications
High resolution MZ-3500 series 12" green monitor
Videotube
Displaycapacity
Display size
Input Signals
Powersupply
Cabinet
Adjusting knobs
Accessories
Type
Non-glaregreenSize12".
90° deflection
Fluorescent color P39 (green, long PERSISTANCE)
Total number of
displaycharacters
2,000 characters
(80 characters x 25 lines)
Display capacity
640 horizontal dots,
400 Verticallines
220x 145
Method
Horizontal
Separate input, TTL level
20.86kHz Vertical
47.8 Hz
29W power consumption
Molded
Color
Size (Wx H x L)
3
Officegray
324x310x356
Weight 7.2kg
Vertical synchronization, contrast, brightness
CPU connection cable and power cord andTut stand
c

MZ3500
1-8. System configuration of Model3500
Keyboard
M2-1K02
MZ-1K03
MZ-1K04
MZ-1K05
1
1
Printer '
I02824E l
|
l OptionMFDl
l CE-331M |
ll
*Model-3541 = Model-3531 + MZ-1F03
-6-

M Z 3500
2. SOFTWARE(MEMORY)CONFIGURATION
Memory will be operatedunder four states of SDO ~ SD3,
depending onthe hardware and Software configurations.
Inthe paragraphs to follow, description will be made for
those four states.
2-1. SDOUNITIALIZESTATE)
SDO can only exist immediatelyafterpower on,andthe
System executes IPL underthis condition and that the
system thusloaded will automatically assign memory area
for SD1, SD2, and SD3.
MAIN CPU
SUB CPU
MAS
MA2
MAI
MAO
17 p 171?
r r r r
{,
/
cooo
BFFF
]
/
8000
7 FFF
J
/
4000
3FFF
1
0
0
0
0
1
RAMA
4
RAMA
3
RAMA
2
1
1
ROMB ]
1
0 1
01
01
11
— 1 T FFFF T
]l |RAM(COM)f
:nAn 1 i
tiOO ^\
\
RAMA
J1
MSI =0(L)
MSO = 0 (L)
2000
OFFF
0000
l J
v
A
\\
\\
\\
U
\\
\\
\\
\\
\\
\\
ROM
(SPÄHE)
ROM
IPL
ROM
IPL
4000
27 FF
l FFF
0000

M Z 3500
Operational description
(1) Upon reset after power on,the main CPU loads the
contents ofthe initial programloader(IPL) into RAM
starting at address 4000H, during which time reset is
applied tothe sub-CPU.
TIMING OF RESET SIGNAL
Vcc-
SYSRES-
SRES-
•*
I l
pnwFRISUB
CPU
P°*E*<
START
l
l
POWER
OFF
(2)The main CPU then terminates resetting the sub-CPU
and Starts the sub-CPU. Atthe same time, the ROM-
IPLis assigned tothe sub-CPU.
(3)The main CPU thensend the memoryallocation (state)
to SD1. and Starts to load DOS from the System floppy
disk.
Signal generated from the
CR network and power supply.
Output Signal from the main CPU port.
MAIN CPU
START
a. Main CPU reset time
b. Main CPUIPL load time
Memory Map Data:
1. ROM-B is tested to determine if ROM's are present.
2.The ROM-IPL functions under control ofthe main CPU
at first, but later it functions under the sub-CPU after
theIPL program has been loaded in RAM.
3. RAM-COM is shared by both the main CPUandthe sub-
CPU.
INITIALIZE FLOW
4. Memories other than describedabove cannot be accessed
under theSDO state.
5. Bankselect, MAO~MA3, is used within the address ränge
ofCOOOH-FFFFH.
-

ROMIPL
1.An8KBROM (2764 or mask ROM equivalent) is used
forthe ROM-IPL.
2. When the system reset signalturns from Iowto high
state after power on,the main CPU Starts to operate. At
thisstage, the ROM-IPL is addressed.
3.TheCPU Starts from address 0000(ROM address 10000).
4.The main CPU sets the sub-CPU reset signal from Iowto
high state äs itgoes outofits initial state viathe memory
mapper andthe sub-CPU Starts to operate. At this point,
the ROM-IPL is addressed bythe sub-CPU.
5. Address 0000 ofthe sub-CPU isROM address (0000).
The memory areaabove ROM address (1000) cannot
be used bythe sub-CPUbecause the main CPU initial
program has beenloaded there.
'
2-2. SD1 (SYSTEM LOADING & CP/M)
SD1 determines which operating system isin use. The
system is loaded inthe CP/M (Control Program for Micro-
processors) mode.
MZ3500
Main CPU logical address (during IPL Operation)
Logical address ofthe sub-CPU
I
ROM physical address
i
OFFF
0800
07 FF
0000
X
V
1 FFF
1 800
17 FF
1 000
OFFF
0800
07FF
0000
1 FFF
1 800
17FF
1 000
OFFF
0800
07FF
0000
8F
\
'
ROMIPL
.B
MS1=0(L)
WSO=1(H)
SUB CPU
rr r r
/
F7
(
FF
;'if i ( i
RAM (KM
4
3
k
\
» \
x
\
V
- 9 -

MZ 3500
Operational description
(1) As soon ästhe sub-CPU is started, it initializes theI/O
port and waits for programtransfer(IOCS) from the
main CPU. This IOCS (Input Output Control System)
is the programresident at address 4000H-5FFFH.
(2) Asthe main CPU loads the Information from sector
CommunicationbetweenMain andSUB CPU
"1"of track "0"ofthe floppy disk, it loads the IOCS
and bootstraproutine tothe sub-CPU.
(3)The bootstrapprogram is loadednext.
(4) The bootstrapprogramdeterminesmemoryallocation.
BUSRQ H OUTPUT
l (ISOLATION OFCOM RAM)
2.3. SD2 (ROM based BASIC)
SD2 is active when "SHARP BASIC" is executed via ROM.
MAIN CI'U
MS] = l (H)
MSO = 0;L;
SUBCPU
MA3
RAM
BANK
MAI
SELECT
MAI
MAO
FFFF
cooo
4000
im
0000
{MO2
00 0000
00 0011
00 1100
01 0101
1 III
RAMA RAMB
4
3
2
ROM B
ROMA
0
1 1,2,3,4
ROMCROMU ROM] ROM2
000]
MO] 00110
MOO 01010
0
1
I
0
1
'l
01 1
I 0 0
I 0 0
1 0 1
11
HAM<_
2,3,4
1111
00 1 1
1100
0101
11 1
KAMI.
l|2,S|4
]
1
1
1
püS>
LZLrnm
vV
\\
\\
\\
U
u
\\
u
\\
u
H
1»
»\
v\
°v
RAM SD
RAM SC
RAM SB
RAM SA
1. Bank select. MAO~MA3. is effective for memory area COOOH-FFFFH.
2. Bank select. MOO~MA2, is effective for memory area 2000H-3FFFH.

M.Z 3500
2-4. SD3 (RAMbasedBASIC)
SD3is active when "SHARPBASIC" is ececuted via RAM.
"SHARPBASIC" is loaded inRAM from the floppydisk.
MAIN CPU
MSI = 1<H)
SUBCPU
RAM
BANK
SELECT
MA3 00000000 1111 1
MA 10011 00110011 1
MAO 010101010101 1
(
)
SFF?
1FFF
0000
IIIIIIIII lüftaJx " '
RAMB RAMC RAM»
x\
\^
1 2,3,4 1,2,3,4 1,2,3,4 \\
3_
L2
^\
^\
V
*
0
\\ RAJt| SP
\\ RAM SC
V,RAMSB
KOMo
RAMA ROMl ROM2KOW3ROM4 \\ROMBAS
1L
"-• "u S'WfOOM)
Ut"'"C
ROM 1Pl
ROM («02 0 0 0 0 l 1 1
BANK<M01 0 0 1 " 1 0 0 1
SELECT(MOO 01010I 0
1. Bankselect,MAO-MA3, is effective for memory areaCOOOH-FFFFH.
2. Bankselect.MOO-MO2, is effective for memory area 2000H-3FFFH.
Operationaldescription
The state ofthe System is determined bythe bootstrap
program before the load ofthe System program.

3-1.Block diagram
1) Relationbetween MMR (MainMemoryMapper) and
mainmemory.
3.CPUAND MEMORY
Höh
PH
CLOCK ('..
—O32MI!
—O ISMHi
—O 4Mll>
MAIN
CI'U
7. - 80A
SEMI CUSTOM
LSI
MEMORY
MAPPER
-0
-o
-O 200/4«
-O./.
=
Sl
BUS
DK1VKR
=====
BCPU
/-80A
A/B
U
CTRL]
||AS
m
P^— —
l
1 , r-„-
r
FKER
II1 1
T" RAM|
<64KB»2) '
1 1
1 MI'XH
MDL IPLEXER
pou OPTION
U_m
MPXK COMMON RAM
2KB
1
!•
ROM ( BAS I C ) 1
S2KB 1
or «KBX4
1
L
i
V
F
=
K
76
=
ROM IPL1 RAMorROM
8KB [~~|
8KB
1- 1
r— RECEIVER
LLLMFDi
-o 1 ' 1
. OPTION '
f
P
.II
SLOT1
SI.OTZ
SLOT3
SLOT 4
n
^T1 ON MZIUO?
yinni.i:
OK H n.n
VV T PRINTER l/KJ
l

M Z 3500
3-2. Main CPUandI/O port
M
A
I
N
C
P
U
[NO
Ix
A2
A3
A4
A5 i
A6 "A
V\ r
A7 P C
IORQ
MT
AYO
Y1
OiA Y3
Y4
G2 B
Y5
GlY6
74LS138
This paragra
Connector Port select an
1 FC2The address
_ \~f\ ~~\is decoded it
v
select signal.
Tf^i -,-,.,- Table below
^v# ."> r L)C
signal functic
J V
J 0 MFÜC
0T"O IOMF
L |
3 U IOABCMEMORY MAPPER)
ADDRESS
A7 A6A5A4A3A2A1AO
00000000
00000001
11011110
11011111
11 1 0 0 0 X X
t'\-\OQ1XX
^t'\OtOXX
11101 1 X X
1111QOXX
11 1 1 0 1 X X
11 1 1 1 0 X X
11 1 1 1 1 X X
HEX
00
01
DE
DF
EO
E3
E4
E 7
E8
EB
EC
EF
FO
F3
F4
F7
F8
F B
FC
FF
NOTUSE
NOTUSE
SFDC (UPD765)
IOSF
INTR
NOTUSE
MFDC (UPD765)
IOMF
IOAB (MEMORY MAPPER)
SPD interface FDC chip select.
AO used forRDandWR.
A1is "don' t care".
SPD interface I/O port and DMACchipselect.
!
Interrupt signal from the sub-CPU tothe main CPU. i
Flipflop resetting signal.
MFD interface FDC chip select.
MFD interface I/O port.
AO used forRDandWR.
AIis "don't care".
I/O port select inthe memory mapper
AOand A1 used during RD,WR.

MZ3500
3-3. SubCPUandI/O port
SUB
CPU
AS65
ASS
2
AS4 i
AS7 4^
5
*Ü~
6
Y6
4G
Y4
Gl Yl
YO
74LS138
„7
S07t
Ä9506
^IQ SO5^
J^ CSP 1, CSP 2
^11SO4-
-12 SÖ3" ^ -JTTT
D15 SÖ2" HEC3 "C"-
14 SÖT—
D "H^ MAIN CPU-INT
Shown atthe left isthe Circuit used by
theCPUto Select theI/O ports. The out-
put address from thesubCPUis decoded
bythe 74LS138to create the Select signal.
Shown below isthe address mapand
select Signals.
AS 7654MEX\
88
1 23456789A8CDEF
88
Signal description
0000 SOO
Output signal tosetthe flipflop to apply Interrupt(INTO) tothe
mainCPU. Enable: communication betweenCPU's.
0001
S01 82518251
SIO ChipSelect.
ASO is used for data control selection.
AS1, AS2, andASSare "don'tcare".
0010 S02 8253
8253counter chip Select.
ASO andAS1are used for Programming duringwrite.
AS2 andASSare "don't care".
0011
S03 8255
8255 PIO Chip select.
ASO andAS1are used for port/control selection.
AS2 andASSare "don't care".
0100 S04 input port Select
8-bit input port.
Used for read.
AS3 are "don't care".
0101
CRT control I/O port chipselect.
AS1,AS2, andASSare used for write.
ASO is "don't care".
0110
S06
UPD7220 (graphic) chip select.
ASO is used for read and write.
AS1,AS2, andASSare "don't care"
0111 SÜ7
UPD7220 (Character) chip select.
ASO is used for read and write.
AS1,AS2, andAS3are "don't care"
1000
1001
1010
1011
1100
1101
1110
1111
NOTUSE
- 18-

MZ3500
3-4.Memorymapper(MMR)SP6102R-001
1) Block diagram
ADDRESS BUS[ J)
AO .l .13.14?1S
CÜAB
CONTROL BUS
MERQ
RFSH
RD
DATA BUS
DO-D7
oc
INTB
WAITB
SYSR
A15
A14
AI3
AI
AO
COAB
MREQB
RFSH
Memory
A15
AI4
RB
GAB
1/0
PORT
LOGIC
~L
""L
1
-
WAIT
TIMING
GENERATOR
CLK
TORESET
INTERRUPT
PRIORITY
ENCORDER
I NTFI)
19 -

M Z 3500
2) Memory mapper (MMR) SP6102R-001 signal description
1
2
9
10
12
13
14
15
16
18
19
20
21
22
23
26
27
~
30
31
Polarity
Signal Name
ST
DO
D7
A15
A13
A1
SRES
SRQ
AR13
AR15
R32
IOAB
SRDY
ROPB
ROAB
RODB
RSAB
~
RSDB
SACK
IN
IN/OUT
IN
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
IN
Main CPU DRAMOutputbuffer (LS244) switching strap.
Bidirectionalmain CPU databus.
(Data bus0 ~ 7)
Main CPU address bus.
Used inthe memorymappinglogic oftheMMRfor address Output forthe DRAM,ROM, and
shared RAM.(Address bus13~ 15)
Main CPU address bus.
Used intheI/O port Select logic oftheMMRto assign device number.
Sub-CPU bus request signal.
• After power on: Halts the sub-CPU.
• After write command (LDA-80H:OUT#FD) bythe mainCPU: Starts the sub-CPU.
Thissignal is issuedaftertransfer ofthe main CPU programcontained inthe ROM-IPL.
(Sub CPU Reset)
Sub-CPU bus request signal.
• Afterpower on: Resets bus request to sub-CPU.
• Afterwritecommand (LDA-02H: OUT#FC) bythe mainCPU: Place bus request tothe sub-CPU.
This signal is issued tobusofthe sub-CPU,after the main CPU writes tothe shared RAMa command
Parameter tothe sub-CPU or reads the message Status from the sub-CPU.
(Sub CPU Request)
Address signal tothe main CPU dynamicRAM.
The main CPU addresssignals,A13-A 15, merged inthe memorymappinglogic Circuit to produce
AR13-AR15. This is means by which the4 basic and CP/Mmemory maps are made. along with MS1
and MSO.
BASIC interpreter 32KBmask ROM chip Select signal.
Valid when SD2is active(Sharp ROM basedBASIC).Command(LDA 02HOUT 3FD)
(ROM 32K Select)
Internal MMRI/O port select logic Signal.
Goes Iowbythe command IN/OUT #FC-#FF.
(Input/Output Address)
Input of ready signal from the sub-CPU.
(Sub CPU Ready)
Chipselectsignalissued from the main CPUtothe8KB mask ROM.
Valid with SDO active (initialize state).
(ROM ipl)
Chip selectsignal for four chip BASICinterpreter 8KB EPROM (A.B.C,D).
Valid with SD2 active(Sharp ROM based BASIC).
*R32B(alternatechoice with the 32KB mask ROM chip selectsignal).
(ROM A~D Buffer)
Row address Select Signal forthe main CPU dynamic RAM (blockA-block D).
RAS (ROWADDRESSSELECT;LINE ADDRESS SELECT) SIGNAL.
(Row address Select)
Input ofbus acknowledge signal from the sub-CPU.
command is Written inthe shared RAM after acknowledgementfrom the sub-CPU. l
Attheendofthe command cycle bus request is released andthesubCPU executes the command. /
- 20-

M7, 3500
Pin No.
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
SO
51
52
53
54
55
56
Polarity :
Signal Name
RF1B
RF2B
WATB
RCMB
ITFB
ITOB
IT1B
IT2B
MRQB
WRB
IT3B
TT4B
SEC
GND
Vcc
SW1
SW2
AO
RFSH
SW3
SW4
GND
FD1
Vcc
FD2
IN/OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Function
Main CPU 128KB dynamic RAM Output buffer (LS244) Output enable signal.
(RAM buffer 1)
Signal identical toRF 1 B.For Option RAM
(RAMbuffer 2)
Wait signal tothe mainCPU.
(One wait cycle is appliedduring the memory fetchcycle ofthe main CPU. It consists ofone clock
period).(WAIT)
Chip Select signal issued from the main CPUto Select theRAM shared bythe main CPUand
the sub-CPU.
(RAM Common)
Interrupt input from the UPD765 FDC (Floppy Disk Controller).
(Interrupt from Floppy)
Interrupt input from the sub-CPU.
(Interrupt from No.0)
Interrupt input fromslot 1 or2.
(Interrupt from No.1,2)
Memory reguest signal from the mainCPU.
(MemoryRequest)
Write signal from the mainCPU.
(Write)
Interrupt input fromslot 3 or4.
(Interrupt from No.3,4)
Input from theFDD (Floppy DiskDrive)assignment dip switch (A). No.1.
'See thedip switch description, provided separately.
(Section)
Ground
5V supply
Input from the System assignment dip switch.
•See thedip switchdescription. provided separately.
Main CPU address bus
Used intheI/O port Select logic intheMMRto designatedevice number.
Refresh signal from the mainCPU.
(Refresh)
Input from the system assignment dip switch.
'See thedip switch description, provided separately.
Ground
Input from the System assignment dip switch.
'See thedip swuchdescription, provided separately.
5V supply.
Input from theF DO assignment dip switch(A), No.2.
*See thedip switch description,provided separately.
- 2l -
- .-..,,,..,

M 7,3500
Pin No.
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
Polarity
Signal Name
SYSR
FD3
COAB
RO1B
GND
Vcc
RO2B
RÖ3B
'ROB
CLK
RO4B
MPX
GND
CASB
GND
INTB
IN/OUT
IN
IN
IN
OUT
IN
IN
OUT
IN
OUT
OUT
IN
OUT
IN
OUT
Function
System reset Signal.
Used to reset I/O port inthe MMR.
(System Reset)
Input from the sytem assignment dip switch.
'See thedip switchdescription,provided separately.
Shared RAM Select Signal.
Address ofthe shared RAMis *F800-#FFFF forthe main CPU
(Common RAM Address)
Select Signal for8KB area allocated to slot 1.
Valid when SD2is active(ROM based BASIC) andSD3 (RAM based BASIC).
(ROM 1)
Ground
5V supply
Select signal for8KB area allocated to slot 2 or3
Valid when SD2is active(ROM based BASIC) andSD3 (RAM based BASIC).
(ROM2. 3)
Read signalfrom the mainCPU.
(Read)
EAITsignalgeneration Clock.
(Clock)
Select signal for8KB area allocated to slot 4.
Valid when SD2orSD3 (RAM basedBASIC) are active.
(ROM 4)
RAS/CAS address switchingsignal forthe main CPU DRAM.
High: Row address Low: Column address
(Multiplex)
Ground
CAS (Column Address)signal forthe main CPU64K DRAM.
•Refresh fortheRAM only.
(Column Address Select Buffer)
Ground
'l h •
(Interrupt)
Not used
-22-

M Z 3500
MAIN CPU
I/O PORT IN MEMORY MAPPER
ADDRESS
A7|A6|A5|A4|A3|A2|Al|AO
11111101
11111110
11111111
II EX
Uf~
KI)
FE
FF
UHUS
Dl
00
D7
ül
DO
1)7
D6
D5
D4
D2
Dl
DO
D4
D3
D2
Dl
DO
D7
D6
D5
1)4
D3
D2
Dl
DO
D7
D6
I/O
OUT
IN
IN
SKQH
i-; i
SKKS
MSI
MSO
M A3
MA2
MAI
MAO
MO2
MOI
MÜO
S\\'4
swg
SW2
swi
SHC
FD 3
FD2
FD1
SKDY
SACK
INP2
INT1
INFO
ME2
M El
-•-> SRQ: Bus request Irom the main CPUtothe sub-CPU.
7-V Sub-CPU reset signal
Memory System define
Bankselectsignal to memory area of COOO-FFFF.
,J
•A
Bank select Signal to memory area of 2000-3FFF.
System assign switch
FD assign
(SW8)
•fr Sub-CPUREADYsignal
•fr Sub-CPUacknowledge signal
Interrupt Status
.1. All Output Signals are reset toIow level upon power on,
l except for SRBQ that goes high.
2. Noted with a star mark "6"are Input/Output Signals, and
rest of others are processed inthe LSI.
#1I/O port Output ofME1andME2 uses the memory at
the addresses.
ME2->8000~BFFF
ME1->-4000~7FFF
When ME1andME2arein high state, RSAB(RASA) is
inhibited during memory addresses in RAM-A that
correspond to overlayedaddresses forME1and ME2.
This isnot true during SD1 mode.
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Wait timing generator
WAIT is issuedonce per main CPU fetch cycle.
Its outut is tri-state.
- L>3 -