RF Technology R50 Eclipse Series User manual

Eclipse Series
RF Technology
[e-mail]
August, 2003
Revision 2
R50 Receiver
Operation and Maintenance Manual
This manual is produced by RF Technology Pty Ltd
10/8 Leighton Place, Hornsby NSW 2077 Australia
Copyright © 2001 RF Technology

Page 2 RF Technology R50
CONTENTS CONTENTS
1OPERATING INSTRUCTIONS 1
1.1 FRONT PANEL C
ONTROLS AND
INDICATORS 1
1.1.1 Monitor Volume 1
1.1.2 Monitor Squelch 1
1.1.3 N.SQ 1
1.1.4 C.SQ 2
1.1.5 LINE 2
1.2 FRONT PANEL INDICATORS 2
1.2.1 PWR LED 2
1.2.2 SQ LED 2
1.2.3 ALARM LED 2
2RECEIVER OPTIONS 3
2.1 SERIAL I/O PARAMETERS 3
2.2 RECEIVER LOW BATTERY LEVEL 3
2.3 LOOP VOLTS SELECT 3
2.4 COS SOURCE/SINK SELECT 3
2.5 COS POLARITY 4
2.6 NOISE BLANKER 4
2.7 ADVANCED SLOT SELECTABLE PARAMETERS 4
2.8 STANDARD CHANNEL PARAMETERS 5
3RECEIVER I/O CONNECTIONS 5
3.1 25 PIN CONNECTOR 5
3.2 9 PIN FRONT PANEL CONNECTOR 6
4CHANNEL PROGRAMMING AND OPTION SELECTIONS 6
5CIRCUIT DESCRIPTION 7
5.1 R50 MASTER SCHEMATIC (SHEET 1) 7
5.2 M
ICROPROCESSOR
(SHEET 2) 7
5.3 RF SECTION (SHEET 3) 9
5.4 5.4 RECEIVER SECTION (SHEET 4) 10
5.5 VOLTAGE CONTROLLED OSCILLATOR (SHEET 5) 11
5.6 AUDIO PROCESSING SECTION (SHEET 6) 12
5.7 POWER GENERATION SECTION (SHEET 7) 13
6FIELD ALIGNMENT (CALIBRATION) PROCEDURE 14
6.1 STANDARD TEST EQUIPMENT 14
6.2 INVOKING THE CALIBRATION PROCEDURE MANUALLY 14
6.3 THE "MISCELLANEOUS" C
ALIBRATION
PROCEDURE 14
6.4 LINE CALIBRATION PROCEDURE 15
6.5 THE "REFERENCE" CALIBRATION PROCEDURE 16
7SPECIFICATIONS 16
7.1 OVERALL DESCRIPTION 16
7.1.1 Channel Capacity 16
7.1.2 CTCSS 17
7.1.3 DCS 17
7.1.4 Channel Programming 17
7.1.5 Channel Selection 17
7.1.6 Microprocessor 17

RF Technology R50 Page 3
7.2 PHYSICAL C
ONFIGURATION
18
7.3 FRONT PANEL CONTROLS, INDICATORS, AND TEST POINTS 18
7.3.1 Controls 18
7.3.2 Indicators 18
7.3.3 Test Points 18
7.4 ELECTRICAL S
PECIFICATIONS
18
7.4.1 Power Requirements 18
7.4.2 Frequency Range and Channel Spacing 18
7.4.3 Frequency Synthesizer Step Size 18
7.4.4 Frequency Stability 19
7.4.5 Number of Channels 19
7.4.6 RF Input Impedance 19
7.4.7 IF Frequencies 19
7.4.8 Sensitivity 19
7.4.9 Selectivity 19
7.4.10 Spurious and Image Rejection 19
7.4.11 Intermodulation 19
7.4.12 Modulation Acceptance BW 19
7.4.13 Noise Squelch 19
7.4.14 Carrier Level Squelch 19
7.4.15 Receiver Frequency Spread 20
7.4.16 Receiver Conducted Spurious Emission 20
7.4.17 Audio Frequency Response 20
7.4.18 Audio Output Level 20
7.4.19 Audio Distortion 20
7.4.20 Channel Select Input/Output 20
7.4.21 Carrier Operated Switch (COS) Output 21
7.4.22 COS Output Current Source/Sink, Collector Voltage 21
7.4.23 CTCSS 21
7.4.24 DCS 21
7.4.25 External Squelch Input 21
7.5 CONNECTORS 22
7.5.1 Antenna Connector 22
7.5.2 Power & I/O Connector 22
7.5.3 Test Connector 22
Appendix A EIA CTCSS Tone Frequencies 28
Appendix B Parts List 29
Appendix C Engineering Diagrams
C.1 Block Diagram
C.2 Circuit Diagrams
C.3 Component Overlay Diagrams

Page 1 RF Technology R50
1 OPERATING INSTRUCTIONS
1Operating Instructions
1.1 Front Panel Controls and Indicators
1.1.1 Monitor Volume
The Mon. Volume control is used to adjust the volume of the internal loudspeaker and
any external speaker connected to the test socket. It does not effect the level of
the 600 Ohm line output level, nor the direct audio output level.
1.1.2 Monitor Squelch
The MON. SQ. switch allows the normal squelch functions controlling the monitor
output to be disabled. When the switch is in the MON. SQ. position the audio
at the monitor speaker is controlled by the noise detector. The CTCSS, carrier,
tone, DCS, and external squelch functions will not stop the audio from being
broadcast by the speaker. This can be useful when you are trying to trace the
source of on channel interference or when setting the noise squelch threshold.
The audio from the
600 Ohm line output, and the direct audio output, is not
effected by the switch position.
1.1.3 N.SQ
The N.SQ trimpot is used to set the noise squelch sensitivity. Use the following
procedure to set the noise squelch to maximum sensitivity.
(a) Set the toggle switch to the MON.SQ. position and set the MON VOLUME
control to 9 o'clock.
(b) Turn the N.SQ.
adjustment counter clockwise until the squelch opens and noise is
heard from the speaker. Adjust the VOLUME to a comfortable listening level.
(c) In the absence of any on channel signal,
Turn the N.SQ.
screw clockwise until the
until the noise in the speaker is muted.
WARNING
Changes or modifications not expressly approved by RF
Technology could void your authority to operate
this equipment. Specifications may vary from those
given in this document in accordance with
requirements of local authorities. RF Technology
equipment is subject to continual improvement and
RF Technology reserves the right to change
performance and specification without further
notice.

Page 2 RF Technology R50
1.1.4 C.SQ
The C.SQ trimpot is used to set the carrier squelch sensitivity. Carrier squelch is
useful at higher signal levels than noise squelch and can be used from 1 - 200
uV input.
It is provided mainly for use in fixed link applications where
a high minimum signal
to noise ratio is required or where very fast squelch operation is required for
data transmission. The carrier squelch will open and close in less than 2 mSec.
In most base station applications carrier squelch is disabled by turning the adjustment
counter clockwise until the screw clicks.
The carrier squelch may be set to a predetermined level with the
WinTekHelp
software or by using the following procedure:
(a) First turn the adjustment fully counter-clockwise. Then set the noise squelch as
above.
(b) Connect a source of an on channel signal with the desired threshold level to the
receiver's RF input.
(c) Turn the screw clockwise until the SQ LED goes OFF. Then turn the screw back
until the LED just comes ON.
1.1.5 LINE
The LINE trimpot is used to set the line and direct audio output levels. It is normally
set to output 0dBm on the Line output when the carrier is modulated with a
1kHz audio signal at 60% of maximum deviation. NB that 0dBm is equivalent
to 774 mV to an open circuit, or 387mV into a 600 ohm load.
1.2 Front Panel Indicators
1.2.1 PWR LED
The PWR LED shows that the dc supply is connected to the receiver and that the
microprocessor is not being held in a RESET state.
1.2.2 SQ LED
The SQ LED comes on when the audio to the line and direct outputs is un-squelched.
The LED and squelch function are controlled by the external squelch input, and/or the
noise, carrier, tone, or DCS squelch circuits.
1.2.3 ALARM LED
The ALARM LED can indicate several fault conditions if they are detected by the self
test program. The alarm indicator shows the highest priority fault present.
See Table 1.
LED Flash Cadence Fault Condition
5 flashes, pause Synthesizer unlocked
4 flashes, pause Tuning volts out of range
3 flashes, pause Low RSSI
2 flashes, pause
The current channel is not programmed or the frequency

RF Technology R50 Page 3
is out of range.
1 flash, pause Low dc supply voltage
LED ON continuously External squelch is active
Table 1: Interpretations of LED flash cadence
2Receiver Options
There are many software selectable options. Some options are selected on a per
channel basis, and some are defined globally (i.e. the parameter is fixed
irrespective of which channel is selected). Below is a description of these
global parameters
2.1 Serial I/O Parameters
There are two serial ports. There is the main serial port which is brought out to the
front panel connector. This is referred to as PORT0. There is another serial
port which is for factory use only. It is referred to as PORT1.
The baud rate, can be defined for PORT0. PORT0 is set by default to 57.6Kbps, with
No parity.
2.2 Receiver Low Battery Level
This is factory set to 24.0V, and defines the level of the DC supply that will cause a
Receiver dc supply low alarm.
2.3 LOOP Volts Select
By default, when the squelch opens and the Line output audio is enabled, 12V is
applied to the
Line+/Line- pair through 680 ohms. The 12V power source is
removed when the squelch closes.
In Rev. 2 receivers, the user can select to reverse the application of 12V,
ie 12V
is
applied when the squelch is closed, and removed when the squelch opens.
In Rev. 3 (or later) receivers, the user can select to apply a DC loop to the
Line+/Line-
pair instead of applying 12V. Similarly, they can select to reverse the
application of the Loop, or the voltage, depending on the squelch state.
2.4 COS Source/Sink Select
The COS output can have four possible states:
a)
12V: 12V is applied to COS+/COS- through 680 ohms,
b) 0V: ie COS+ is shorted to COS- which is shorted to GND,
c)
shorted: COS+ and COS- are shorted together, but both are electrically
isolated,
d)
open: COS+ and
COS- are not shorted together, but both are electrically
isolated
In states (a) and (b), the receiver applies either 12V to the COS+ pin, or GND. The
COS- pin is connected to GND in both states. The receiver acts as a “source”
when in either of these two states.

Page 4 RF Technology R50
In states (c) and (d), the COS+/COS- pair can “sink” current, or not sink current, that
is sourced elsewhere.
The receivers will either toggle between states (a) and (b), or toggle between states (c)
and (d), depending on the state of the squelch.
The user can select which of these two modes they wish to use.
The default COS mode is to toggle between states (a) and (b)
2.5 COS Polarity
By default, +12V is applied to COS+ when the squelch opens, and COS- is connected
to ground,
ie the COS+/COS- pair are placed into state (a) when the squelch
opens, and are in state (b) when it is closed. (see 2.4 above).
The user can optionally select to reverse this.
Similarly,
if , the user has chosen to operate COS as a “sink” (see 2.4 above), the
default is to short COS+ to COS- when the squelch opens (state (c) above), or
open them when the squelch closes. The user can reverse this as well.
2.6 Noise Blanker
The R50 has a noise blanker. This circuit detects RF impulses and quenches the RF
before it is de-modulated. This prevents “clicks” and “pops” from being
detected and passed through to the audio. The noise blanker can be enabled or
disabled by the user.
2.7 Advanced Slot Selectable Parameters
WinTekHelp receivers have several advanced features. These features can be
programmed for each channel.
One of these advanced features is to program up to 8 frequencies on a channel. When
this is done, we refer to the “channel” as a “slot” to avoid confusion, as many
people equate the word “channel” with the word “frequency”.
When more than one frequency is assigned to a “slot”, and that slot has been selected
from the channel input, the receiver will automatically scan all the assigned
frequencies, tuning to the first that has sufficient carrier strength and/or
SINAD, and a correct CTCSS tone, or correct DCS code.
In this “scanning” mode, one of the frequencies can be given “priority”. If this is
done, the receiver will check, every few seconds, if there is a signal on the
priority frequency, and if so, it will switch to the priority frequency. It will
stay tuned to the priority signal, whilst signal is present on it, but it will then
resume its usual scanning function, if the signal is lost.
Another advanced feature is the ability to assign more than one CTCSS tone to a
frequency. When this is enabled, the receiver checks if the received CTCSS
tone is one of up to 6 tones rather than just one.
Another advanced feature is to inhibit the assertion of COS, or loop, (or both) when
the squelch opens depending on either the frequency received or the tone
detected.
For example, in a scanning situation, with two possible frequencies, LOOP can be
programmed to be asserted if one frequency is detected, or
COS to be asserted

RF Technology R50 Page 5
if the other frequency is detected. Similarly, one
can enable/disable the default
assertion of COS and/or loop depending on which CTCSS tone is detected.
Other advanced features are:
a) de-emphasis: enabled or disabled, depending on frequency
b) start and end delays for COS and LOOP.
c) scanning interval for the priority frequency,
d) increments or decrements in the carrier level or noise level thresholds,
depending on the frequency. For example one frequency can be set to have a
higher noise threshold than another. Units are in dB of carrier signal, or
SINAD dB.
2.8 Standard Channel Parameters
Each channel can set the following standard parameters:
a) frequency,
b) one CTCSS tone, or DCS code.
3Receiver I/O Connections
3.1 25 Pin Connector
The female D-shell, 25 pin, connector is the main interface to the transmitter. The pin
connections are described in Table 3.
Function Signal Pins Specification
DC Power +28Vdc(in)
0 Vdc
+5Vdc(out)
+12Vdc(out)
Vref
13, 25
1, 14
17
15
4
+15 to 32 Vdc
Common Voltage
Output for external
Logic(100mA)
Output for an external
relay(120mA)
Reference voltage
Serial Communi
cations
SCLK
MOSI
CH_EN
SPARE_I/O1
SPARE_SEL
12
6
18
16
5
Serial Clock
Bi-directional Data Pin
Enables Channel Select
Shift Register
Spare Input or Output
(for future use)
Spare Select (for future
use)
600ΩLine
Output Line+
Line- 8 19 Transformer Isolated
Balanced 600
Ω
0dBm Output
Carrier Operated
Switch
Output
COS+
COS-
10
22
Opto Coupled Transistor
Switch Output
(10mA)
External Squelch
Input EXT_SQ 11
<1 VDC to force the
squelch to close.
>2 VDC or open ckt, to
enable the squelch

Page 6 RF Technology R50
to open
External Speaker
Output EXT_SPK 24
AC Coupled External
Speaker Output,
5W @ 4ΩLoad
Direct Audio
Output DIR_AUD 21 >10kΩ
, AC Coupled
Audio Output
2Vp-p @ 3kHz
System Deviation
Discriminator
Audio
Output
DISC_AUD 20 >10kΩ
, AC Coupled
Un-
Squelched 2Vp-p
@ 3kHz System
Deviation
Sub-Audible
Tone
Output
SUBTONE 9>10kΩ
, AC Coupled
Un-
Squelched, 2Vp-p
@ 3kHz System
Deviation
Table 3: Pin connections and explanations for the main 25-pin, D connector
3.2 9 Pin Front Panel Connector
The female D-shell, 9 pin, front panel connector is an RS232 interface for serial
communications to a terminal, a terminal emulator, or to a computer. The pin
connections are described in table 4.
Function Pins Specification Pin name on IBM PC
TXD 2
Transmit Data (Output)
RxD
RXD 3 Receive Data (Input) TxD
RTS 8Request To Send (Output) CTS
CTS 7Clear To Send (Input) RTS
DTR 6 Data Terminal Ready(Output) DSR
DSR 1 Data Set Ready (Input) DCD
GND 5 GND GND
Table 4: Pin connections for the front panel 9 pin D connector
The pinout for the connector has been chosen so that a straight-through BD9 male to
DB9 female cable can connect the transmitter to any male DB9 serial port on
an IBM PC compatible computer.
Note that for connection to a modem, a
cross-over cable will be required.
4
Channel Programming and Option Selections
Channel and tone frequency programming are most easily accomplished with RF
Technology WinTekHelp software. This software can be run on an IBM
compatible PC and can be used to calibrate a T50, R50, and PA50 as well as

RF Technology R50 Page 7
program channel information. See the
WinTekHelp
users manual for further
information.
5Circuit Description
The following descriptions should be read as an aid to understanding the block and
schematic diagrams given in the appendix of this manual.
There are 7 sheets in the schematic in all.
5.1 R50 Master Schematic (Sheet 1)
Sheet 1, referred to as the "R50 Master Schematic", is a top level sheet, showing four
circuit blocks, and their interconnection with each other, as well as the
interconnection with all connectors and external switches.
P1 is the front panel DB9 RS-232 connector for attachment to a terminal, a terminal
emulator, or to an IBM PC running the WinTekHelp software.
P3 represents the rear female DB25 connector.
J1 is the terminal on print circuit board, it is connected to the internal load speaker.
JP2 is for the attachment of
an LCD display module. This has been included for later
development.
JP3 is a specialised connector for test and factory configuration use only.
D102, D103, and D104 represent the three front panel LEDs.
5.2 Microprocessor (Sheet 2)
Sheet 2 describes the basic microprocessor circuitry.
The core CPU is the Motorola XC68HC12A0. It is configured in
8 bit data width
mode.
The CPU is clocked by a 14.7456MHz crystal oscillator circuit (top left) comprising
the JFET Q202, and two switching transistors Q203 and Q204.
The CPU contains an 8 channel A/D converter whose inputs are identified as AN0,
AN1, …, AN7.
AN7 is used as LOCK detect inputs from the Locked Loop (PLL) circuits (see 5.6)
AN6 is used to sense the noise squelch level setting.
AN5 is used to sense whether or not the dc supply is within spec or not.
AN4 is used to sense the audio from the discriminator, so the R50 receiver can be
used as a deviation meter.
AN3 and AN1 are inputs from the PLL circuits that sense the bias voltage on the VCO
control varactor for each VCO.
AN2 is used to sense the carrier squelch level setting.
AN0 is used to sense the RF input signal strength which is detected by the IF chip.
FRDY is an output from the flash. It goes low when the Flash starts to write a byte of
data, or erase a block, or erase the whole chip, and it returns to its default high
state when the action requested has completed.

Page 8 RF Technology R50
FPSW1, FPSW2 and FPSW3 are three pins that have been reserved for future use as
switch inputs.
LOOP/VOLTS_SEL is a CPU output that when high applies 12V of dc feed to the
audio output.
LINE_LEVEL_U/D and LINE_LEVEL_INC are CPU outputs which are reserved for
controlling a digital potentiometer in future.
COS_VOLTS_ON/OFF is a CPU output that when high applies 12VDC feed to
COS+ terminal, so that the COS can be selected as +12VDC source or a free
switch.
COS_POLARITY is CPU output that when low turns
Opto-coupled
transistor switch
U601on. It is controlled by the noise squelch detect, carrier squelch, or
external squelch signal
SQ is a CPU output that when low, enables the 600 ohm line output, and the direct
audio output. It is controlled by the noise squelch detect, carrier squelch, or
external squelch signal
N_BLK_EN is a CPU output that when low turns noise blanker option off.
CTCSS_SEL is a serial bus select pin. It is used to select the FX805 chip(U500),
which is used to decode CTCSS tones. (see 5.5)
PLL_SEL is a serial bus select pin. It is used to select the PLL chip in the PLL circuit
(U302). (See 5.6)
RCV_ADSEL is a serial bus select pin. It selects the quad Digital to Analogue
converter (DAC) that sets the levels for the 12MHz reference oscillator bias
voltage, 21.855MHz oscillator bias voltage, noise squelch
comparator bias
voltage and the LCD bias circuit. (see 5.4)
CH_EN is a serial bus select. It is brought out to the rear panel and is used to
interface to the channel encoder on the rear daughter-board. (See 5.1)
FLAT and DE_EMPHA are outputs which are the logical inverse of one another.
When the FLAT pin is low, the audio output is flat response, when
DE_EMPHA pin low, audio is 750uSec de-emphasized.
Fo_PLL is derived from the
the Fo output
of the PLL chip. It is Fo after being
divided by 100. They should be 312.5Hz square waves, except for brief
periods when frequencies are being changed. (See 5.6)
MON_SW is a digital
input which represents the state of the front panel MON.SQ
switch.
LCD_DB7 is a signal that has been reserved for interfacing to an LCD display.
ECLK is a pin that at start-up only, should have the CPU system clock of 7.3728MHz
on it.
SQ_LED, ALARM_LED, are CPU outputs that drive (when low) the SQ LED, and
the ALARM LED.
T/R_RELAY_H is a spare pin which is not used in the R50 receiver.
SCLK, and MOSI are used as the core of a serial bus. SCLK is a clock pin, and
MOSI is a bi-directional data pin.
DBGTX_TTL, DBGRX_TTL are RS232 transmit and receive (TTL) data pins which
are connected to the debug port after conversion to/from RS232 compatible
voltage levels by U202 and U201.

RF Technology R50 Page 9
TXD_TTL, RXD_TTL, RTS_TTL, CTS_TTL, DTR_TTL, DSR_TTL, are RS232
data pins which are connected to the main front panel serial port, after
conversion to/from RS232 compatible voltage levels by U202 and U201.
N_DET is used to sense the noise squelch output of the receiver section. (see)
SUBTONE_IRQ is connected to the interrupt pin of the FX805 (U500). When
CTCSS tones change state, ie a new tone is detected, or an existing tone stops
being received, or 8 bits of NRZ data (when decoding DCS codes) are
received, this signal is asserted to force the CPU to read data from U500.
INT is a dedicated CPU interrupt input pin. It is used to detect the state of the external
squelch signal.
BKGD is a bi-directional I/O pin used to communicate with the core of the CPU. It is
connected to the debug port and is utilised by specialised hardware to control
the CPU externally, even without any firmware being present in the Flash.
The RESET pin is both a low active input and a low active output to the CPU. If
generated externally to the CPU, it forces the CPU into reset, and if the CPU
executes a RESET instruction
this pin will be driven low by the CPU.
Whenever there is insufficient volts (< 4.65V) on pin 2 of the MC33064D (U203), it
will keep its RES output low. After the voltage has met the right level it will
assert its output low for another 200 milliseconds. Thus the CPU will be held
in reset until VCC is at the correct level. Thus the PWR_OK LED will only
light when VCC is within specification, and RESET has been released.
S200 is a momentary push-button switch that, when pressed, will cause the CPU to be
reset.
MON_SQ is a CPU output which is used to enable (when low), or disable (when high)
the audio at the monitor speaker.
LCD_RS, LCD_R/W, and LCD_E are reserved for interfacing to
an LCD display
module. Note that this feature has not been implemented.
U205 is used to select whether the Flash or RAM is to be read or written.
U207 is a single supply, 5V, TSOP40 Flash chip of size 8, 16, or 32 Megabits, and is
used to store the firmware.
U208 is a 1, or 4
, Megabit Static RAM in an SOP-32 package, and is used for both
code and data. The code in the RAM is copied from the Flash, at start-up.
5.3 RF Section (Sheet 3)
Sheet 3 is a schematic of the RF section, which itself refers to two other
subsheets.
U301 is a quad Digital to Analogue converter (DAC). OUTA (pin2) is used to adjust
the 3rd local oscillator frequency. OUTB (pin1) is used to adjust the frequency
of the 12MHz reference. OUTC(pin16) is used to set the noise squelch
comparator offset voltage. OUTD (pin15) is reserved for future use.
Communication between U301 and the
MicroController, U204, is via the serial
bus.
U302 is a dual channel PLL chip, X301 is the reference for both PLL channels. PLL
channel 1 is for the 1st VCO, and channel 2 is for the 2nd VCO. C315, C317,
C327, R316 and R317 are components of the loop filter for the 1st VCO,
C316, C328, C329, R330 and R331 are for the loop filter of the 2nd VCO.

Page 10 RF Technology R50
U303A, U303D are buffers that isolate the bias voltage. The Microcontroller,
U204, has both of these buffered voltages connected to two of it’s A/D ports.
U304A, U304B divide the FoLD
of the PLL chip by 100, and send it to a Timer input
pin of the MicroController, U204.
5.4 Receiver Section (Sheet 4)
The RF input signal (25MHz-50MHz) is first filtered with a band-pass filter. This is
implemented with two filters, firstly a high pass filter (C401, C402, C403,
C407, C415, C416, C417, C419, C420 and L401, L404, L405, L406) and then
a low pass filter (C404, C405, C406, C421, C422 and L402, L403, L407,
L408).
After band-pass filtering, the signal is amplified. Q401 is the front-end amplifier.
After amplification, unwanted products generated by the amplifier are filtered.
The capacitors and coils between Q401 and C457 provide this additional
filtering for the RF signal amplified by Q401.
This amplified RF input signal is referred to on the schematic as RF_AMP. It is up-
converted by mixer MX401 to create the 1
st IF.
It is also amplified by Q405,
and Q406, which are the front-end amplifiers for the Noise Blanker circuit.
The output of Q406 is “detected” by D401, and if the waveform “envelope” exceeds
approximately 3.3V, the output of U403 will go high. U404 is a retriggerable
monostable multivibrator, which produces a pulse at least 2usecs long after
each rising edge detected on the output of U403. If rising edges re-occur
during each pulse, the pulse period keeps extending until they stop.
The output of U404 is level shifted and inverted by Q408 to create the blanking signal
N_BLK. C470, R416, and R414, act to slew the negation of N_BLK, without
affecting the slew rate of the assertion of N_BLK.
U303C provides some AGC for the RF amplifier formed by Q405 and Q406. They
also reduce the intermodulation which is produced by Q405 and Q406.
MX401 is a double balanced mixer which converts the RF signal to the 1st IF. The
frequency of the 1st IF is at least three times higher than the highest RF
frequency to obtain good image and spurious rejection. In the R50 receiver, the
1st IF frequency is approximately 246MHz. The actual frequency depends on
the frequency tuned to, and may vary by as much as +/- 120kHz. The 1st LO is
set to be approximately 264MHz above the frequency being tuned to.
Q402 is used to amplify the 1st IF signal before it is filtered by FIL401.
FIL401 is a SAW filter, which provides an excellent spurious rejection for the 1st IF.
The filtered IF signal is then fed to double balanced mixer MX402. The output of
MX402 produces the 2nd IF, which is then amplified by Q403. The 2nd IF
frequency is set at exactly 21.400MHz, to avoid interference from any in-band
RF signals. The 2
nd
LO is set to approximately 224.6MHz. Again the LO
frequency may vary from 224.6MHz by as much as +/-120kHz depending on
which frequency the receiver is tuned to.
Q404 and Q409 gate the 2nd
IF signal. If the N_BLK signal is high, then the 2
nd IF is
quenched. N_BLK is generated by the impulse noise detector.
FIL404 and FIL405 are two 21.4MHz crystal filters. Combined they form a four pole
crystal filter. The filter has a minimum of 40dB attenuation at the adjacent
channel frequencies (25kHz channel spacing). C448, C477, L423 and

RF Technology R50 Page 11
components between FIL405 and U401 form the matching network for the
filter.
U401 is an IF receiver IC which includes mixer, oscillator, amplifiers and
discriminator. It down-converts the 2
nd
IF to the 3
rd
IF at 455kHz, which is
filtered by ceramic filters FIL402, and FIL403, before the signal is
demodulated(discriminated). The discriminator uses ceramic resonator X401
as its 455kHz reference.
X402 is a crystal used to create a 21.855MHz oscillator that becomes the 3rd
LO. The
frequency can be varied slightly by
varactor
D406, and thus it can be adjusted
by the 3rd_LO_ADJ voltage. This is done as part of calibration.
Pin9 of U401 is the recovered audio output. C411, C412, C413, R441, R444 and
U402A form a 5
th order
ellyptical high pass filter with 3dB cut-off at 7.5kHz.
Any “signal” at such frequencies is assumed to be noise, as exciters sharply
attenuate all signals above 3kHz. U402B amplifies this FM “noise” signal, and
D403 and C438 act as a peak detector. The voltage on C438 is proportional to
the square root of the noise energy. U402C works as a comparator
which
asserts the low active digital signal, N_DET, if the noise voltage is higher than
the D/A output, NSQ_SET.
Pin8 of U401 is the other recovered audio output which can be muted by pin5.
Capacitor C484, and D407, ensure that the audio remains muted until the
+10V is at the right voltage. The discriminated audio signal is amplified by
U605A and then fed into the Audio Section (Sheet 6).
Pin7 of U401 is the Radio Signal Strength Indicator (RSSI) output. U402D is a buffer.
The RSSI voltage is converted to a digital value by one of the A/D inputs of the
MicroController.
5.5 Voltage Controlled Oscillator (Sheet 5)
There are two similar VCO circuits in this sheet, the difference between these two
VCO is component values, so only one VCO circuit is illustrated in this
section.
Q501, C532, C533, C534 and L501 form a Colpitts oscillator, the frequency of the
oscillator is decided by the tuning voltage of varactor D501. The capacitance
of D501 is in series with C531, and this total capacitance is in parallel with
C501 and also with the series connection of the feedback capacitors C533 and
C534. The net capacitance forms a tank resonance with the, high Q, air coil
inductor, L501.
The bias for varactor D501 comes from the loop filter of the 1st PLL. Q503 forms a
gyrator circuit which reduces noise that might be injected from the power
supply.
The parameter,
Vgs(off), of Q501 can vary from 1 to 4V. D503, R517 and C519
provide some AGC, in order to reduce the dependence of the output level on
this parameter.
MMIC amplifier MA501 provides about 20dB gain for the VCO signal and feeds it to
the PLL chip.
MA502 and MA503 provide about 30dB gain of the VCO signal to drive the LO port
of the double balanced mixer MX401 at a nominal level of +7dBm.
NB that Q506, R547, R531, L508, C510, C540, R537, and R536 are not fitted. Place
for these components has been provided on the printed circuit board to allow

Page 12 RF Technology R50
the possibility of replacing MX401 with a mixer that requires a higher level of
LO drive (but an improved IP3 figure).
5.6 Audio Processing Section (Sheet 6)
The discriminator output from the RF section is connected, in this audio section, to a
peak detector formed by U604 and C623. This peak detector output is passed
to an A/D input of the Microcontroller to be used as a simple deviation meter.
This raw detected audio is then attenuated by R642 and R655 before being filtered.
This attenuation is required to ensure that the audio signal will fit into the
dynamic range limitation of the CTCSS chip, U602.
The raw, unfiltered Discriminator Audio signal is attenuated by R658 and R657
before being connected to the rear panel connector P3.
U605B, R642, R643, R644, C626, C627 and C628 form a 5th order
ellyptical low pass
filter with 3dB cut-off at 4.2kHz.
U602 is a CTCSS tone encoder and decoder. U602 can receive and transmit NRZ
data, and as such can be used, with suitable firmware, to receive or detect DCS
codes.
The CPU accesses U602 via the serial bus using MOSI, SCLK, and the low active
Select signal CTCSS_SEL. When U602 detects new CTCSS tones, or detects
the absence of a tone, or receives bytes of NRZ data, it signals the
Microcontroller by asserting the low active signal SUBTONE_IRQ.
The 4MHz crystal, X401, is used as the reference for decoding CTCSS tones, or
setting the bit rate for NRZ data. U602 has a built-in high pass filter, between
pins 10 and 11, which can eliminate any subtone, or low frequency NRZ data.
Whilst the Microcontroller can enable or disable this filter, in the R50, it is
always enabled. The subtone output from Pin17 is amplified by U605C. The
output from U605C is ac-coupled to the rear panel connector P3, through
capacitor C604.
The audio paths in U602 are all dc-biased to Vcc/2. The audio paths before and after
U602 are zero-biased.
U609B is set up as an inverting amplifier with a nominal gain of unity at 1kHz. If the
signal FLAT, is asserted low, analogue switch U607A is enabled. This sets the
gain at unity across the audio band. If, on the other hand, the digital signal
DE_EMPHA is asserted low, analogue switch U607B is enabled, and the gain
becomes proportional to frequency. Thus de-emphasis is applied to compensate
for any pre-emphasis applied at the exciter.
The audio is connected to the Line outputs and the DIR_AUD output, when the digital
signal SQ is asserted low.
The audio is connected to the speaker amplifier when the digital signal MON_SQ is
asserted low.
U609C is the amplifier for the 600 ohm line output. U609D is the amplifier for the
direct audio output (DIR_AUD). The output level of the
600 ohm output is
adjustable via VR601 on the front panel.
U604 is the power amplifier for internal and external speaker. The volume can be
adjusted by VR602 on the front panel.
RL602 may apply, or remove, 12VDC to the 600 ohm line output. Whether this
occurs or not, and whether the voltage is applied when the squelch opens or

RF Technology R50 Page 13
closes depends on the way in which the channel is programmed by the user.
The position of RL602 is controlled by the signal LOOP/VOLTS_SEL from
the MicroController.
Opto-coupled transistor switch U601 provides a COS (Carrier Operated Switch)
output which is controlled by the digital COS_POLARITY
signal from the
MicroController. The output COS+ and COS- can be used as +12V DC source
or a free switch depending on the status of the relay RL601. RL601 is
controlled by the digital COS_VOLTS_ON/OFF signal from the
MicroController.
5.7 Power Generation Section (Sheet 7)
U909 converts the +12V rail to +5V for all the digital circuitry.
The +12V rail is used to power the two on-board relays, as well as up to one extra off-
board relay. It is also dropped, via a linear regulator (U910) to produce the
+10V rail, which in turn is dropped by another linear regulator U911 to
produce +5Q, which, in turn, is dropped by a further linear regulator (U912) to
produce +2.5V.
Similarly U913, U914, and U915 are linear regulators that produce –10V, -5V, and –
2.5V from the –12V output of U908.
+10, +5Q, and +2.5V, -10V, -5V, and –2.5V rails are used in the audio and RF
sections.
D911 is a 4.096V (3%) reference diode. Its output is buffered by U906 which then
produces a reference voltage rail Vref, which is used by the CPU’s A/D
converter, and the
DACs, and also in the voltage to current converters of the
VCAs (see Sheet 4, and Sheet 7).
There are three switch-mode dc-dc converters in the board. These use monolithic
converters based on the National LM2595. Two of the converters are 12V
converters and one is a 5V converter.
The power in to the whole exciter is the voltage rail 28V.
U907 converts this down to 12V.
U908 is set up as an inverter, and uses the 12V rail to create -12V.
U909 converts the +12V rail to +5V for all the digital circuitry.
The +12V rail is used to power the two on-board relays, as well as up to one extra off-
board relay. It is also dropped, via a linear regulator (U910) to produce the
+10V rail, which in turn is dropped by another linear regulator U911 to
produce +5Q.
Similarly U913 and U914 are linear regulators that produce -10V and -5V from the -
12V output of U908.
NB -2.5V is not used in the R50 receiver. In case, it is ever required in a future
release of the R50, it has been included in the schematic.
U915, though is not
fitted to the printed circuit board.
D911 is a 4.096V (3%) reference diode. Its output is buffered by
U906 which then
produces a reference voltage rail Vref, which is used by the CPU's A/D
converter, and the DACs.

Page 14 RF Technology R50
6Field Alignment (Calibration) Procedure
6.1 Standard Test Equipment
Some, or all of the following equipment will be required:
•Power supply set to 28Vdc, with current >0.25A.
•
RF Signal Generator with 50 Ohm Output impedance, and Frequency range
25-50MHz. The signal generator must be capable of generating a carrier aith
output level adjustable from –60dBm to –128dBm. It must be able to FM
modulate the carrier with a 1kHz audio signal with deviations of 3 and 5kHz.
•
Frequency Counter, or spectrum analyser, capable of measuring frequency
accurate to 0.5ppm.
•True RMS AC voltmeter with bandwidth > 20kHz, and,
•a DC voltmeter.
6.2 Invoking the Calibration Procedure Manually
From Version 4 of the firmware, and version 1.4 of WinTekHelp, the calibration
procedure can be performed through a Windows front end program. This is
documented in the
WinTekHelp manual. It is recommended that you use the
new Windows based procedure for calibrating each R50.
The firmware still supports the older command prompt method, which is described in
this section.
The firmware will requests the user for information as to meter readings, and/or to
attach or adjust an AF signal generator.
The firmware based calibration program can be accessed from a terminal, a terminal
emulator, or the WinTekHelp terminal emulator.
If the user selects the “Go to the Prompt Window” option from the main menu, they
can manually type commands to invoke the calibration procedure. When the
exciter is ready to accept commands it echoes the following prompt:
R50>
Via a terminal, or a terminal emulator, a user can type various commands in. The
basic command to start the calibration procedure is:
R50> cal
calibration_type
Where "
calibration_type" is one of:
(a) misc:
Miscellaneous parameters are defined and calibrated
(b) line:
Line1, Line2,
Dir
Aud (Tone), and microphone inputs are
tested and calibrated.
(c) ref:
The reference oscillators are adjusted and calibrated
6.3 The "Miscellaneous" Calibration Procedure
R50> cal misc
This procedure should not normally be invoked as part of any field maintenance.
The program will print out the Model Name and Serial Number of the exciter. If these
parameters haven't already been defined (e.g. at an initial calibration, at the
factory, the service personnel will be prompted to enter these values).

RF Technology R50 Page 15
Then it will ask the operator to enter the value of Vref (as measured at TP913, see
5.7).
Measure the voltage, at TP913 (Vref)
and type it on the command line...
Unless the reference diode D911 has been replaced, this should not be done. The user
should simply hit the Enter key to bypass this operation. If, though, D911 has
been replaced for some reason, then, the lid of the unit should be removed, and
the voltage measured. TP913 can be found just above JP12 (near the centre of
the exciter).
Then the receiver low battery alarm level will be asked for. If the current value is
acceptable, the User need only hit the Enter key on the keyboard. If another
value is preferred, then that value can be typed in.
For example:
The Exciter's LowBattery Alarm is 24V
If this is correct enter <RET>,
else enter the newvalue: 26
In this example, the low Battery Alarm level is changed to 26V.
Then the user will be prompted for serial port baud rates, etc. Please leave these
parameters unchanged unless you are familiar with how to change such
parameters on your PC. The WinTekHelp software will expect 57600 BPS,
and No Parity. Note well, that if you do change any of these, the change will
not take effect until you power down the receiver and then power it up again.
(As an alternative to power cycling the receiver, and if the cover is off the
receiver, you may simply press
switch momentary push-button S200 (see 5.2).
Then the following questions are:
Is Flat frequency response on by default (Y/N)?
Is COS purely a sink of current (Y/N)?
Is COS Asserted when the Squelch is closed (Y/N)?
Is COS UnAsserted when the Squelch is open (Y/N)?
Is LOOP Asserted when the Squelch is closed (Y/N)?
Is LOOP UnAsserted when the Squelch is open (Y/N)?
Always hit "Enter key" unless the value other than default is required. Note the user
should use the "Y" key if the default value needs to be changed.
6.4 Line Calibration Procedure
R50> cal line
This procedure is used for calibrating the RF RSSI level reading, FM modulation
(deviation) reading. Also this procedure is used to set the 600 Ohm audio line
output level, Noise squelch level and Carrier squelch level. Simply follow the
instruction of the software as bellow:
Attach an RF signal generator to the input.
Set the RF output to 37.5MHz,
and an input level of -110dBm
with a 1kHz tone and 3kHz deviation.
Adjust the Volume Pot until the DIR AUD output

Page 16 RF Technology R50
is 388mV.(eqvt to 0dBm into 600 ohms)
Enter <RET> when done.
Set the RF signal generator's output to -60dBm
Enter <RET> when done.
rssi_scale is 0.417dBm/dac step, and rssi offset is -137.500dBm)
Adjust the Modulation to only 1KHz max deviation
Enter <RET> when done.
deviation_scale is 1.000dBm/dac step, and
deviation offset is .000dBm
Adjust the Carrier Squelch to the desired level
Enter <RET> when set.
-99.5 --- for example
Enter the Fast Noise Threshold(in dBm):
Enter the Carrier AlarmThreshold(in dBm):
Set the RF generator output to the desired level ( < -105dBm ),
and adjust the N.SQ adjustment counter clockwise
until the squelch opens, thence turn it clockwise
until the noise is muted.
Enter <RET> when done
6.5 The "Reference" Calibration Procedure
R50> cal ref
To compensate for crystal ageing and other parameters that drift, the following
procedure should be performed approximately once per year.
Open the cover of the receiver, find out the test point TP209 on receiver PCB, using a
frequency counter to measure the frequency and follow the instruction as
bellow:
Measure the ECLK frequency, accurate to 0.5Hz
and enter the result(in MHz, eg 7.3727965)
Measure the E clockfrequencyagain, and enter yes(y/Y)
if less than 1Hz from prev. freq, or re-enter the frequency
Connect an RF generator to the input
and with output freq of 37.5MHz and output level of -100dBm
Enter <RET> when done.
7
SPECIFICATIONS
7.1 Overall Description
The receiver is a frequency synthesized, narrow band, HF/VHF, FM unit which can be
used in conjunction with transmitter and power supply modules as a base
station, or it can operate as a stand alone receiver. All necessary control and
600 ohm line interface circuitry is included.
7.1.1 Channel Capacity
Although most applications are single channel, the R50 can be programmed for up to
256 channels, numbered 0-255. This allows a network administrator to
program every receiver, in every site, the same way. By setting each site up to
select which of the 256 channels is appropriate, any receiver can be plugged