Rohm BD71837MWV Guide

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© 2017 ROHM Co., Ltd.
No. 60AP001E Rev.001
© 2018 ROHM Co., Ltd.
No. 61AN002E Rev.001
May.2018
2017.4
Application Note
Power Management IC designed for “NXP® i.MX 8M Quad”
BD71837MWV Platform Design Guide
1. Introduction
BD71837MWV is a Power Management Integrated Circuit (PMIC) available in 68-QFN package and dedicated to the application
powered by 5V input. PMIC includes eight Buck convertors, seven LDOs, one internal load switch and crystal oscillator driver for RTC
clock. These functions are designed to support the specific power requirements from NXP i.MX 8M platform to achieve the required
performance for cost-sensitive applications.
The below figure is the outline of the power map between PMIC and i.MX 8M SoC, showing that all voltage rails required by SoC are
satisfied.
“BD71837MWV Platform Design Guide” provides the guideline for designing PCB including recommendation for the PCB layer stack
up, the components placement and the PCB routings.
To reduce the risk that comes from PCB layout or parts placement, the guideline is strongly recommended to be applied to the PCB
design.
2.7V to 5.5V
BD71837MWV
BUCK1 0.9V / 3.6A
i.MX 8M Quad
i.MX 8M QuadLite
i.MX 8M Dual
LDO1 3.3V / 10mA
Power Mux Switch
1.8V/3.3V / 150mA
LPDDR4 Memory
SD Card
USB /
Li-Ion Battery BUCK2 1.0V / 4.0A
BUCK3 1.0V / 2.1A
BUCK4 1.0V / 1.0A
LDO2 0.9V / 10mA
LDO7 3.3V / 150mA
BUCK6 3.3V / 3.0A
LDO3 1.8V / 150mA
LDO5 1.8V / 300mA
BUCK7 1.8V / 1.5A
LDO4 0.9V / 250mA
LDO6 0.9V / 300mA
BUCK5 1.0V / 2.5A
BUCK8 1.1V / 3.0A
I2C (slave)
Power Mode
Control Signals
Power
Sequencing
Controller
Die temp
UVLO
32.768kHz Crystal Oscillator Driver
Interrupt
VR Fault
Power On Key
Detection
Power On Key
Figure 1.1 The system power map
Figure 1.2 The package image

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Application Note
BD71837MWV Platform Design Guide
© 2018 ROHM Co., Ltd.
No. 61AN002E Rev.001
May.2018
1. Introduction................................................................................................................................................................................ 1
2. Revision History......................................................................................................................................................................... 4
3. Features..................................................................................................................................................................................... 5
3.1. Terminologies...................................................................................................................................................................... 5
3.2. Reference Documents........................................................................................................................................................ 5
3.3. PMIC futures....................................................................................................................................................................... 6
4. General Design Considerations ................................................................................................................................................. 7
4.1. Package Dimension of BD71837MWV ............................................................................................................................... 7
4.2. Pin Configuration ................................................................................................................................................................ 8
4.3. General Stack-up Recommendations................................................................................................................................. 9
4.4. 6-layer Board Stack-up....................................................................................................................................................... 9
4.5. Via Guidelines................................................................................................................................................................... 10
4.6. Placement of PTHs underneath the exposed pad..............................................................................................................11
4.7. Outline for PCB layout ...................................................................................................................................................... 12
5. Platform Power Delivery Guidelines......................................................................................................................................... 18
5.1. Platform Power Delivery ................................................................................................................................................... 18
5.2. General Layout Guideline ................................................................................................................................................. 20
5.2.1. Overall Component Placement.................................................................................................................................. 20
5.2.2. Large Current Loop.................................................................................................................................................... 21
5.2.3. Power GND................................................................................................................................................................ 22
5.2.4. VSYS (Power supply for BD71837MWV analog circuit) ............................................................................................ 22
5.2.5. Other Signal Pattern Precautions .............................................................................................................................. 22
5.2.6. Feedback Sense Lines .............................................................................................................................................. 22
5.2.7. AGND layout.............................................................................................................................................................. 23
5.3. BUCK Convertors ............................................................................................................................................................. 24
5.3.1. BUCK1 (VDD_SoC)................................................................................................................................................... 24
5.3.1.1. Schematic Example ............................................................................................................................................... 24
5.3.1.2. Schematic checklist................................................................................................................................................ 24
5.3.1.3. Parts placement for each decoupling capacitor...................................................................................................... 25
5.3.2. BUCK2 (VDD_ARM).................................................................................................................................................. 25
5.3.2.1. Schematic Example ............................................................................................................................................... 25
5.3.2.2. Schematic checklist................................................................................................................................................ 26
5.3.2.3. Layout Example ..................................................................................................................................................... 26
5.3.3. BUCK3 (VDD_GPU).................................................................................................................................................. 27
5.3.3.1. Schematic Example ............................................................................................................................................... 27
5.3.3.2. Schematic Checklist............................................................................................................................................... 27
5.3.3.3. Layout Example ..................................................................................................................................................... 28
5.3.4. BUCK4 (VDD_VPU) .................................................................................................................................................. 29
5.3.4.1. Schematic Example ............................................................................................................................................... 29
5.3.4.2. Schematic Checklist............................................................................................................................................... 29
5.3.4.3. Layout Example ..................................................................................................................................................... 30
5.3.5. BUCK5 (VDD_DRAM) ............................................................................................................................................... 30

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Application Note
BD71837MWV Platform Design Guide
© 2018 ROHM Co., Ltd.
No. 61AN002E Rev.001
May.2018
5.3.5.1. Schematic Example ............................................................................................................................................... 30
5.3.5.2. Schematic Checklist............................................................................................................................................... 31
5.3.5.3. Layout Example ..................................................................................................................................................... 32
5.3.6. BUCK6 (NVCC_3P3)................................................................................................................................................. 32
5.3.6.1. Schematic Example ............................................................................................................................................... 32
5.3.6.2. Schematic Checklist............................................................................................................................................... 33
5.3.6.3. Layout Example ..................................................................................................................................................... 33
5.3.7. BUCK7 (NVCC_1V8)................................................................................................................................................. 34
5.3.7.1. Schematic Example ............................................................................................................................................... 34
5.3.7.2. Schematic Checklist............................................................................................................................................... 34
5.3.7.3. Layout Example ..................................................................................................................................................... 35
5.3.8. BUCK8 (NVCC_DRAM)............................................................................................................................................. 36
5.3.8.1. Schematic Example ............................................................................................................................................... 36
5.3.8.2. Schematic Checklist............................................................................................................................................... 36
5.3.8.3. Layout Example ..................................................................................................................................................... 37
5.4. LDOs................................................................................................................................................................................. 38
5.4.1. LDO1 (NVCC_SNVS)................................................................................................................................................ 38
5.4.2. LDO2 (VDD_SNVS)................................................................................................................................................... 38
5.4.3. LDO3 (VDDA_1P8/VDDA_DRAM) ............................................................................................................................ 38
5.4.4. LDO4 (VDDA_0P9).................................................................................................................................................... 38
5.4.5. LDO5 (1P8_PHY) ...................................................................................................................................................... 38
5.4.6. LDO6 (0P9_PHY) ...................................................................................................................................................... 38
5.4.7. LDO7 (3P3_PHY) ...................................................................................................................................................... 38
5.4.8. Schematic Examples ................................................................................................................................................. 39
5.4.8.1. Schematic Checklist............................................................................................................................................... 39
5.5. Load SW........................................................................................................................................................................... 41
5.5.1. MUXSW (NVCC_SD2)............................................................................................................................................... 41
5.5.1.1. Schematic Examples.............................................................................................................................................. 41
5.5.1.2. Schematic Checklist............................................................................................................................................... 41
5.6. Crystal Oscillator Driver .................................................................................................................................................... 42
5.6.1. XIN / XOUT / C32K_OUT .......................................................................................................................................... 42
5.6.1.1. Schematic Examples.............................................................................................................................................. 42
5.6.1.2. Schematic Checklist............................................................................................................................................... 42
5.6.1.3. Layout Example ..................................................................................................................................................... 43
5.7. Interfaces.......................................................................................................................................................................... 44
5.7.1. I2C............................................................................................................................................................................. 44
5.7.2. System Control –Reset, Power, and Control Signals................................................................................................ 45
5.7.3. MISC.......................................................................................................................................................................... 46

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Application Note
BD71837MWV Platform Design Guide
© 2018 ROHM Co., Ltd.
No. 61AN002E Rev.001
May.2018
2. Revision History
Table 2.1 Revision History
Revision Number
Description
Revision Date
001
Initial release
May. 1st, 2018

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Application Note
BD71837MWV Platform Design Guide
© 2018 ROHM Co., Ltd.
No. 61AN002E Rev.001
May.2018
3. Features
3.1. Terminologies
Table 3.1 Acronyms, Conventions and Terminologies
Term
Definition
BOM
Bill Of Materials
PMIC
Power Management Integrated Circuit
FET
Field Effect Transistor
I2C
Inter-Integrated Circuit
IRQ
Interrupt ReQuest
LDO
Low Drop-Out Regulator
OCP
Over Current Protection
OVP
Over Voltage Protection
SoC
System-On-a-Chip
3.2. Reference Documents
Table 3.2 Reference Documents
Document
BD71837MWV Datasheet Rev.001.pdf
BD71837MWV Reference Schematic Rev.001.pdf
BD71837MWV Reference BOM Rev001.xlsx
BD71837MWV Reference Layout Rev.001.brd
BD71837MWV Schematic Checklist Rev001.xlsx

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Application Note
BD71837MWV Platform Design Guide
© 2018 ROHM Co., Ltd.
No. 61AN002E Rev.001
May.2018
3.3. PMIC futures
BD71837MWV supply the power required by SoC and peripheral devices for NXP i.MX 8M platform.
Once PMIC powered up, it can be controlled by I2C interface to determine the internal register settings.
The followings explain the features incorporated in the IC.
Voltage Rails
■8ch low power consumption Buck Convertors with Integrated BUCK FETs
Buck1: 0.7V –1.3V / 10mV step (DVS), IOMAX = 3.6A
Buck2: 0.7V –1.3V / 10mV step (DVS), IOMAX = 4.0A
Buck3: 0.7V –1.3V / 10mV step (DVS), IOMAX = 2.1A
Buck4: 0.7V –1.3V / 10mV step (DVS), IOMAX = 1.0A
Buck5: 0.7V –1.35V / 8 steps, IOMAX = 2.5A
Buck6: 3.0V –3.3V / 100mV step, IOMAX = 3.0A
Buck7: 1.6V –2.0V / 8 steps, IOMAX = 1.5A
Buck8: 0.8V –1.4V / 10mV step, IOMAX = 3.0A
■7ch LDO Regulator
LDO1: 3.0V –3.3V / 1.6V –1.9V, IOMAX = 10mA
LDO2: 0.9V / 0.8V, IOMAX = 10mA
LDO3: 1.8V –3.3V, IOMAX = 300mA
LDO4: 0.9V –1.8V, IOMAX = 250mA
LDO5: 1.8V –3.3V, IOMAX = 300mA
LDO6: 0.9V –1.8V, IOMAX = 300mA
LDO7: 1.8V –3.3V, IOMAX = 150mA
■1ch Internal General Switch
Mux Switch: 1.8V/3.3V, IOMAX = 150mA
Serial Interface
I2C interface provides access to configuration registers.
Crystal Oscillator Driver
32.768kHz Crystal Oscillator Driver is included.

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Application Note
BD71837MWV Platform Design Guide
© 2018 ROHM Co., Ltd.
No. 61AN002E Rev.001
May.2018
4. General Design Considerations
This chapter provides general PCB design guidelines such as BD71837MWV general parts placement.
4.1. Package Dimension of BD71837MWV
Figure 4.1 The package dimension of BD71837MWV
BD71837
ROHM
LOT Number
Part Number Marking

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Application Note
BD71837MWV Platform Design Guide
© 2018 ROHM Co., Ltd.
No. 61AN002E Rev.001
May.2018
4.2. Pin Configuration
The pin configuration of BD71837MWV is designed and it will result in the effective routings between PMIC and SoC, memory device
and other components.
Figure 4.2 BD71837MWV pin configuration
Note: (*) EXP-PAD is the power GND for PMIC so it should be soldered to GND plane.
(**) EXP-PAD assigned to 4 corners are also the same potentials with (*) EXP-PAD.
LDO4_FB
LDO4_VOUT
VSYS2
WDOG_B
RTC_RESET_B
BUCK8_FB
BUCK8_VIN
BUCK8_VIN
BUCK8_LX
BUCK8_LX
BUCK7_LX
BUCK7_VIN
BUCK7_FB
IRQ_B
POR_B
C32K_OUT
DVDD
(**)EXP-PAD
(**)EXP-PAD
LDO3_FB
VIN_3P3
LDO3_VOUT
VSYS3
BUCK4_FB
BUCK4_VIN
BUCK4_LX
BUCK3_LX
BUCK3_LX
BUCK3_VIN
BUCK3_FB
AGND
INTLDO1P5
LDO7_VOUT
VSYS1
XIN
XOUT
45
44
43
42
41
40
51
50
49
48
47
46
SDA
33
SCL
32
PMIC_ON_REQ
31
PMIC_STBY_REQ
39
38
37
36
35
34
27
BUCK1_LX
26
BUCK1_LX
25
BUCK2_LX
30
BUCK1_FB
29
BUCK1_VIN
28
BUCK1_VIN
21
BUCK2_FB
20
PWRON_B
19
LDO1_VOUT
24
BUCK2_LX
23
BUCK2_VIN
22
BUCK2_VIN
18
LDO2_VOUT
1
2
3
4
5
6
7
8
15
16
17
11
12
13
14
55
9
10
56
BUCK6_VIN
57
BUCK6_VIN
58
BUCK6_LX
68
LDO5_VOUT
(*)EXP-PAD
(PGND)
1Pin Mark
65
VIN_1P8_2
66
MUXSW_VOUT
BUCK6_FB
(**)EXP-PAD
(**)EXP-PAD
67
MUXSW_VOUT
62
BUCK5_VIN
63
BUCK5_VIN
64
BUCK5_FB
59
BUCK6_LX
60
BUCK5_LX
61
BUCK5_LX
52
VIN_1P8_1
53
LDO6_VOUT
54
SD_VSELECT

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Application Note
BD71837MWV Platform Design Guide
© 2018 ROHM Co., Ltd.
No. 61AN002E Rev.001
May.2018
4.3. General Stack-up Recommendations
Type-3 and 6 layers PCB technology are used for BD71837MWV ROHM’s EVM.
The following general stack-up is strongly recommended to be applied to all the routings on the PCB.
Surface plane layers are recommended to apply 1.9 Mils thick copper.
Internal plane layers are recommended to apply 1.2 Mils thick copper.
It is recommended I2C signals to have the reference versus solid planes over the length of their routing and not to
cross plane splits. Ground should be the ideal reference.
The extra area in each layers should be filled with as much ground or other power rails as possible.
There should not be any large free areas with no metal for each layer because of the improvement for heat
dissipation. Large metal area also reduces stray resistance and inductance.
4.4. 6-layer Board Stack-up
BD71837MWV ROHM’s EVM uses Type 3 PCB technology and Figure 4.3 shows the 6-layer PCB stack-up.
Figure 4.3 6-layers PCB stack-up

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Application Note
BD71837MWV Platform Design Guide
© 2018 ROHM Co., Ltd.
No. 61AN002E Rev.001
May.2018
4.5. Via Guidelines
This section explains proper via-drill, pad, and anti-pad size.
Note:
Improper drill, pad, and anti-pad size may cause some troubles on the PCB cost, reliability, manufacturability, and electrical
characteristics.
Type-3 PCB technology employs plated through-hole (PTH) vias for breakout routing. The dimension of PTH vias may vary as
necessary. Table 2.1 shows the recommended via dimension used for the breakout areas of BD71837MWV. Figure 4.4 shows the
image of PTH vias.
Table 4.1 Dimension example for PTH
Via type
Hole size
Pad size
Anti-Pad size
Plated through-hole (PTH)
12 mils
24 mils
32 mils
Hole size
Pad size
Anti-Pad size
Figure 4.4 The image of PTH vias

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Application Note
BD71837MWV Platform Design Guide
© 2018 ROHM Co., Ltd.
No. 61AN002E Rev.001
May.2018
4.6. Placement of PTHs underneath the exposed pad
When the distance between the edge of metal mask of the exposed pad and PTH is close, the solder may get on the resist then the
PTH and exposed pad of BD71837MWV will be shorted. To avoid the soldering issue, it is highly recommended to keep the positons
of PTHs away from the edge of the exposed pad by 500μm or more, and PTHs should be placed not to disrupt the current flows
between each GND of the output capacitors and the exposed pad.
Note
The spaces for the current flows between GNDs of each output capacitor and exposed pad for PMIC PGND should be ensured. So it
is recommended that the numbers of PTHs disturbing the current flows should be secured.
500
μ
m or more
Current
flow
Exposed pad
Figure 4.5 The clearance between PTH and the exposed pad

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Application Note
BD71837MWV Platform Design Guide
© 2018 ROHM Co., Ltd.
No. 61AN002E Rev.001
May.2018
4.7. Outline for PCB layout
For understanding the outline of ROHM’s reference layout, the layout data for Layer 1(Top Layer) to 6 (Bottom layer) are shown in
Figure 4.6 to Figure 4.11.
The layout is designed, supposing the position of the SoC as Figure 4.6.
(1st pin of SoC is positioned at lower right.)
BUCK8
BUCK5
BUCK1
MUXSW
BUCK7
BUCK2
BUCK3
BUCK4
BUCK6
i.MX 8M
Top layer is used as power trace for each VR.
It’s better to secure the power traces with enough width to
relief the effect of the parasitic impedance.
Figure 4.6 BD71837MWV Reference Board Outline (Top Layer)

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Application Note
BD71837MWV Platform Design Guide
© 2018 ROHM Co., Ltd.
No. 61AN002E Rev.001
May.2018
Figure 4.7 BD71837MWV Reference Board Outline (Layer 2)
GND
Layer 2 is used as power GND.
It’s better to secure the wide plane for large switching currents.
The parasitic impedance between PGND and each capacitor should be as low as possible.

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Application Note
BD71837MWV Platform Design Guide
© 2018 ROHM Co., Ltd.
No. 61AN002E Rev.001
May.2018
Figure 4.8 BD71837MWV Reference Board Outline (Layer 3)
VSYS
Layer 3 is used as VSYS power (Input for each VR).
It’s better to secure the wide plane for large input currents
which happens between input source and input capacitors.

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Application Note
BD71837MWV Platform Design Guide
© 2018 ROHM Co., Ltd.
No. 61AN002E Rev.001
May.2018
Figure 4.9 BD71837MWV Reference Board Outline (Layer 4)
Layer 4 is used as power traces for each VR.
It’s better to secure the enough width to relief the effect of
the parasitic impedance.

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Application Note
BD71837MWV Platform Design Guide
© 2018 ROHM Co., Ltd.
No. 61AN002E Rev.001
May.2018
Figure 4.10 BD71837MWV Reference Board Outline (Layer 5)
LDO4
LDO1
LDO2
LDO7
LDO3
LDO5
LDO6
Layer 5 is used as the power traces for each LDO.
It’s better to secure the enough width to relief the effect of
the parasitic impedance.

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Application Note
BD71837MWV Platform Design Guide
© 2018 ROHM Co., Ltd.
No. 61AN002E Rev.001
May.2018
Figure 4.11 BD71837MWV Reference Board Outline (Layer 6)
WDOG_B
SD_VSELECT
RTC_RESET_B
Layer 6 is used for routings of each feedback line and I/Os.
IRQ_B
POR_B
C32K_OUT

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Application Note
BD71837MWV Platform Design Guide
© 2018 ROHM Co., Ltd.
No. 61AN002E Rev.001
May.2018
5. Platform Power Delivery Guidelines
BD71837MWV is the PMIC that incorporates single BUCK regulators, LDOs, and the internal load switch.
It is essential to follow the guidelines to ensure the stable power delivery to the SoC and the system.
5.1. Platform Power Delivery
Figure 5.1 shows the voltages BD71837MWV provides to the SoC and other devices in the system and the information of the
maximum currents for each VR are summarized in Table 5.1.
Table 5.1 The Maximum Design Powers for BUCK convertors, LDOs, and the Load Switch
Voltage Rail
Type
Input Voltage
Default
Output Voltage
[V]
Max
Current
[mA]
Over Current
Protection
Min [mA]
BUCK1
Buck
VSYS
0.7 –1.3
3600
5000
BUCK2
Buck
VSYS
0.7 –1.3
4000
5500
BUCK3
Buck
VSYS
0.7 –1.3
2100
3000
BUCK4
Buck
VSYS
0.7 –1.3
1000
2500
BUCK5
Buck
VSYS
0.7 –1.35
2500
3500
BUCK6
Buck
VSYS
3.0 –3.3
3000
4500
BUCK7
Buck
VSYS
1.6 –2.0
1500
3000
BUCK8
Buck
VSYS
0.8 –1.4
3000
4500
LDO1
LDO
VSYS
1.6 –1.9
10
20
LDO2
LDO
VSYS
0.9 / 0.8
10
20
LDO3
LDO
BUCK6 / VSYS
1.8 –3.3
300
390
LDO4
LDO
BUCK7 / VSYS
0.9 –1.8
250
325
LDO5
LDO
BUCK6
1.8 –3.3
300
390
LDO6
LDO
BUCK7
0.9 –1.8
300
340
LDO7
LDO
VSYS
1.8 –3.3
150
195
MUXSW
Load Switch
1.8V / 3.3V
1.8 / 3.3
150
-

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Application Note
BD71837MWV Platform Design Guide
© 2018 ROHM Co., Ltd.
No. 61AN002E Rev.001
May.2018
Figure 5.1 BD71837MWV Power Delivery Map
0.9V
0.9V/1.0V
0.9V/1.0V
0.9V/1.0V
1.0V
3.3V
0.9V
3.3V
3.3V
1.8V
1.8V
1.8V
0.9V
0.9V
VSYS(5V)
1.1/1.2/1.35V
PMIC_STBY_REQ
HOST
I/F
32kHz
Xtal
Driver
150mA MUXSW
BD71837MWV
1.8V/3.3V(SD CARD)1.8V
3.3V
I2C I/F
WDOG_B
PMIC_ON_REQ
POR_B
RTC_RESET_B
SD_VSELECT
IRQ_B
XOUT
XIN
C32K_OUT
BUCK6
3.0A, 3.0 to 3.3V
/0.1V step
BUCK7
1.5A, 1.6V to 2.0V
/ 8steps
NVCC_DRAM
VDD_SOC
VDD_ARM
VDD_GPU
VDD_VPU
VDD_DRAM
NVCC_SNVS
3P3_PHY
GPIO_3V3
VDD_SNVS
VDDA_1P8
1P8_PHY
GPIO_1V8
VDDA_0P9
0P9_PHY
iMX8M
VDDA_DRAM
BUCK1 –DVS
3.6A, 0.7V to 1.3V
/10mV step
BUCK2 –DVS
4.0A, 0.7V to 1.3V
/10mV step
BUCK3 –DVS
2.1A, 0.7V to 1.3V
/10mV step
BUCK4 –DVS
1.0A,0.7V to 1.3V
/10mV step
BUCK5
2.5A,0.7V to 1.35V
/ 8steps
BUCK8
3.0A,0.8V to 1.4V
/10mV step
LDO1
10mA,3.0V to 3.3V
/1.6V to 1.9V
LDO2
10mA,
0.9V/0.8V
LDO7
150mA,
1.8V to 3.3V
LDO3
300mA,
1.8V to 3.3V
LDO5
300mA,
1.8V to 3.3V
LDO4
250mA,
0.9V to 1.8V
LDO6
300mA,
0.9V to 1.8V
PWRON_B

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Application Note
BD71837MWV Platform Design Guide
© 2018 ROHM Co., Ltd.
No. 61AN002E Rev.001
May.2018
5.2. General Layout Guideline
This section explains the guideline about the layout for voltage regulators. The voltage rails with higher Iomax current especially for
BUCK convertors should be carefully designed not to transmit the unwanted interference caused by switching noises to other signals
with high impedance.
And IR drop caused by large switching currents often influence the violation of the stability for the input level for each buck convertor
so the design for each input should be also taken care. It is highly recommended to follow the all guidelines in this section.
5.2.1. Overall Component Placement
Figure 5.2 shows the overall parts placement. The figure shows the positions of the components needed to be put closely to PMIC. It
is strongly recommended that the components controlling the higher currents like input / output capacitors and inductors are placed in
priority to any other components to guarantee the stabilities of each VR.
Figure 5.2 Overall component placement example
BUCK1
BUCK6
BCUK7
BUCK8
BUCK4
BUCK2
BUCK3
BUCK5
LDO4
LDO1
LDO5
MUXSW
LDO7
LDO3
LDO6