Rohm BU16028KV Instruction Manual

TECHNICAL NOTE
HDMI Switch ICs
3 for input 1 output switch with
Termination sense
correspondence
(Sync with HPD_SINK)
BU16028KV
●Description
BU16028KV is 3 for input 1 output HDMI/DVI switch LSI. Each port supports 2.25Gbps. (HDMI 1.3a)
This device control is simple. It requires only 3.3V source and a few GPIO controls.
Terminated resistors(50Ω) are integrated at input port. When channel is not selected, termination resistors are turned off.
TMDS inputs are high impedance.
This device is integrated equalization function and DDC buffer function, so it can adapt long cable.
●Features
・ Supports 2.25 Gbps signaling rate for 480i/p, 720i/p, and 1080i/p resolution to 12-bit color depth
・ Compatible with HDMI 1.3a
・ 5V tolerance to all DDC and HPD_SINK inputs
・ Integrated DDC buffer
・ Integrated switchable 50Ωreceiver termination
・ Integrated equalizer circuit to adapt long cable
・ HBM ESD protection exceeds 10kV
・ 3.3V fixed supply to TMDS I/Os
・ 64Pin VQFP package
・ ROHS compatible
●Applications
・ Digital TV
・ DVD Player
・ Set-Top-Box
・ Audio Video Receiver
・ Digital Projector
・ DVI or HDMI Switch Box
Sep. 2008

2/17
●OUTSIDE DIMENSION CHART
Fig. 1-1 . Outside dimension chart
Lot No.
BU16028K
V
1PIN MARK

3/17
●BLOCK DIAGRAM
B23
A24
B24
A23
A22
B22
A21
B21
B33
A34
B34
A33
A32
B32
A31
B31
B13 A14 B14 A13 A12 B12
A11
B11
Control Logic
TMDS
Drive
TMDS
Drive
TMDS
Drive
TMDS
Drive
Z4
Y4
Y3
Z3
Y2
Z2
Y1
Z1
S1
S2
HPD_SINK
SCL_SINK
SDA_SINK
HPD1
HPD2
HPD3
SCL1
SDA1
SCL2
SDA2
SCL3
SDA3
TMDS
RX
TMDS
RX
TMDS
RX
TMDS
RX
RINT
RINT
VCC
RINT
RINT
VCC
RINT
RINT
VCC
RINT
RINT
VCC
VSADJ
HPD_SINK
TMDS
RX
RINT RINT
VCC
TMDS
RX
RINT RINT
VCC
TMDS
RX
RINT RINT
VCC
TMDS
RX
RINT RINT
VCC
TMDS
RX
RINT RINT
VCC
TMDS
RX
RINT RINT
VCC
TMDS
RX
RINT RINT
VCC
TMDS
RX
RINT RINT
VCC
Fig. 2-1. Block Diagram

4/17
●PIN EXPLANATION
1). PIN ASSIGNMENT
(TOP VIEW)
BU16028KV
(64-pin VQFP)
Z3
Y1
Z2
Y2
GND
Y3
Z4
Y4
Z1
Vcc A12 GND A13 Vcc A14 B12 B13 B14
Vcc
B24
HPD3
Vcc B33
GND
B32 Vcc
GND
A33 A32 B31
SDA3
SCL3 46
37 38 39 40 41 42 43 44 45 48 47 34 33 36 35
28
27
26
25
24
32
31
30
29
3
12 11 10
9 8 7 6 5 4 1 2
14 13 16 15
A31
GND
B34
A34
VSADJ
SCL_SINK
GND
SDA_SINK
HPD_SINK
S1
Vcc
Vcc
A11 B11 SCL1 SDA1 HPD1 S2
B23
A23
SCL2
B21
A21
62
54
55
56
57
58
59
60
51
61
64
63
49
50
52
53
GND
Vcc
B22
A22
SDA2
Reserve2
HPD2
A24
19
23
22
21
20
17
18
Reserve1
1PIN
MARK
Fig3-1. Pin Location

5/17
2). PIN LIST
TERMINAL I/O DESCRIPTION
NAME No.
A11, A12, A13, A14 39, 42, 45, 48 I Source port 1 TMDS positive inputs
A21, A22, A23, A24 54, 57, 60, 63 I Source port 2 TMDS positive inputs
A31, A32, A33, A34 5, 8, 11, 14 I Source port 3 TMDS positive inputs
B11, B12, B13, B14 38, 41, 44, 47 I Source port 1 TMDS negative inputs
B21, B22, B23, B24 53, 56, 59, 62 I Source port 2 TMDS negative inputs
B31, B32, B33, B34 4, 7, 10, 13 I Source port 3 TMDS negative inputs
GND 3, 9, 15, 22, 28,
43, 58 - Ground
HPD1 35 O Source port 1 hot plug detector output (status pin)
HPD2 50 O Source port 2 hot plug detector output (status pin)
HPD3 64 O Source port 3 hot plug detector output (status pin)
HPD_SINK 31 I Sink port hot plug detector input (status pin)
Reserve1 34 I/O Set to HIGH/LOW/OPEN
Reserve2 49 I/O Non Connect Pin
SCL1 37 I/O Source port 1 DDC I2C clock line
SCL2 52 I/O Source port 2 DDC I2C clock line
SCL3 2 I/O Source port 3 DDC I2C clock line
SCL_SINK 29 I/O Sink port DDC I2C clock line
SDA1 36 I/O Source port 1 DDC I2C data line
SDA2 51 I/O Source port 2 DDC I2C data line
SDA3 1 I/O Source port 3 DDC I2C data line
SDA_SINK 30 I/O Sink port DDC I2C data line
S1, S2 32, 33 I Source selector
VCC 6, 12, 19, 25,
40, 46, 55, 61 - Power supply
VSADJ 16 I
TMDS compliant voltage swing control
(via 4.64kΩto GND)
Y1, Y2, Y3, Y4 26, 23, 20, 17 O Sink port TMDS positive outputs
Z1, Z2, Z3, Z4 27, 24, 21, 18 O Sink port TMDS negative outputs

6/17
●EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
50Ω
Anm Bnm
50Ω
VDD
TMDS Input Stage
Ym
Zm
10mA
TMDS Output Stage
R-Side I2C Input/Output Stage
SCL
SDA
VDD
VDD VDD
VDD
VDD
SCL_SINK
SDA_SINK HPD_SINK
HPDn
VDD
HPD Output Stage
T-Side I2C Input/Output Stage
※n=1,2,3 m=1,2,3,4
Fig. 4-1 . I/O pin schematic diagram

7/17
●SOURCE SELECTION LOOKUP TABLE
CONTROL PINS I/O SELECTED HOT PLUG DETECT STATUS
HPD_SINK S1 S2 Y/Z SCL_SINK
SDA_SINK HPD1 HPD2 HPD3
H H H
A1/B1
Terminations of A2/B2
and A3/B3 are
disconnected
SCL1
SDA1 H L L
H L H
A2/B2
Terminations of A1/B1
and A3/B3 are
disconnected
SCL2
SDA2 L H L
H L L
A3/B3
Terminations of A1/B1
and A2/B2 are
disconnected
SCL3
SDA3 L L H
H H L
None (Z)
All terminations are
disconnected
None (Z)
Are pulled HIGH by
external pull-up
termination
H H H
L H H
Disallowed
(indeterminate)State
All terminations are
disconnected
SCL1
SDA1 L L L
L L H
Disallowed
(indeterminate)State
All terminations are
disconnected
SCL2
SDA2 L L L
L L L
Disallowed
(indeterminate)State
All terminations are
disconnected
SCL3
SDA3 L L L
L H L
None (Z)
All terminations are
disconnected
None (Z)
Are pulled HIGH by
external pull-up
termination
L L L
(1)H: Logic high; L: Logic low; X: Don't care; Z: High impedance

8/17
●ERECTRICAL SPECIFICATIONS
1.）ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted)(1)
※70mm×70mm×1.6mm glass epoxy board mount.（Reverse Cu occupation rate：15mm×15mm）
When it’s used by than Ta=25℃, it’s reduced by 12.5mW/℃.
2.）RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
VCC Supply voltage 3 3.3 3.6 V
TA Operating free-air temperature 0 - 70 ℃
TMDS DIFFERENTIAL PINS
VIC Input common mode voltage VCC–0.6 - VCC+0.01 V
VID Receiver peak-to-peak differential input voltage 150 - 1560 mVp-p
RVSADJ Resistor for TMDS compliant voltage swing range 4.60 4.64 4.68 kΩ
AVCC TMDS Output termination voltage, see Figure 5-1. 3 3.3 3.6 V
RTTermination resistance, see Figure 5-1. 45 50 55 Ω
Signaling rate 0 - 2.25 Gbps
CONTROL PINS (S1,S2)
VIH LVTTL High-level input voltage 2 - VCC V
VIL LVTTL Low-level input voltage GND - 0.8 V
STATUS(HPD_SINK)
VIH LVTTL High-level input voltage 2.4 - 5.5 V
VIL LVTTL Low-level input voltage GND - 0.8 V
DDC I/O PINS Tx (SCL_SINK, SDA_SINK)
VIH High-level input voltage 2.1 - 5.5 V
VIL Low-level input voltage -0.3 - 0.35 V
DDC I/O PINS Rx (SCLn, SDAn) n = 1, 2, 3
VIH High-level input voltage 2.4 - 5.5 V
VIL Low-level input voltage -0.3 - 0.8 V
ITEM MIN. TYP. MAX. UNIT
Power supply voltage (Vcc) -0.3 - 4.0
V
DDC, HPD_SINK input voltage -0.3 - 6.0
V
Differential input voltage 2.5 - 4.0
V
S1, S2 input voltage -0.3 - 4.0
V
Power dissipation - - 1250
mW
Strage temperture range -55 - 125
℃

9/17
3.）ELECTRICAL CHARACTERISTICS
Over recommended operating conditions (unless otherwise noted)
SYMBOL PARAMETER TEST CONDITIONS LIMITS UNIT
MIN. TYP.(1) MAX.
Icc Supply current
VIH- = Vcc,VIL = Vcc-0.4V,RVSADJ =
4.64kΩ
RT = 50Ω,AVcc = 3.3V
Am/Bm = 2.25 Gbps HDMI data
pattern,
m = 2,3,4
A1,/B1 = 225 MHz clock
- 120 150 mA
PDPower dissipation
VIH = Vcc,VIL = Vcc-0.4V,RVSADJ =
4.64kΩ
RT = 50Ω,AVcc = 3.3V
Am/Bm = 2.25Gbps HDMI data
pattern,
m = 2,3,4
A1/B1 =255 MHZclock
- 450 600 mW
TMDS DIFFERENTIAL PINS (A/B;Y/Z)
VOH Single-ended high-level output
voltage
See Figure 5-2, AVcc = 3.3V,
RT = 50Ω
AVcc-
200 - Avcc-50 mV
VOL Single-ended low-level output
voltage
AVcc-
600 - Avcc-400 mV
VSWING Single-ended low-level swing
voltage 300 - 460 mV
Vod(O) Overshoot of output differential
voltage - 6% 15% 2xVswing
Vod(U) Undershoot of output
differential voltage - 12% 25% 2xVswing
VOD(ｐｐ)Steady state output differential
voltage
See Figure 5-2,
Am/Bm = 250 Mbps HDMI data
pattern ,
m = 2,3,4
A1/B1 = 25 MHz clock
600 - 920 mVp-p
RINT Input termination resistance VIN = 2.9V 45 50 55 Ω
⊿VOC（SS）
Change in steady-state
common-mode output voltage
between logic states
- 5 - mV

10/17
SYMBOL PARAMETER TEST CONDITIONS LIMITS UNIT
MIN. TYP.(1) MAX.
DDC Input and output
Tx
VIH High-level input voltage 2.1 - 5.5 V
VIL Low-level input voltage -0.3 - 0.35 V
IlKT
①
Input leak current, VI=5.5V -10 - 10 uA
IlKT
②
Input leak current, VI=Vcc -10 - 10 uA
IOHT High-level output current VO=3.6V -10 - 10 uA
IILT Low-level input current VIL=GND -10 - 10 uA
VOLT Low-level output voltage RL=4.7kΩ0.43 0.5 0.57 V
VOLT-VIL Low-level input voltage below
output low-level voltage 20 100 190 mV
Rx
VIH High-level input voltage 2.4 - 5.5 V
VIL Low-level input voltage -0.3 - 0.8 V
IlKR
①
Input leak current VI=5.5V -10 - 10 uA
IlKR
②
Input leak current VI=Vcc -10 - 10 uA
IOHR High-level output current VO=3.6V -10 - 10 uA
IILR Low-level input current VIL=GND -10 - 10 uA
VOLR Low-level output voltage Iout = 4mA - - 0.2 V
DDC Input and output
STATUS PINS (HPD 1, HPD 2, HPD 3)
VOH(TTL) TTL High –level output voltage IOH = -8mA 2.4 - Vcc V
VOL(TTL) TTL Low –level output voltage IOL = 8mA 0 - 0.4 V
CONTROL PINS (S1, S2 )
IIH High –level digital input current VIH = Vcc -10 - 10 uA
IIL Low –level digital input current VIL = GND -10 - 10 uA
STATUS PINS (HPD_SINK)
IIH High –level digital input current VIH = 5.5V 10 50 100 uA
VIH = Vcc 5 30 80 uA
IIL Low –level digital input current VIL = GND -10 - 10 uA

11/17
SYMBOL PARAMETER TEST CONDITIONS LIMITS UNIT
MIN. TYP.(1) MAX.
TMDS DIFFERENTIAL PINS (Y/Z)
tPLH Propagation delay time
low-high-level output
See Figure 5-2, AVCC = 3.3V,
RT= 50Ω
- 480 - ps
tPHL Propagation delay time
low-high-level output - 500 - ps
trDifferential output signal rise
time (20%-80%) - 150 - ps
tfDifferential output signal fall
time (20%-80%) - 150 - ps
tsk(p) Pulse skew (|tPHL - tPLH |) - 20 - ps
tsk(D) Intra-pair differential skew,
see Figure 5-3. - 50 - ps
tsk(o) Inter-pair channel-to-channel
output skew - 50 - ps
tsk(pp) Part to part skew - 400 - ps
DDC I/O PINS (SCL, SCL_SINK, SDA, SDA_SINK)
tpdLHTR
(DDC)
Propagation delay time,
low-to-high-level output
Tx to Rx RL= 4.7kΩ CL= 100pF
- 650 - ns
tpdHLTR
(DDC)
Propagation delay time,
high-to-low-level output
Tx to Rx
- 200 - ns
tpdLHRT
(DDC)
Propagation delay time,
low-to-high-level output
Rx to Tx RL= 1.67kΩ CL= 400pF
- 500 - ns
tpdHLRT
(DDC)
Propagation delay time,
high-to-low-level output
Rx to Tx
- 350 - ns
tr Tx(DDC) Tx output Rise time RL= 4.7kΩ CL= 100pF - 800 - ns
tf Tx(DDC) Tx output Fall time - 150 - ns
tr Rx(DDC) Rx output Rise time RL= 1.67kΩ CL= 400pF - 950 - ns
tf Rx(DDC) Rx output Fall time - 50 - ns
tsx Select to switch output - 8 - ns
tdis Disable time - 5 - ns
ten Enable time - 7 - ns
tsx(DDC) Switch time from SCLn to
SCL_SINK CL=10pF - 800 - Ns
STATUS PINS (HPD1,HPD2,HPD3)
tpdLH(HPD)
Propagation delay time,
low-to-high-level output from
HPD_SINK to HPDn(n=1,2,3)
CL=10pF - 5 - ns
tpdHL(HPD)
Propagation delay time,
high-to-low-level output from
HPD_SINK to HPDn(n=1,2,3)
CL=10pF - 5 - ns
tsx(HPD) Switch time from port select to
the latest valid status of HPD CL=10pF - 8 - ns
Note:
1. All typical values are at 25℃and with a 3.3V supply.

12/17
●MEASUREMENT SYMBOL AND CIRCUIT
Figure 5-1. Termination for TMDS Output Driver
VA
VID
Vcc-0.4 V Vcc-0.2 V
0.4 V
0 V
-0.4 V
VID(pp)
VIC
VOD(pp)
tf
80%
20%
VOD(U)
0%
0V Differential
100%
tPLH
VOC
tr
VOD(O)
△VOC(SS)
VB
Vswing
tPLH
Vcc V Vcc+0.2 V
DC Coupled AC Coupled
Figure 5-2. Timing Test Circuit and Definitions
Zo = RT
Zo = RT
TMDS
Driver
TMDS
Receiver
AVCC
RTRT
TMDS
Receiver
TMDS
Driver
VID
Vcc
RINT RINT
A
B
RT
RTAVCC
CL
Y
Z
0.5pF VY
VZ
VA
VB
Vswing = VY-VZVID = VA-VB

13/17
Figure 5-3. Definition of Intra-Pair Differential Skew
Figure 5-4.TMDS Outputs Control Timing Definitions
S1
Clocking
S2
A
B
A
B
A
B
75mV
-75mV HI-Z
75mV
-75mV
tsx
ten
Y
Z
Output
2
VDD
0V
VDD
tsx
tdis
Port 1
Port 2
Port 3
Vcc-0.4 V
Vcc V
Vcc-0.4 V
Vcc V
Vcc-0.4 V
Vcc V
tsk(D)
50%
VY
VZ
VOH
VOL

14/17
tpdHL(HPD) tpdLH(HPD)
2
VDD
2
VDD
2.4V
tsx(HPD)
0V
2
Vcc
tpdHLRT(DDC) tpdLHRT(DDC)
HPD_SINK
HPD1
HPD2
HPD3
S1
S2
SDA_SINK
SDA1
SDA2
SDA3
VDD
1.5V
tSX(DDC)
1.5V
VDD
0V
tpdHLTR(DDC) tpdLHTR(DDC)
tfTX(DDC) trTX(DDC) tfRX(DDC) trRX(DDC)
80%
20%
80%
20%
RX to TX TX to RX
VIL
Figure 5-5. DDC and HPD Timing Definitions

15/17
1). Y and Z terminal ESD Diode notice.
Y and Z terminals are connected ESD diode.
When VCC＋0.4 < AVCC.
BU16028KV flow leak current from AVCC to VCC.
In order to minimize leak current.
Please use following application.
If you use “Repeater” or “output Buffer”
AVCC
power down
controler
VCC
BU16028KV
Low Vsat TR Tx side
need more than
10mA load
VCC
10kΩ
GND(3pin)
HPD2
Figure 6-1. Ist mode application
2). HPD_SINK Pull down resistance.
HPD_SINK is a 5V tolerant structure shown in Fig6-2.
It needs some drive current to pull down HPD_SINK "H" to "L"(max10uA@HPD_SINK=2V).
So to pull down HPD_SINK, please use 10kΩ(or under 10kΩ) resistor.
Figure 6-2. HPD_SINK I/O schematic
10kΩ
VCC
HPD_SINK
BU16028KV

16/17
3). About don’t use terminal.
Unused TMDS input channel can be opened.
Figure 6-3. TMDS Input Fail-Safe Recommendation
Unused DDC Buffers of R side pull up to Vdd .
Figure 6-4. DDC Buffers in BU16028KV
4）. About serial connect notice.
When HDMI sw output connect to other HDMI sw input like following application.
There is possibility that. 1080p(12bit) image isn’t displayed. It‘s depend on receiver IC characteristic.
When system is required 1080p (12bit), Rohm doesn’t recommend serial connect application.
.
TMDS
Receiver
TMDS
Driver
Vcc
RINT RINT
Y
Z
A
B
Y
Z
RT
RT
TMDS
Receiver
TMDS
Driver
Vcc
RINT RINT
Y
Z
A
B
AVCC
Fig6-5 serial connect notice
TMDS
Receiver
TMDS
Driver
Vcc
R
INT
R
INT
BU16028KV
Y
Z
R
T
R
T
AVcc
A
B
T
R
VCC
RSCL
RSDA
TSCL
TSDA
4.7k

Catalog No.08T220B'08.9 ROHM ©
1pin
<Packing information>
（Unit:mm)
<Dimension>
VQ
FP64
48 33
32
17
16
1
49
64
10.0 ±0.1
12.0 ±0.2
10.0 ±0.1 12.0 ±0.2
0.145
0.5 ±0.15
0.1 ±0.05 1.4 ±0.05
1.25
1.25
1.0 ±0.2
1.6Max.
+0.05
−0.04
0.2
0.5 ±0.1
4
°
+6
°
−4
°
+0.05
−0.03
0.08 S
0.08
M
※When you order , please order in times the amount of package quantity.
Containe
r
Quantit
y
Direction
of feed
Tray(with dry pack)
1000pcs
Direction of product is fixed in a tray.

Notes
No technical content pages of this document may be reproduced in any form or transmitted by any
means without prior permission of ROHM CO.,LTD.
The contents described herein are subject to change without notice. The specifications for the
product described in this document are for reference only. Upon actual use, therefore, please request
that specifications to be separately delivered.
Application circuit diagrams and circuit constants contained herein are shown as examples of standard
use and operation. Please pay careful attention to the peripheral conditions when designing circuits
and deciding upon circuit constants in the set.
Any data, including, but not limited to application circuit diagrams information, described herein
are intended only as illustrations of such devices and not as the specifications for such devices. ROHM
CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any
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whatsoever nature in the event of any such infringement, or arising from or connected with or related
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exploit any intellectual property rights or other proprietary rights owned or controlled by
ROHM CO., LTD. is granted to any such buyer.
Products listed in this document are no antiradiation design.
Appendix1-Rev2.0
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It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance
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for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in
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cannot be held responsible for any damages arising from the use of the products under conditions out of the
range of the specifications or due to non-compliance with the NOTES specified in this catalog.
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Appendix